[coreboot-gerrit] New patch to review for coreboot: src/vendorcode/amd/cimx: Unify all filenames
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Sat Jun 20 01:49:27 CEST 2015
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10602
-gerrit
commit 21d040efc15b599d2482c16c4f0332bbba8e91df
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date: Fri Jun 19 16:27:52 2015 -0700
src/vendorcode/amd/cimx: Unify all filenames
This changes the file name schema to be consistent
and similar to what the newest release (sb900) does.
Change-Id: Ia890930661ae33281f2be99b896d1a576eed1d5c
Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
---
src/vendorcode/amd/cimx/sb700/ACPILIB.c | 120 ---
src/vendorcode/amd/cimx/sb700/ACPILIB.h | 61 --
src/vendorcode/amd/cimx/sb700/AMDLIB.c | 434 -----------
src/vendorcode/amd/cimx/sb700/AMDSBLIB.c | 276 -------
src/vendorcode/amd/cimx/sb700/AZALIA.c | 304 --------
src/vendorcode/amd/cimx/sb700/AcpiLib.c | 120 +++
src/vendorcode/amd/cimx/sb700/AcpiLib.h | 61 ++
src/vendorcode/amd/cimx/sb700/AmdLib.c | 434 +++++++++++
src/vendorcode/amd/cimx/sb700/AmdSbLib.c | 276 +++++++
src/vendorcode/amd/cimx/sb700/Azalia.c | 304 ++++++++
src/vendorcode/amd/cimx/sb700/DEBUG.c | 169 -----
src/vendorcode/amd/cimx/sb700/DISPATCHER.c | 208 -----
src/vendorcode/amd/cimx/sb700/Debug.c | 169 +++++
src/vendorcode/amd/cimx/sb700/Dispatcher.c | 208 +++++
src/vendorcode/amd/cimx/sb700/EC.c | 132 ----
src/vendorcode/amd/cimx/sb700/Ec.c | 132 ++++
src/vendorcode/amd/cimx/sb700/FLASH.c | 58 --
src/vendorcode/amd/cimx/sb700/Flash.c | 58 ++
src/vendorcode/amd/cimx/sb700/LEGACY.c | 38 -
src/vendorcode/amd/cimx/sb700/Legacy.c | 38 +
src/vendorcode/amd/cimx/sb700/Makefile.inc | 62 +-
src/vendorcode/amd/cimx/sb700/SATA.c | 453 -----------
src/vendorcode/amd/cimx/sb700/SBCMN.c | 572 --------------
src/vendorcode/amd/cimx/sb700/SBCMNLIB.c | 108 ---
src/vendorcode/amd/cimx/sb700/SBCMNLIB.h | 89 ---
src/vendorcode/amd/cimx/sb700/SBDEF.h | 166 ----
src/vendorcode/amd/cimx/sb700/SBMAIN.c | 289 -------
src/vendorcode/amd/cimx/sb700/SBPort.c | 441 -----------
src/vendorcode/amd/cimx/sb700/SBTYPE.h | 249 ------
src/vendorcode/amd/cimx/sb700/SMM.c | 91 ---
src/vendorcode/amd/cimx/sb700/Sata.c | 453 +++++++++++
src/vendorcode/amd/cimx/sb700/SbAmdLib.h | 196 +++++
src/vendorcode/amd/cimx/sb700/SbCmn.c | 572 ++++++++++++++
src/vendorcode/amd/cimx/sb700/SbCmnLib.c | 108 +++
src/vendorcode/amd/cimx/sb700/SbCmnLib.h | 89 +++
src/vendorcode/amd/cimx/sb700/SbDef.h | 166 ++++
src/vendorcode/amd/cimx/sb700/SbMain.c | 289 +++++++
src/vendorcode/amd/cimx/sb700/SbPort.c | 441 +++++++++++
src/vendorcode/amd/cimx/sb700/SbType.h | 249 ++++++
src/vendorcode/amd/cimx/sb700/Smm.c | 91 +++
src/vendorcode/amd/cimx/sb700/USB.c | 187 -----
src/vendorcode/amd/cimx/sb700/Usb.c | 187 +++++
src/vendorcode/amd/cimx/sb700/sbAMDLIB.h | 196 -----
src/vendorcode/amd/cimx/sb800/ACPILIB.c | 166 ----
src/vendorcode/amd/cimx/sb800/ACPILIB.h | 69 --
src/vendorcode/amd/cimx/sb800/AMDLIB.c | 92 ---
src/vendorcode/amd/cimx/sb800/AMDSBLIB.c | 152 ----
src/vendorcode/amd/cimx/sb800/AMDSBLIB.h | 122 ---
src/vendorcode/amd/cimx/sb800/AZALIA.c | 512 -------------
src/vendorcode/amd/cimx/sb800/AcpiLib.c | 166 ++++
src/vendorcode/amd/cimx/sb800/AcpiLib.h | 69 ++
src/vendorcode/amd/cimx/sb800/AmdLib.c | 92 +++
src/vendorcode/amd/cimx/sb800/AmdSbLib.c | 152 ++++
src/vendorcode/amd/cimx/sb800/AmdSbLib.h | 122 +++
src/vendorcode/amd/cimx/sb800/Azalia.c | 512 +++++++++++++
src/vendorcode/amd/cimx/sb800/DISPATCHER.c | 252 ------
src/vendorcode/amd/cimx/sb800/Dispatcher.c | 252 ++++++
src/vendorcode/amd/cimx/sb800/EC.c | 131 ----
src/vendorcode/amd/cimx/sb800/ECLIB.c | 156 ----
src/vendorcode/amd/cimx/sb800/ECfan.h | 70 --
src/vendorcode/amd/cimx/sb800/ECfanLIB.c | 96 ---
src/vendorcode/amd/cimx/sb800/ECfanc.c | 204 -----
src/vendorcode/amd/cimx/sb800/Ec.c | 131 ++++
src/vendorcode/amd/cimx/sb800/EcFan.h | 70 ++
src/vendorcode/amd/cimx/sb800/EcFanLib.c | 96 +++
src/vendorcode/amd/cimx/sb800/EcFanc.c | 204 +++++
src/vendorcode/amd/cimx/sb800/EcLib.c | 156 ++++
src/vendorcode/amd/cimx/sb800/GEC.c | 145 ----
src/vendorcode/amd/cimx/sb800/Gec.c | 145 ++++
src/vendorcode/amd/cimx/sb800/IOLIB.c | 91 ---
src/vendorcode/amd/cimx/sb800/IoLib.c | 91 +++
src/vendorcode/amd/cimx/sb800/LEGACY.c | 47 --
src/vendorcode/amd/cimx/sb800/Legacy.c | 47 ++
src/vendorcode/amd/cimx/sb800/MEMLIB.c | 96 ---
src/vendorcode/amd/cimx/sb800/Makefile.inc | 86 +--
src/vendorcode/amd/cimx/sb800/MemLib.c | 96 +++
src/vendorcode/amd/cimx/sb800/PCILIB.c | 86 ---
src/vendorcode/amd/cimx/sb800/PMIO2LIB.c | 130 ----
src/vendorcode/amd/cimx/sb800/PMIOLIB.c | 129 ----
src/vendorcode/amd/cimx/sb800/PciLib.c | 86 +++
src/vendorcode/amd/cimx/sb800/Pmio2Lib.c | 130 ++++
src/vendorcode/amd/cimx/sb800/PmioLib.c | 129 ++++
src/vendorcode/amd/cimx/sb800/SATA.c | 675 -----------------
src/vendorcode/amd/cimx/sb800/SBCMN.c | 1066 --------------------------
src/vendorcode/amd/cimx/sb800/SBDEF.h | 261 -------
src/vendorcode/amd/cimx/sb800/SBMAIN.c | 258 -------
src/vendorcode/amd/cimx/sb800/SBPELIB.c | 198 -----
src/vendorcode/amd/cimx/sb800/SBPort.c | 366 ---------
src/vendorcode/amd/cimx/sb800/SBSUBFUN.h | 523 -------------
src/vendorcode/amd/cimx/sb800/SBTYPE.h | 1135 ----------------------------
src/vendorcode/amd/cimx/sb800/SMM.c | 86 ---
src/vendorcode/amd/cimx/sb800/Sata.c | 675 +++++++++++++++++
src/vendorcode/amd/cimx/sb800/SbCmn.c | 1066 ++++++++++++++++++++++++++
src/vendorcode/amd/cimx/sb800/SbDef.h | 261 +++++++
src/vendorcode/amd/cimx/sb800/SbMain.c | 258 +++++++
src/vendorcode/amd/cimx/sb800/SbPeLib.c | 198 +++++
src/vendorcode/amd/cimx/sb800/SbPort.c | 366 +++++++++
src/vendorcode/amd/cimx/sb800/SbSubFun.h | 523 +++++++++++++
src/vendorcode/amd/cimx/sb800/SbType.h | 1135 ++++++++++++++++++++++++++++
src/vendorcode/amd/cimx/sb800/Smm.c | 86 +++
src/vendorcode/amd/cimx/sb800/USB.c | 431 -----------
src/vendorcode/amd/cimx/sb800/Usb.c | 431 +++++++++++
src/vendorcode/amd/cimx/sb900/Makefile.inc | 4 +-
src/vendorcode/amd/cimx/sb900/SBPort.c | 737 ------------------
src/vendorcode/amd/cimx/sb900/SbPort.c | 737 ++++++++++++++++++
105 files changed, 13199 insertions(+), 13199 deletions(-)
diff --git a/src/vendorcode/amd/cimx/sb700/ACPILIB.c b/src/vendorcode/amd/cimx/sb700/ACPILIB.c
deleted file mode 100644
index 807b166..0000000
--- a/src/vendorcode/amd/cimx/sb700/ACPILIB.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*****************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *
- ***************************************************************************/
-
-
-#include "Platform.h"
-
-/*++
-
-Routine Description:
-
- Locate ACPI table
-
-Arguments:
-
- Signature - table signature
-
-Returns:
-
- pointer to ACPI table
-
---*/
-void* ACPI_LocateTable(
- UINT32 Signature
-)
-{
- UINT32 i;
- UINT32* RsdPtr = (UINT32*)0xe0000;
- UINT32* Rsdt = NULL;
- DESCRIPTION_HEADER* CurrentTable;
- do{
-// if (*RsdPtr == ' DSR' && *(RsdPtr+1) == ' RTP'){
- if ((*RsdPtr == Int32FromChar ('R', 'S', 'D', ' ')) && (*(RsdPtr+1) == Int32FromChar ('R', 'T', 'P', ' '))){
- Rsdt = (UINT32*)((RSDP*)RsdPtr)->RsdtAddress;
- break;
- }
- RsdPtr+=4;
- }while (RsdPtr <= (UINT32*)0xffff0);
- if(Rsdt != NULL && ACPI_GetTableChecksum(Rsdt)==0){
- for (i = 0;i < (((DESCRIPTION_HEADER*)Rsdt)->Length - sizeof(DESCRIPTION_HEADER))/4;i++){
- CurrentTable = (DESCRIPTION_HEADER*)*(UINT32*)((UINT8*)Rsdt + sizeof(DESCRIPTION_HEADER) + i*4);
- if (CurrentTable->Signature == Signature) return CurrentTable;
- }
- }
- return NULL;
-}
-
-/*++
-
-Routine Description:
-
- Update table checksum
-
-Arguments:
-
- TablePtr - table pointer
-
-Returns:
-
- none
-
---*/
-void ACPI_SetTableChecksum(
- void* TablePtr
-)
-{
- UINT8 Checksum = 0;
- ((DESCRIPTION_HEADER*)TablePtr)->Checksum = 0;
- Checksum = ACPI_GetTableChecksum(TablePtr);
- ((DESCRIPTION_HEADER*)TablePtr)->Checksum = 0x100 - Checksum;
-}
-
-/*++
-
-Routine Description:
-
- Get table checksum
-
-Arguments:
-
- TablePtr - table pointer
-
-Returns:
-
- none
-
---*/
-UINT8 ACPI_GetTableChecksum(
- void* TablePtr
-)
-{
- return GetByteSum(TablePtr,((DESCRIPTION_HEADER*)TablePtr)->Length);
-}
-
diff --git a/src/vendorcode/amd/cimx/sb700/ACPILIB.h b/src/vendorcode/amd/cimx/sb700/ACPILIB.h
deleted file mode 100644
index 5f2734f..0000000
--- a/src/vendorcode/amd/cimx/sb700/ACPILIB.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*;********************************************************************************
-;
-; Copyright (C) 2012 Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#ifndef _AMD_ACPILIB_H_
-#define _AMD_ACPILIB_H_
-
-typedef struct _RSDP{
- UINT64 Signature;
- UINT8 Checksum;
- UINT8 OEMID[6];
- UINT8 Revision;
- UINT32 RsdtAddress;
- UINT32 Length;
- UINT64 XsdtAddress;
- UINT8 ExtendedChecksum;
- UINT8 Reserved[3];
-}RSDP;
-
-typedef struct _DESCRIPTION_HEADER{
- UINT32 Signature;
- UINT32 Length;
- UINT8 Revision;
- UINT8 Checksum;
- UINT8 OEMID[6];
- UINT8 OEMTableID[8];
- UINT32 OEMRevision;
- UINT32 CreatorID;
- UINT32 CreatorRevision;
-}DESCRIPTION_HEADER;
-
-void* ACPI_LocateTable(UINT32 Signature);
-void ACPI_SetTableChecksum(void* TablePtr);
-UINT8 ACPI_GetTableChecksum(void* TablePtr);
-
-#endif //ifndef _AMD_ACPILIB_H_
diff --git a/src/vendorcode/amd/cimx/sb700/AMDLIB.c b/src/vendorcode/amd/cimx/sb700/AMDLIB.c
deleted file mode 100644
index b233259..0000000
--- a/src/vendorcode/amd/cimx/sb700/AMDLIB.c
+++ /dev/null
@@ -1,434 +0,0 @@
-/*****************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *
- ***************************************************************************/
-
-
-
-#include "Platform.h"
-
-VOID
-ReadIO (
- IN UINT16 Address,
- IN UINT8 OpFlag,
- IN VOID* Value
- )
-{
- OpFlag = OpFlag & 0x7f;
- switch ( OpFlag ) {
- case AccWidthUint8:
- *(UINT8*)Value = ReadIo8 (Address);
- break;
- case AccWidthUint16:
- *(UINT16*)Value = ReadIo16 (Address);
- break;
- case AccWidthUint32:
- *(UINT32*)Value = ReadIo32 (Address);
- break;
- default:
- break;
- }
-}
-
-VOID
-WriteIO (
- IN UINT16 Address,
- IN UINT8 OpFlag,
- IN VOID* Value
- )
-{
- OpFlag = OpFlag & 0x7f;
- switch ( OpFlag ) {
- case AccWidthUint8:
- WriteIo8 (Address, *(UINT8*)Value);
- break;
- case AccWidthUint16:
- WriteIo16 (Address, *(UINT16*)Value);
- break;
- case AccWidthUint32:
- WriteIo32 (Address, *(UINT32*)Value);
- break;
- default:
- break;
- }
-}
-
-VOID
-RWIO (
- IN UINT16 Address,
- IN UINT8 OpFlag,
- IN UINT32 Mask,
- IN UINT32 Data
- )
-{
- UINT32 Result;
- ReadIO (Address, OpFlag, &Result);
- Result = (Result & Mask) | Data;
- WriteIO (Address, OpFlag, &Result);
-}
-
-
-VOID
-ReadPCI (
- IN UINT32 Address,
- IN UINT8 OpFlag,
- IN VOID* Value
- )
-{
- OpFlag = OpFlag & 0x7f;
-
- if ( (UINT16)Address < 0xff ) {
- //Normal Config Access
- UINT32 AddrCf8;
- AddrCf8 = (1 << 31) + ((Address >> 8) & 0x0FFFF00) + (Address & 0xFC);
- WriteIO (0xCf8, AccWidthUint32, &AddrCf8);
- ReadIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value);
- }
-}
-
-VOID
-WritePCI (
- IN UINT32 Address,
- IN UINT8 OpFlag,
- IN VOID* Value
- )
-{
- OpFlag = OpFlag & 0x7f;
- if ( (UINT16)Address < 0xff ) {
- //Normal Config Access
- UINT32 AddrCf8;
- AddrCf8 = (1 << 31) + ((Address >> 8)&0x0FFFF00) + (Address & 0xFC);
- WriteIO (0xCf8, AccWidthUint32, &AddrCf8);
- WriteIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value);
- }
-}
-
-VOID
-RWPCI (
- IN UINT32 Address,
- IN UINT8 OpFlag,
- IN UINT32 Mask,
- IN UINT32 Data
- )
-{
- UINT32 Result;
- Result = 0;
- OpFlag = OpFlag & 0x7f;
- ReadPCI (Address, OpFlag, &Result);
- Result = (Result & Mask) | Data;
- WritePCI (Address, OpFlag, &Result);
-}
-
-void
-ReadIndexPCI32 (
-UINT32 PciAddress,
-UINT32 IndexAddress,
-void* Value
-)
-{
- WritePCI(PciAddress,AccWidthUint32,&IndexAddress);
- ReadPCI(PciAddress+4,AccWidthUint32,Value);
-}
-
-void
-WriteIndexPCI32 (
-UINT32 PciAddress,
-UINT32 IndexAddress,
-UINT8 OpFlag,
-void* Value
-)
-{
-
- WritePCI(PciAddress,AccWidthUint32 | (OpFlag & 0x80),&IndexAddress);
- WritePCI(PciAddress+4,AccWidthUint32 | (OpFlag & 0x80) ,Value);
-}
-
-void
-RWIndexPCI32 (
-UINT32 PciAddress,
-UINT32 IndexAddress,
-UINT8 OpFlag,
-UINT32 Mask,
-UINT32 Data
-)
-{
- UINT32 Result;
- ReadIndexPCI32(PciAddress,IndexAddress,&Result);
- Result = (Result & Mask)| Data;
- WriteIndexPCI32(PciAddress,IndexAddress,(OpFlag & 0x80),&Result);
-
-}
-
-void
-ReadMEM (
-UINT32 Address,
-UINT8 OpFlag,
-void* Value
-)
-{
- OpFlag = OpFlag & 0x7f;
- switch (OpFlag){
- case AccWidthUint8 : *((UINT8*)Value)=*((UINT8*)Address);break;
- case AccWidthUint16: *((UINT16*)Value)=*((UINT16*)Address);break;
- case AccWidthUint32: *((UINT32*)Value)=*((UINT32*)Address);break;
- }
-}
-
-void
-WriteMEM (
-UINT32 Address,
-UINT8 OpFlag,
-void* Value
-)
-{
- OpFlag = OpFlag & 0x7f;
- switch (OpFlag){
- case AccWidthUint8 : *((UINT8*)Address)=*((UINT8*)Value);break;
- case AccWidthUint16: *((UINT16*)Address)=*((UINT16*)Value);break;
- case AccWidthUint32: *((UINT32*)Address)=*((UINT32*)Value);break;
- }
-}
-
-void
-RWMEM (
-UINT32 Address,
-UINT8 OpFlag,
-UINT32 Mask,
-UINT32 Data
-)
-{
- UINT32 Result;
- ReadMEM(Address,OpFlag,&Result);
- Result = (Result & Mask)| Data;
- WriteMEM(Address,OpFlag,&Result);
-}
-
-
-void
-RWMSR(
-UINT32 Address,
-UINT64 Mask,
-UINT64 Value
-)
-{
- MsrWrite(Address,(MsrRead(Address)& Mask)|Value);
-}
-
-UINT32
-IsFamily10()
-{
- CPUID_DATA Cpuid;
- CpuidRead(0x1,(CPUID_DATA *)&Cpuid);
-
- return Cpuid.REG_EAX & 0xff00000;
-}
-
-
-UINT8 GetNumberOfCpuCores(void)
-{
- UINT8 Result=1;
- Result=ReadNumberOfCpuCores();
- return Result;
-}
-
-
-void
-Stall(
-UINT32 uSec
-)
-{
- UINT16 timerAddr;
- UINT32 startTime, elapsedTime;
- ReadPMIO(SB_PMIO_REG24, AccWidthUint16, &timerAddr);
-
- if (timerAddr ==0){
- uSec = uSec/2;
- while (uSec!=0){
- ReadIO(0x80,AccWidthUint8,(UINT8 *)(&startTime));
- uSec--;
- }
- }
- else{
- ReadIO(timerAddr, AccWidthUint32,&startTime);
- while (1){
- ReadIO(timerAddr, AccWidthUint32,&elapsedTime);
- if (elapsedTime < startTime)
- elapsedTime = elapsedTime+0xFFFFFFFF-startTime;
- else
- elapsedTime = elapsedTime-startTime;
- if ((elapsedTime*28/100)>uSec)
- break;
- }
- }
-}
-
-
-void
-Reset(
-)
-{
- RWIO(0xcf9,AccWidthUint8,0x0,0x06);
-}
-
-
-CIM_STATUS
-RWSMBUSBlock(
-UINT8 Controller,
-UINT8 Address,
-UINT8 Offset,
-UINT8 BufferSize,
-UINT8* BufferPrt
-)
-{
- UINT16 SmbusPort;
- UINT8 i;
- UINT8 Status;
- ReadPCI(PCI_ADDRESS(0,0x14,0,Controller?0x58:0x10),AccWidthUint16,&SmbusPort);
- SmbusPort &= 0xfffe;
- RWIO(SmbusPort + 0,AccWidthUint8,0x0,0xff);
- RWIO(SmbusPort + 4,AccWidthUint8,0x0,Address);
- RWIO(SmbusPort + 3,AccWidthUint8,0x0,Offset);
- RWIO(SmbusPort + 2,AccWidthUint8,0x0,0x14);
- RWIO(SmbusPort + 5,AccWidthUint8,0x0,BufferSize);
- if(!(Address & 0x1)){
- for (i = 0 ;i < BufferSize;i++){
- WriteIO(SmbusPort + 7,AccWidthUint8,&BufferPrt[i]);
- }
- }
- RWIO(SmbusPort + 2,AccWidthUint8,0x0,0x54);
- do{
- ReadIO(SmbusPort + 0,AccWidthUint8,&Status);
- if (Status & 0x1C) return CIM_ERROR;
- if (Status & 0x02) break;
- }while(!(Status & 0x1));
-
- do{
- ReadIO(SmbusPort + 0,AccWidthUint8,&Status);
- }while(Status & 0x1);
-
- if(Address & 0x1){
- for (i = 0 ;i < BufferSize;i++){
- ReadIO(SmbusPort + 7,AccWidthUint8,&BufferPrt[i]);
- }
- }
- return CIM_SUCCESS;
-}
-
-
-
-void outPort80(UINT32 pcode)
-{
- WriteIO(0x80, AccWidthUint8, &pcode);
- return;
-}
-
-
-UINT8
-GetByteSum(
- void* pData,
- UINT32 Length
-)
-{
- UINT32 i;
- UINT8 Checksum = 0;
- for (i = 0;i < Length;i++){
- Checksum += *((UINT8*)pData+i);
- }
- return Checksum;
-}
-
-
-UINT32
-readAlink(
- UINT32 Index
-){
- UINT32 Data;
- WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index);
- ReadIO(ALINK_ACCESS_DATA, AccWidthUint32, &Data);
- //Clear Index
- Index=0;
- WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index);
- return Data;
-}
-
-
-void
-writeAlink(
- UINT32 Index,
- UINT32 Data
-){
- WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index);
- WriteIO(ALINK_ACCESS_DATA, AccWidthUint32, &Data);
- //Clear Index
- Index=0;
- WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index);
-
-}
-
-
-/**
- *
- * IsServer - Determine if southbridge type is SP5100 (server) or SB7x0 (non-server)
- *
- * A SP5100 is determined when both following two items are true:
- * 1) Revision >= A14;
- * 2) A server north bridge chipset is detected;
- *
- * A list of server north bridge chipset:
- *
- * Family DeviceID
- * ----------------------
- * SR5690 0x5A10
- * SR5670 0x5A12
- * SR5650 0x5A13
- *
- */
-UINT8
-IsServer (void){
- UINT16 DevID;
-
- if (getRevisionID () < SB700_A14) {
- return 0;
- }
- ReadPCI ((NB_BDF << 16) + 2, AccWidthUint16, &DevID);
- return ((DevID == 0x5a10) || (DevID == 0x5a12) || (DevID == 0x5a13))? 1: 0;
-}
-
-/**
- *
- * IsLS2Mode - Determine if LS2 mode is enabled or not in northbridge.
- *
- */
-UINT8
-IsLs2Mode (void)
-{
- UINT32 HT3LinkTraining0;
-
- ReadPCI ((NB_BDF << 16) + 0xAC, AccWidthUint32, &HT3LinkTraining0);
- return ( HT3LinkTraining0 & 0x100 )? 1: 0;
-}
diff --git a/src/vendorcode/amd/cimx/sb700/AMDSBLIB.c b/src/vendorcode/amd/cimx/sb700/AMDSBLIB.c
deleted file mode 100644
index bf4f06a..0000000
--- a/src/vendorcode/amd/cimx/sb700/AMDSBLIB.c
+++ /dev/null
@@ -1,276 +0,0 @@
-/*****************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *
- ***************************************************************************/
-
-
-#include "Platform.h"
-
-
-void
-ReadPMIO (
-UINT8 Address,
-UINT8 OpFlag,
-void* Value
-)
-{
- UINT8 i;
-
- OpFlag = OpFlag & 0x7f;
- if (OpFlag == 0x02) OpFlag = 0x03;
- for (i=0;i<=OpFlag;i++){
- WriteIO(0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6
- Address++;
- ReadIO(0xCD7, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD7
- }
-}
-
-
-void
-WritePMIO (
-UINT8 Address,
-UINT8 OpFlag,
-void* Value
-)
-{
- UINT8 i;
-
- OpFlag = OpFlag & 0x7f;
- if (OpFlag == 0x02) OpFlag = 0x03;
- for (i=0;i<=OpFlag;i++){
- WriteIO(0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6
- Address++;
- WriteIO(0xCD7, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD7
- }
-}
-
-
-void
-RWPMIO (
-UINT8 Address,
-UINT8 OpFlag,
-UINT32 AndMask,
-UINT32 OrMask
-)
-{
- UINT32 Result;
-
- OpFlag = OpFlag & 0x7f;
- ReadPMIO(Address,OpFlag,&Result);
- Result = (Result & AndMask)| OrMask;
- WritePMIO(Address,OpFlag,&Result);
-}
-
-
-void
-ReadPMIO2 (
-UINT8 Address,
-UINT8 OpFlag,
-void* Value
-)
-{
- UINT8 i;
-
- OpFlag = OpFlag & 0x7f;
- if (OpFlag == 0x02) OpFlag = 0x03;
- for (i=0;i<=OpFlag;i++){
- WriteIO(0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0
- Address++;
- ReadIO(0xCD1, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD1
- }
-}
-
-
-void
-WritePMIO2 (
-UINT8 Address,
-UINT8 OpFlag,
-void* Value
-)
-{
- UINT8 i;
-
- OpFlag = OpFlag & 0x7f;
- if (OpFlag == 0x02) OpFlag = 0x03;
- for (i=0;i<=OpFlag;i++){
- WriteIO(0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0
- Address++;
- WriteIO(0xCD1, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD1
- }
-}
-
-
-void
-RWPMIO2 (
-UINT8 Address,
-UINT8 OpFlag,
-UINT32 AndMask,
-UINT32 OrMask
-)
-{
- UINT32 Result;
-
- OpFlag = OpFlag & 0x7f;
- ReadPMIO2(Address,OpFlag,&Result);
- Result = (Result & AndMask)| OrMask;
- WritePMIO2(Address,OpFlag,&Result);
-}
-
-
-void
-EnterEcConfig()
-{
- UINT16 dwEcIndexPort;
-
- ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
- dwEcIndexPort &= ~(UINT16)(BIT0);
- RWIO(dwEcIndexPort, AccWidthUint8, 0x00, 0x5A);
-}
-
-void
-ExitEcConfig()
-{
- UINT16 dwEcIndexPort;
-
- ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
- dwEcIndexPort &= ~(UINT16)(BIT0);
- RWIO(dwEcIndexPort, AccWidthUint8, 0x00, 0xA5);
-}
-
-
-void
-ReadEC8 (
-UINT8 Address,
-UINT8* Value
-)
-{
- UINT16 dwEcIndexPort;
-
- ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
- dwEcIndexPort &= ~(UINT16)(BIT0);
- WriteIO(dwEcIndexPort, AccWidthUint8, &Address); // SB_IOMAP_REGCD6
- ReadIO(dwEcIndexPort+1, AccWidthUint8, Value); // SB_IOMAP_REGCD7
-}
-
-
-void
-WriteEC8 (
-UINT8 Address,
-UINT8* Value
-)
-{
- UINT16 dwEcIndexPort;
-
- ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
- dwEcIndexPort &= ~(UINT16)(BIT0);
- WriteIO(dwEcIndexPort, AccWidthUint8, &Address); // SB_IOMAP_REGCD6
- WriteIO(dwEcIndexPort+1, AccWidthUint8, Value); // SB_IOMAP_REGCD7
-}
-
-
-void
-RWEC8 (
-UINT8 Address,
-UINT8 AndMask,
-UINT8 OrMask
-)
-{
- UINT8 Result;
- ReadEC8(Address,&Result);
- Result = (Result & AndMask)| OrMask;
- WriteEC8(Address, &Result);
-}
-
-
-void
-programPciByteTable (
-REG8MASK* pPciByteTable,
-UINT16 dwTableSize
-)
-{
- UINT8 i, dbBusNo, dbDevFnNo;
- UINT32 ddBDFR;
-
- dbBusNo = pPciByteTable->bRegIndex;
- dbDevFnNo = pPciByteTable->bANDMask;
- pPciByteTable++;
- for (i = 1; i < dwTableSize; i++){
- if ( (pPciByteTable->bRegIndex==0xFF) && (pPciByteTable->bANDMask==0xFF) && (pPciByteTable->bORMask==0xFF) ){
- pPciByteTable++;
- dbBusNo = pPciByteTable->bRegIndex;
- dbDevFnNo = pPciByteTable->bANDMask;
- }
- else{
- ddBDFR = (dbBusNo << 24) + (dbDevFnNo << 16) + (pPciByteTable->bRegIndex) ;
- TRACE((DMSG_SB_TRACE, "PFA=%X AND=%X, OR=%X\n", ddBDFR, pPciByteTable->bANDMask, pPciByteTable->bORMask));
- RWPCI(ddBDFR, AccWidthUint8 | S3_SAVE, pPciByteTable->bANDMask, pPciByteTable->bORMask);
- pPciByteTable++;
- }
- }
-}
-
-
-void
-programPmioByteTable (
-REG8MASK* pPmioByteTable,
-UINT16 dwTableSize
-)
-{
- UINT8 i;
- for (i = 0; i < dwTableSize; i++){
- TRACE((DMSG_SB_TRACE, "PMIO Reg = %X AndMask = %X OrMask = %X\n",pPmioByteTable->bRegIndex,pPmioByteTable->bANDMask, pPmioByteTable->bORMask));
- RWPMIO(pPmioByteTable->bRegIndex, AccWidthUint8 , pPmioByteTable->bANDMask, pPmioByteTable->bORMask);
- pPmioByteTable++;
- }
-}
-
-
-UINT8
-getClockMode (
-void
-)
-{
- UINT8 dbTemp=0;
-
- RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT7);
- ReadPMIO(SB_PMIO_REGB0, AccWidthUint8, &dbTemp);
- return(dbTemp&BIT4);
-}
-
-
-UINT16
-readStrapStatus (
-void
-)
-{
- UINT16 dwTemp=0;
-
- RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT7);
- ReadPMIO(SB_PMIO_REGB0, AccWidthUint16, &dwTemp);
- return(dwTemp);
-}
diff --git a/src/vendorcode/amd/cimx/sb700/AZALIA.c b/src/vendorcode/amd/cimx/sb700/AZALIA.c
deleted file mode 100644
index cc72858..0000000
--- a/src/vendorcode/amd/cimx/sb700/AZALIA.c
+++ /dev/null
@@ -1,304 +0,0 @@
-/*****************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *
- ***************************************************************************/
-
-
-
-#include "Platform.h"
-
-void configureAzaliaPinCmd (AMDSBCFG* pConfig, UINT32 ddBAR0, UINT8 dbChannelNum);
-void configureAzaliaSetConfigD4Dword(CODECENTRY* tempAzaliaCodecEntryPtr, UINT32 ddChannelNum, UINT32 ddBAR0);
-
-//Pin Config for ALC880, ALC882 and ALC883:
-CODECENTRY AzaliaCodecAlc882Table[] = {
- {0x14, 0x01014010},
- {0x15, 0x01011012},
- {0x16, 0x01016011},
- {0x17, 0x01012014},
- {0x18, 0x01A19030},
- {0x19, 0x411111F0},
- {0x1a, 0x01813080},
- {0x1b, 0x411111F0},
- {0x1C, 0x411111F0},
- {0x1d, 0x411111F0},
- {0x1e, 0x01441150},
- {0x1f, 0x01C46160},
- {0xff, 0xffffffff}
-};
-
-
-//Pin Config for ALC262
-CODECENTRY AzaliaCodecAlc262Table[] = {
- {0x14, 0x01014010},
- {0x15, 0x411111F0},
- {0x16, 0x411111F0},
-// {0x17, 0x01012014},
- {0x18, 0x01A19830},
- {0x19, 0x02A19C40},
- {0x1a, 0x01813031},
- {0x1b, 0x02014C20},
- {0x1c, 0x411111F0},
- {0x1d, 0x411111F0},
- {0x1e, 0x0144111E},
- {0x1f, 0x01C46150},
- {0xff, 0xffffffff}
-};
-
-//Pin Config for ALC0861:
-CODECENTRY AzaliaCodecAlc861Table[] = {
- {0x01, 0x8086C601},
- {0x0B, 0x01014110},
- {0x0C, 0x01813140},
- {0x0D, 0x01A19941},
- {0x0E, 0x411111F0},
- {0x0F, 0x02214420},
- {0x10, 0x02A1994E},
- {0x11, 0x99330142},
- {0x12, 0x01451130},
- {0x1F, 0x411111F0},
- {0x20, 0x411111F0},
- {0x23, 0x411111F0},
- {0xff, 0xffffffff}
-};
-
-//Pin Config for ADI1984:
-CODECENTRY AzaliaCodecAd1984Table[] = {
- {0x11, 0x0221401F},
- {0x12, 0x90170110},
- {0x13, 0x511301F0},
- {0x14, 0x02A15020},
- {0x15, 0x50A301F0},
- {0x16, 0x593301F0},
- {0x17, 0x55A601F0},
- {0x18, 0x55A601F0},
- {0x1A, 0x91F311F0},
- {0x1B, 0x014511A0},
- {0x1C, 0x599301F0},
- {0xff, 0xffffffff}
-};
-
-
-CODECENTRY FrontPanelAzaliaCodecTableList[] = {
- {0x19, 0x02A19040},
- {0x1b, 0x02214020},
- {0xff, 0xffffffff}
-};
-
-
-CODECTBLLIST azaliaCodecTableList[] = {
- {0x010ec0880, &AzaliaCodecAlc882Table[0]},
- {0x010ec0882, &AzaliaCodecAlc882Table[0]},
- {0x010ec0883, &AzaliaCodecAlc882Table[0]},
- {0x010ec0885, &AzaliaCodecAlc882Table[0]},
- {0x010ec0262, &AzaliaCodecAlc262Table[0]},
- {0x010ec0861, &AzaliaCodecAlc861Table[0]},
- {0x011d41984, &AzaliaCodecAd1984Table[0]},
- {(UINT32)0x0FFFFFFFF, (CODECENTRY*)0xFFFFFFFF}
-};
-
-
-/*-------------------------------------------------------------------------------
-; Procedure: azaliaInitAfterPciEnum
-;
-; Description: This routine detects Azalia and, if present, initializes Azalia
-; This routine is called from atiSbAfterPciInit
-;
-;
-; Exit: None
-;
-; Modified: None
-;
-;-----------------------------------------------------------------------------
-*/
-void azaliaInitAfterPciEnum (AMDSBCFG* pConfig){
- UINT8 i, dbEnableAzalia=0, dbPinRouting, dbChannelNum=0, dbTempVariable = 0;
- UINT16 dwTempVariable = 0;
- UINT32 ddBAR0, ddTempVariable = 0;
-
- if (pConfig->AzaliaController == 1) return;
-
- if (pConfig->AzaliaController != 1){
- RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT1, BIT1);
- ReadPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0);
-
- if (ddBAR0 != 0){ //Keep the flag as disabled if BAR is 0 or all "F"s.
- if (ddBAR0 != 0xFFFFFFFF){
- ddBAR0 &= ~(0x03FFF);
- dbEnableAzalia = 1;
- TRACE((DMSG_SB_TRACE, "CIMxSB - Enabling Azalia controller (BAR setup is ok) \n"));
- }
- }
- }
-
- if (dbEnableAzalia){ //if Azalia is enabled
- //Get SDIN Configuration
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGF8, AccWidthUint32 | S3_SAVE, 0, ddTempVariable);
- ddTempVariable |= (pConfig->AzaliaSdin3 << 6);
- ddTempVariable |= (pConfig->AzaliaSdin2 << 4);
- ddTempVariable |= (pConfig->AzaliaSdin1 << 2);
- ddTempVariable |= pConfig->AzaliaSdin0;
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8 | S3_SAVE, 0, (ddTempVariable & 0xFF));
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+3, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT2+BIT1+BIT0), 0);
-
- i=11;
- do{
- ReadMEM( ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
- dbTempVariable |= BIT0;
- WriteMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
- Stall(1000);
- ReadMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
- i--;
- } while ( (!(dbTempVariable & BIT0)) && (i > 0) );
-
- if (i==0){
- TRACE((DMSG_SB_TRACE, "CIMxSB - Problem in resetting Azalia controller\n"));
- return;
- }
-
- Stall(1000);
- ReadMEM( ddBAR0+SB_AZ_BAR_REG0E, AccWidthUint16, &dwTempVariable);
- if (dwTempVariable & 0x0F){
- TRACE((DMSG_SB_TRACE, "CIMxSB - Atleast One Azalia CODEC found \n"));
- //atleast one azalia codec found
- ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8, &dbPinRouting);
- do{
- if ( ( !(dbPinRouting & BIT0) ) && (dbPinRouting & BIT1) )
- configureAzaliaPinCmd(pConfig, ddBAR0, dbChannelNum);
- dbPinRouting >>= 2;
- dbChannelNum++;
- } while (dbChannelNum != 4);
- }
- else{
- TRACE((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC NOT found \n"));
- //No Azalia codec found
- if (pConfig->AzaliaController != 2)
- dbEnableAzalia = 0; //set flag to disable Azalia
- }
- }
-
- if (dbEnableAzalia){
- //redo clear reset
- do{
- dwTempVariable = 0;
- WriteMEM( ddBAR0+SB_AZ_BAR_REG0C, AccWidthUint16 | S3_SAVE, &dwTempVariable);
- ReadMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
- dbTempVariable &= ~(UINT8)(BIT0);
- WriteMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
- ReadMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
- } while (dbTempVariable & BIT0);
-
- if (pConfig->AzaliaSnoop == 1)
- RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG42, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0);
- }
- else{
- //disable Azalia controller
- RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint16 | S3_SAVE, 0, 0);
- RWPMIO(SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 0);
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8 | S3_SAVE, 0, 0x55);
- }
-}
-
-
-void configureAzaliaPinCmd (AMDSBCFG* pConfig, UINT32 ddBAR0, UINT8 dbChannelNum){
- UINT32 ddTempVariable, ddChannelNum;
- CODECTBLLIST* ptempAzaliaOemCodecTablePtr;
- CODECENTRY* tempAzaliaCodecEntryPtr;
-
- if ((pConfig->AzaliaPinCfg) != 1)
- return;
-
- ddChannelNum = dbChannelNum << 28;
- ddTempVariable = 0xF0000;
- ddTempVariable |= ddChannelNum;
- WriteMEM(ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddTempVariable);
- Stall(60);
- ReadMEM(ddBAR0 + SB_AZ_BAR_REG64, AccWidthUint32 | S3_SAVE, &ddTempVariable);
-
- if ( ((pConfig->pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) 0xFFFFFFFF)) )
- ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) FIXUP_PTR(&azaliaCodecTableList[0]);
- else
- ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) pConfig->pAzaliaOemCodecTablePtr;
-
- TRACE((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC table pointer is %x \n", (UINT32)ptempAzaliaOemCodecTablePtr));
-
- while ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF){
- if ( ptempAzaliaOemCodecTablePtr->CodecID == ddTempVariable)
- break;
- else
- ++ptempAzaliaOemCodecTablePtr;
- }
-
- if ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF){
- TRACE((DMSG_SB_TRACE, "CIMxSB - Matching CODEC ID found \n"));
- tempAzaliaCodecEntryPtr = (CODECENTRY*) ptempAzaliaOemCodecTablePtr->CodecTablePtr;
- TRACE((DMSG_SB_TRACE, "CIMxSB - Matching Azalia CODEC table pointer is %x \n", (UINT32)tempAzaliaCodecEntryPtr));
-
- if ( ((pConfig->pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) 0xFFFFFFFF)) )
- tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR(tempAzaliaCodecEntryPtr);
-
- configureAzaliaSetConfigD4Dword(tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0);
- if (pConfig->AzaliaFrontPanel != 1){
- if ( (pConfig->AzaliaFrontPanel == 2) || (pConfig->FrontPanelDetected == 1) ){
- if ( ((pConfig->pAzaliaOemFpCodecTableptr) == NULL) || ((pConfig->pAzaliaOemFpCodecTableptr) == 0xFFFFFFFF))
- tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR(&FrontPanelAzaliaCodecTableList[0]);
- else
- tempAzaliaCodecEntryPtr = (CODECENTRY*) pConfig->pAzaliaOemFpCodecTableptr;
- configureAzaliaSetConfigD4Dword(tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0);
- }
- }
- }
-}
-
-
-void configureAzaliaSetConfigD4Dword(CODECENTRY* tempAzaliaCodecEntryPtr, UINT32 ddChannelNum, UINT32 ddBAR0){
- UINT8 dbtemp1,dbtemp2, i;
- UINT32 ddtemp=0,ddtemp2=0;
-
- while ((tempAzaliaCodecEntryPtr->Nid) != 0xFF){
- dbtemp1=0x20;
- if ((tempAzaliaCodecEntryPtr->Nid) == 0x1)
- dbtemp1=0x24;
- ddtemp = tempAzaliaCodecEntryPtr->Nid;
- ddtemp &= 0xff;
- ddtemp <<= 20;
- ddtemp |= ddChannelNum;
- ddtemp |= (0x700 << 8);
- for(i=4; i>0; i--){
- do{
- ReadMEM(ddBAR0 + SB_AZ_BAR_REG68, AccWidthUint32, &ddtemp2);
- } while (ddtemp2 & BIT0);
- dbtemp2 = ( (tempAzaliaCodecEntryPtr->Byte40) >> ((4-i) * 8 ) ) & 0xff;
- ddtemp = (ddtemp & 0xFFFF0000)+ ((dbtemp1 - i) << 8) + dbtemp2;
- WriteMEM(ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddtemp);
- Stall(60);
- }
- ++tempAzaliaCodecEntryPtr;
- }
-}
-
diff --git a/src/vendorcode/amd/cimx/sb700/AcpiLib.c b/src/vendorcode/amd/cimx/sb700/AcpiLib.c
new file mode 100644
index 0000000..807b166
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/AcpiLib.c
@@ -0,0 +1,120 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+/*++
+
+Routine Description:
+
+ Locate ACPI table
+
+Arguments:
+
+ Signature - table signature
+
+Returns:
+
+ pointer to ACPI table
+
+--*/
+void* ACPI_LocateTable(
+ UINT32 Signature
+)
+{
+ UINT32 i;
+ UINT32* RsdPtr = (UINT32*)0xe0000;
+ UINT32* Rsdt = NULL;
+ DESCRIPTION_HEADER* CurrentTable;
+ do{
+// if (*RsdPtr == ' DSR' && *(RsdPtr+1) == ' RTP'){
+ if ((*RsdPtr == Int32FromChar ('R', 'S', 'D', ' ')) && (*(RsdPtr+1) == Int32FromChar ('R', 'T', 'P', ' '))){
+ Rsdt = (UINT32*)((RSDP*)RsdPtr)->RsdtAddress;
+ break;
+ }
+ RsdPtr+=4;
+ }while (RsdPtr <= (UINT32*)0xffff0);
+ if(Rsdt != NULL && ACPI_GetTableChecksum(Rsdt)==0){
+ for (i = 0;i < (((DESCRIPTION_HEADER*)Rsdt)->Length - sizeof(DESCRIPTION_HEADER))/4;i++){
+ CurrentTable = (DESCRIPTION_HEADER*)*(UINT32*)((UINT8*)Rsdt + sizeof(DESCRIPTION_HEADER) + i*4);
+ if (CurrentTable->Signature == Signature) return CurrentTable;
+ }
+ }
+ return NULL;
+}
+
+/*++
+
+Routine Description:
+
+ Update table checksum
+
+Arguments:
+
+ TablePtr - table pointer
+
+Returns:
+
+ none
+
+--*/
+void ACPI_SetTableChecksum(
+ void* TablePtr
+)
+{
+ UINT8 Checksum = 0;
+ ((DESCRIPTION_HEADER*)TablePtr)->Checksum = 0;
+ Checksum = ACPI_GetTableChecksum(TablePtr);
+ ((DESCRIPTION_HEADER*)TablePtr)->Checksum = 0x100 - Checksum;
+}
+
+/*++
+
+Routine Description:
+
+ Get table checksum
+
+Arguments:
+
+ TablePtr - table pointer
+
+Returns:
+
+ none
+
+--*/
+UINT8 ACPI_GetTableChecksum(
+ void* TablePtr
+)
+{
+ return GetByteSum(TablePtr,((DESCRIPTION_HEADER*)TablePtr)->Length);
+}
+
diff --git a/src/vendorcode/amd/cimx/sb700/AcpiLib.h b/src/vendorcode/amd/cimx/sb700/AcpiLib.h
new file mode 100644
index 0000000..5f2734f
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/AcpiLib.h
@@ -0,0 +1,61 @@
+/*;********************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; * Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; * Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; * Neither the name of Advanced Micro Devices, Inc. nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*********************************************************************************/
+
+#ifndef _AMD_ACPILIB_H_
+#define _AMD_ACPILIB_H_
+
+typedef struct _RSDP{
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OEMID[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
+}RSDP;
+
+typedef struct _DESCRIPTION_HEADER{
+ UINT32 Signature;
+ UINT32 Length;
+ UINT8 Revision;
+ UINT8 Checksum;
+ UINT8 OEMID[6];
+ UINT8 OEMTableID[8];
+ UINT32 OEMRevision;
+ UINT32 CreatorID;
+ UINT32 CreatorRevision;
+}DESCRIPTION_HEADER;
+
+void* ACPI_LocateTable(UINT32 Signature);
+void ACPI_SetTableChecksum(void* TablePtr);
+UINT8 ACPI_GetTableChecksum(void* TablePtr);
+
+#endif //ifndef _AMD_ACPILIB_H_
diff --git a/src/vendorcode/amd/cimx/sb700/AmdLib.c b/src/vendorcode/amd/cimx/sb700/AmdLib.c
new file mode 100644
index 0000000..b233259
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/AmdLib.c
@@ -0,0 +1,434 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+
+#include "Platform.h"
+
+VOID
+ReadIO (
+ IN UINT16 Address,
+ IN UINT8 OpFlag,
+ IN VOID* Value
+ )
+{
+ OpFlag = OpFlag & 0x7f;
+ switch ( OpFlag ) {
+ case AccWidthUint8:
+ *(UINT8*)Value = ReadIo8 (Address);
+ break;
+ case AccWidthUint16:
+ *(UINT16*)Value = ReadIo16 (Address);
+ break;
+ case AccWidthUint32:
+ *(UINT32*)Value = ReadIo32 (Address);
+ break;
+ default:
+ break;
+ }
+}
+
+VOID
+WriteIO (
+ IN UINT16 Address,
+ IN UINT8 OpFlag,
+ IN VOID* Value
+ )
+{
+ OpFlag = OpFlag & 0x7f;
+ switch ( OpFlag ) {
+ case AccWidthUint8:
+ WriteIo8 (Address, *(UINT8*)Value);
+ break;
+ case AccWidthUint16:
+ WriteIo16 (Address, *(UINT16*)Value);
+ break;
+ case AccWidthUint32:
+ WriteIo32 (Address, *(UINT32*)Value);
+ break;
+ default:
+ break;
+ }
+}
+
+VOID
+RWIO (
+ IN UINT16 Address,
+ IN UINT8 OpFlag,
+ IN UINT32 Mask,
+ IN UINT32 Data
+ )
+{
+ UINT32 Result;
+ ReadIO (Address, OpFlag, &Result);
+ Result = (Result & Mask) | Data;
+ WriteIO (Address, OpFlag, &Result);
+}
+
+
+VOID
+ReadPCI (
+ IN UINT32 Address,
+ IN UINT8 OpFlag,
+ IN VOID* Value
+ )
+{
+ OpFlag = OpFlag & 0x7f;
+
+ if ( (UINT16)Address < 0xff ) {
+ //Normal Config Access
+ UINT32 AddrCf8;
+ AddrCf8 = (1 << 31) + ((Address >> 8) & 0x0FFFF00) + (Address & 0xFC);
+ WriteIO (0xCf8, AccWidthUint32, &AddrCf8);
+ ReadIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value);
+ }
+}
+
+VOID
+WritePCI (
+ IN UINT32 Address,
+ IN UINT8 OpFlag,
+ IN VOID* Value
+ )
+{
+ OpFlag = OpFlag & 0x7f;
+ if ( (UINT16)Address < 0xff ) {
+ //Normal Config Access
+ UINT32 AddrCf8;
+ AddrCf8 = (1 << 31) + ((Address >> 8)&0x0FFFF00) + (Address & 0xFC);
+ WriteIO (0xCf8, AccWidthUint32, &AddrCf8);
+ WriteIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value);
+ }
+}
+
+VOID
+RWPCI (
+ IN UINT32 Address,
+ IN UINT8 OpFlag,
+ IN UINT32 Mask,
+ IN UINT32 Data
+ )
+{
+ UINT32 Result;
+ Result = 0;
+ OpFlag = OpFlag & 0x7f;
+ ReadPCI (Address, OpFlag, &Result);
+ Result = (Result & Mask) | Data;
+ WritePCI (Address, OpFlag, &Result);
+}
+
+void
+ReadIndexPCI32 (
+UINT32 PciAddress,
+UINT32 IndexAddress,
+void* Value
+)
+{
+ WritePCI(PciAddress,AccWidthUint32,&IndexAddress);
+ ReadPCI(PciAddress+4,AccWidthUint32,Value);
+}
+
+void
+WriteIndexPCI32 (
+UINT32 PciAddress,
+UINT32 IndexAddress,
+UINT8 OpFlag,
+void* Value
+)
+{
+
+ WritePCI(PciAddress,AccWidthUint32 | (OpFlag & 0x80),&IndexAddress);
+ WritePCI(PciAddress+4,AccWidthUint32 | (OpFlag & 0x80) ,Value);
+}
+
+void
+RWIndexPCI32 (
+UINT32 PciAddress,
+UINT32 IndexAddress,
+UINT8 OpFlag,
+UINT32 Mask,
+UINT32 Data
+)
+{
+ UINT32 Result;
+ ReadIndexPCI32(PciAddress,IndexAddress,&Result);
+ Result = (Result & Mask)| Data;
+ WriteIndexPCI32(PciAddress,IndexAddress,(OpFlag & 0x80),&Result);
+
+}
+
+void
+ReadMEM (
+UINT32 Address,
+UINT8 OpFlag,
+void* Value
+)
+{
+ OpFlag = OpFlag & 0x7f;
+ switch (OpFlag){
+ case AccWidthUint8 : *((UINT8*)Value)=*((UINT8*)Address);break;
+ case AccWidthUint16: *((UINT16*)Value)=*((UINT16*)Address);break;
+ case AccWidthUint32: *((UINT32*)Value)=*((UINT32*)Address);break;
+ }
+}
+
+void
+WriteMEM (
+UINT32 Address,
+UINT8 OpFlag,
+void* Value
+)
+{
+ OpFlag = OpFlag & 0x7f;
+ switch (OpFlag){
+ case AccWidthUint8 : *((UINT8*)Address)=*((UINT8*)Value);break;
+ case AccWidthUint16: *((UINT16*)Address)=*((UINT16*)Value);break;
+ case AccWidthUint32: *((UINT32*)Address)=*((UINT32*)Value);break;
+ }
+}
+
+void
+RWMEM (
+UINT32 Address,
+UINT8 OpFlag,
+UINT32 Mask,
+UINT32 Data
+)
+{
+ UINT32 Result;
+ ReadMEM(Address,OpFlag,&Result);
+ Result = (Result & Mask)| Data;
+ WriteMEM(Address,OpFlag,&Result);
+}
+
+
+void
+RWMSR(
+UINT32 Address,
+UINT64 Mask,
+UINT64 Value
+)
+{
+ MsrWrite(Address,(MsrRead(Address)& Mask)|Value);
+}
+
+UINT32
+IsFamily10()
+{
+ CPUID_DATA Cpuid;
+ CpuidRead(0x1,(CPUID_DATA *)&Cpuid);
+
+ return Cpuid.REG_EAX & 0xff00000;
+}
+
+
+UINT8 GetNumberOfCpuCores(void)
+{
+ UINT8 Result=1;
+ Result=ReadNumberOfCpuCores();
+ return Result;
+}
+
+
+void
+Stall(
+UINT32 uSec
+)
+{
+ UINT16 timerAddr;
+ UINT32 startTime, elapsedTime;
+ ReadPMIO(SB_PMIO_REG24, AccWidthUint16, &timerAddr);
+
+ if (timerAddr ==0){
+ uSec = uSec/2;
+ while (uSec!=0){
+ ReadIO(0x80,AccWidthUint8,(UINT8 *)(&startTime));
+ uSec--;
+ }
+ }
+ else{
+ ReadIO(timerAddr, AccWidthUint32,&startTime);
+ while (1){
+ ReadIO(timerAddr, AccWidthUint32,&elapsedTime);
+ if (elapsedTime < startTime)
+ elapsedTime = elapsedTime+0xFFFFFFFF-startTime;
+ else
+ elapsedTime = elapsedTime-startTime;
+ if ((elapsedTime*28/100)>uSec)
+ break;
+ }
+ }
+}
+
+
+void
+Reset(
+)
+{
+ RWIO(0xcf9,AccWidthUint8,0x0,0x06);
+}
+
+
+CIM_STATUS
+RWSMBUSBlock(
+UINT8 Controller,
+UINT8 Address,
+UINT8 Offset,
+UINT8 BufferSize,
+UINT8* BufferPrt
+)
+{
+ UINT16 SmbusPort;
+ UINT8 i;
+ UINT8 Status;
+ ReadPCI(PCI_ADDRESS(0,0x14,0,Controller?0x58:0x10),AccWidthUint16,&SmbusPort);
+ SmbusPort &= 0xfffe;
+ RWIO(SmbusPort + 0,AccWidthUint8,0x0,0xff);
+ RWIO(SmbusPort + 4,AccWidthUint8,0x0,Address);
+ RWIO(SmbusPort + 3,AccWidthUint8,0x0,Offset);
+ RWIO(SmbusPort + 2,AccWidthUint8,0x0,0x14);
+ RWIO(SmbusPort + 5,AccWidthUint8,0x0,BufferSize);
+ if(!(Address & 0x1)){
+ for (i = 0 ;i < BufferSize;i++){
+ WriteIO(SmbusPort + 7,AccWidthUint8,&BufferPrt[i]);
+ }
+ }
+ RWIO(SmbusPort + 2,AccWidthUint8,0x0,0x54);
+ do{
+ ReadIO(SmbusPort + 0,AccWidthUint8,&Status);
+ if (Status & 0x1C) return CIM_ERROR;
+ if (Status & 0x02) break;
+ }while(!(Status & 0x1));
+
+ do{
+ ReadIO(SmbusPort + 0,AccWidthUint8,&Status);
+ }while(Status & 0x1);
+
+ if(Address & 0x1){
+ for (i = 0 ;i < BufferSize;i++){
+ ReadIO(SmbusPort + 7,AccWidthUint8,&BufferPrt[i]);
+ }
+ }
+ return CIM_SUCCESS;
+}
+
+
+
+void outPort80(UINT32 pcode)
+{
+ WriteIO(0x80, AccWidthUint8, &pcode);
+ return;
+}
+
+
+UINT8
+GetByteSum(
+ void* pData,
+ UINT32 Length
+)
+{
+ UINT32 i;
+ UINT8 Checksum = 0;
+ for (i = 0;i < Length;i++){
+ Checksum += *((UINT8*)pData+i);
+ }
+ return Checksum;
+}
+
+
+UINT32
+readAlink(
+ UINT32 Index
+){
+ UINT32 Data;
+ WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index);
+ ReadIO(ALINK_ACCESS_DATA, AccWidthUint32, &Data);
+ //Clear Index
+ Index=0;
+ WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index);
+ return Data;
+}
+
+
+void
+writeAlink(
+ UINT32 Index,
+ UINT32 Data
+){
+ WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index);
+ WriteIO(ALINK_ACCESS_DATA, AccWidthUint32, &Data);
+ //Clear Index
+ Index=0;
+ WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index);
+
+}
+
+
+/**
+ *
+ * IsServer - Determine if southbridge type is SP5100 (server) or SB7x0 (non-server)
+ *
+ * A SP5100 is determined when both following two items are true:
+ * 1) Revision >= A14;
+ * 2) A server north bridge chipset is detected;
+ *
+ * A list of server north bridge chipset:
+ *
+ * Family DeviceID
+ * ----------------------
+ * SR5690 0x5A10
+ * SR5670 0x5A12
+ * SR5650 0x5A13
+ *
+ */
+UINT8
+IsServer (void){
+ UINT16 DevID;
+
+ if (getRevisionID () < SB700_A14) {
+ return 0;
+ }
+ ReadPCI ((NB_BDF << 16) + 2, AccWidthUint16, &DevID);
+ return ((DevID == 0x5a10) || (DevID == 0x5a12) || (DevID == 0x5a13))? 1: 0;
+}
+
+/**
+ *
+ * IsLS2Mode - Determine if LS2 mode is enabled or not in northbridge.
+ *
+ */
+UINT8
+IsLs2Mode (void)
+{
+ UINT32 HT3LinkTraining0;
+
+ ReadPCI ((NB_BDF << 16) + 0xAC, AccWidthUint32, &HT3LinkTraining0);
+ return ( HT3LinkTraining0 & 0x100 )? 1: 0;
+}
diff --git a/src/vendorcode/amd/cimx/sb700/AmdSbLib.c b/src/vendorcode/amd/cimx/sb700/AmdSbLib.c
new file mode 100644
index 0000000..bf4f06a
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/AmdSbLib.c
@@ -0,0 +1,276 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+
+void
+ReadPMIO (
+UINT8 Address,
+UINT8 OpFlag,
+void* Value
+)
+{
+ UINT8 i;
+
+ OpFlag = OpFlag & 0x7f;
+ if (OpFlag == 0x02) OpFlag = 0x03;
+ for (i=0;i<=OpFlag;i++){
+ WriteIO(0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6
+ Address++;
+ ReadIO(0xCD7, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD7
+ }
+}
+
+
+void
+WritePMIO (
+UINT8 Address,
+UINT8 OpFlag,
+void* Value
+)
+{
+ UINT8 i;
+
+ OpFlag = OpFlag & 0x7f;
+ if (OpFlag == 0x02) OpFlag = 0x03;
+ for (i=0;i<=OpFlag;i++){
+ WriteIO(0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6
+ Address++;
+ WriteIO(0xCD7, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD7
+ }
+}
+
+
+void
+RWPMIO (
+UINT8 Address,
+UINT8 OpFlag,
+UINT32 AndMask,
+UINT32 OrMask
+)
+{
+ UINT32 Result;
+
+ OpFlag = OpFlag & 0x7f;
+ ReadPMIO(Address,OpFlag,&Result);
+ Result = (Result & AndMask)| OrMask;
+ WritePMIO(Address,OpFlag,&Result);
+}
+
+
+void
+ReadPMIO2 (
+UINT8 Address,
+UINT8 OpFlag,
+void* Value
+)
+{
+ UINT8 i;
+
+ OpFlag = OpFlag & 0x7f;
+ if (OpFlag == 0x02) OpFlag = 0x03;
+ for (i=0;i<=OpFlag;i++){
+ WriteIO(0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0
+ Address++;
+ ReadIO(0xCD1, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD1
+ }
+}
+
+
+void
+WritePMIO2 (
+UINT8 Address,
+UINT8 OpFlag,
+void* Value
+)
+{
+ UINT8 i;
+
+ OpFlag = OpFlag & 0x7f;
+ if (OpFlag == 0x02) OpFlag = 0x03;
+ for (i=0;i<=OpFlag;i++){
+ WriteIO(0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0
+ Address++;
+ WriteIO(0xCD1, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD1
+ }
+}
+
+
+void
+RWPMIO2 (
+UINT8 Address,
+UINT8 OpFlag,
+UINT32 AndMask,
+UINT32 OrMask
+)
+{
+ UINT32 Result;
+
+ OpFlag = OpFlag & 0x7f;
+ ReadPMIO2(Address,OpFlag,&Result);
+ Result = (Result & AndMask)| OrMask;
+ WritePMIO2(Address,OpFlag,&Result);
+}
+
+
+void
+EnterEcConfig()
+{
+ UINT16 dwEcIndexPort;
+
+ ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
+ dwEcIndexPort &= ~(UINT16)(BIT0);
+ RWIO(dwEcIndexPort, AccWidthUint8, 0x00, 0x5A);
+}
+
+void
+ExitEcConfig()
+{
+ UINT16 dwEcIndexPort;
+
+ ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
+ dwEcIndexPort &= ~(UINT16)(BIT0);
+ RWIO(dwEcIndexPort, AccWidthUint8, 0x00, 0xA5);
+}
+
+
+void
+ReadEC8 (
+UINT8 Address,
+UINT8* Value
+)
+{
+ UINT16 dwEcIndexPort;
+
+ ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
+ dwEcIndexPort &= ~(UINT16)(BIT0);
+ WriteIO(dwEcIndexPort, AccWidthUint8, &Address); // SB_IOMAP_REGCD6
+ ReadIO(dwEcIndexPort+1, AccWidthUint8, Value); // SB_IOMAP_REGCD7
+}
+
+
+void
+WriteEC8 (
+UINT8 Address,
+UINT8* Value
+)
+{
+ UINT16 dwEcIndexPort;
+
+ ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
+ dwEcIndexPort &= ~(UINT16)(BIT0);
+ WriteIO(dwEcIndexPort, AccWidthUint8, &Address); // SB_IOMAP_REGCD6
+ WriteIO(dwEcIndexPort+1, AccWidthUint8, Value); // SB_IOMAP_REGCD7
+}
+
+
+void
+RWEC8 (
+UINT8 Address,
+UINT8 AndMask,
+UINT8 OrMask
+)
+{
+ UINT8 Result;
+ ReadEC8(Address,&Result);
+ Result = (Result & AndMask)| OrMask;
+ WriteEC8(Address, &Result);
+}
+
+
+void
+programPciByteTable (
+REG8MASK* pPciByteTable,
+UINT16 dwTableSize
+)
+{
+ UINT8 i, dbBusNo, dbDevFnNo;
+ UINT32 ddBDFR;
+
+ dbBusNo = pPciByteTable->bRegIndex;
+ dbDevFnNo = pPciByteTable->bANDMask;
+ pPciByteTable++;
+ for (i = 1; i < dwTableSize; i++){
+ if ( (pPciByteTable->bRegIndex==0xFF) && (pPciByteTable->bANDMask==0xFF) && (pPciByteTable->bORMask==0xFF) ){
+ pPciByteTable++;
+ dbBusNo = pPciByteTable->bRegIndex;
+ dbDevFnNo = pPciByteTable->bANDMask;
+ }
+ else{
+ ddBDFR = (dbBusNo << 24) + (dbDevFnNo << 16) + (pPciByteTable->bRegIndex) ;
+ TRACE((DMSG_SB_TRACE, "PFA=%X AND=%X, OR=%X\n", ddBDFR, pPciByteTable->bANDMask, pPciByteTable->bORMask));
+ RWPCI(ddBDFR, AccWidthUint8 | S3_SAVE, pPciByteTable->bANDMask, pPciByteTable->bORMask);
+ pPciByteTable++;
+ }
+ }
+}
+
+
+void
+programPmioByteTable (
+REG8MASK* pPmioByteTable,
+UINT16 dwTableSize
+)
+{
+ UINT8 i;
+ for (i = 0; i < dwTableSize; i++){
+ TRACE((DMSG_SB_TRACE, "PMIO Reg = %X AndMask = %X OrMask = %X\n",pPmioByteTable->bRegIndex,pPmioByteTable->bANDMask, pPmioByteTable->bORMask));
+ RWPMIO(pPmioByteTable->bRegIndex, AccWidthUint8 , pPmioByteTable->bANDMask, pPmioByteTable->bORMask);
+ pPmioByteTable++;
+ }
+}
+
+
+UINT8
+getClockMode (
+void
+)
+{
+ UINT8 dbTemp=0;
+
+ RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT7);
+ ReadPMIO(SB_PMIO_REGB0, AccWidthUint8, &dbTemp);
+ return(dbTemp&BIT4);
+}
+
+
+UINT16
+readStrapStatus (
+void
+)
+{
+ UINT16 dwTemp=0;
+
+ RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT7);
+ ReadPMIO(SB_PMIO_REGB0, AccWidthUint16, &dwTemp);
+ return(dwTemp);
+}
diff --git a/src/vendorcode/amd/cimx/sb700/Azalia.c b/src/vendorcode/amd/cimx/sb700/Azalia.c
new file mode 100644
index 0000000..cc72858
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/Azalia.c
@@ -0,0 +1,304 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+
+#include "Platform.h"
+
+void configureAzaliaPinCmd (AMDSBCFG* pConfig, UINT32 ddBAR0, UINT8 dbChannelNum);
+void configureAzaliaSetConfigD4Dword(CODECENTRY* tempAzaliaCodecEntryPtr, UINT32 ddChannelNum, UINT32 ddBAR0);
+
+//Pin Config for ALC880, ALC882 and ALC883:
+CODECENTRY AzaliaCodecAlc882Table[] = {
+ {0x14, 0x01014010},
+ {0x15, 0x01011012},
+ {0x16, 0x01016011},
+ {0x17, 0x01012014},
+ {0x18, 0x01A19030},
+ {0x19, 0x411111F0},
+ {0x1a, 0x01813080},
+ {0x1b, 0x411111F0},
+ {0x1C, 0x411111F0},
+ {0x1d, 0x411111F0},
+ {0x1e, 0x01441150},
+ {0x1f, 0x01C46160},
+ {0xff, 0xffffffff}
+};
+
+
+//Pin Config for ALC262
+CODECENTRY AzaliaCodecAlc262Table[] = {
+ {0x14, 0x01014010},
+ {0x15, 0x411111F0},
+ {0x16, 0x411111F0},
+// {0x17, 0x01012014},
+ {0x18, 0x01A19830},
+ {0x19, 0x02A19C40},
+ {0x1a, 0x01813031},
+ {0x1b, 0x02014C20},
+ {0x1c, 0x411111F0},
+ {0x1d, 0x411111F0},
+ {0x1e, 0x0144111E},
+ {0x1f, 0x01C46150},
+ {0xff, 0xffffffff}
+};
+
+//Pin Config for ALC0861:
+CODECENTRY AzaliaCodecAlc861Table[] = {
+ {0x01, 0x8086C601},
+ {0x0B, 0x01014110},
+ {0x0C, 0x01813140},
+ {0x0D, 0x01A19941},
+ {0x0E, 0x411111F0},
+ {0x0F, 0x02214420},
+ {0x10, 0x02A1994E},
+ {0x11, 0x99330142},
+ {0x12, 0x01451130},
+ {0x1F, 0x411111F0},
+ {0x20, 0x411111F0},
+ {0x23, 0x411111F0},
+ {0xff, 0xffffffff}
+};
+
+//Pin Config for ADI1984:
+CODECENTRY AzaliaCodecAd1984Table[] = {
+ {0x11, 0x0221401F},
+ {0x12, 0x90170110},
+ {0x13, 0x511301F0},
+ {0x14, 0x02A15020},
+ {0x15, 0x50A301F0},
+ {0x16, 0x593301F0},
+ {0x17, 0x55A601F0},
+ {0x18, 0x55A601F0},
+ {0x1A, 0x91F311F0},
+ {0x1B, 0x014511A0},
+ {0x1C, 0x599301F0},
+ {0xff, 0xffffffff}
+};
+
+
+CODECENTRY FrontPanelAzaliaCodecTableList[] = {
+ {0x19, 0x02A19040},
+ {0x1b, 0x02214020},
+ {0xff, 0xffffffff}
+};
+
+
+CODECTBLLIST azaliaCodecTableList[] = {
+ {0x010ec0880, &AzaliaCodecAlc882Table[0]},
+ {0x010ec0882, &AzaliaCodecAlc882Table[0]},
+ {0x010ec0883, &AzaliaCodecAlc882Table[0]},
+ {0x010ec0885, &AzaliaCodecAlc882Table[0]},
+ {0x010ec0262, &AzaliaCodecAlc262Table[0]},
+ {0x010ec0861, &AzaliaCodecAlc861Table[0]},
+ {0x011d41984, &AzaliaCodecAd1984Table[0]},
+ {(UINT32)0x0FFFFFFFF, (CODECENTRY*)0xFFFFFFFF}
+};
+
+
+/*-------------------------------------------------------------------------------
+; Procedure: azaliaInitAfterPciEnum
+;
+; Description: This routine detects Azalia and, if present, initializes Azalia
+; This routine is called from atiSbAfterPciInit
+;
+;
+; Exit: None
+;
+; Modified: None
+;
+;-----------------------------------------------------------------------------
+*/
+void azaliaInitAfterPciEnum (AMDSBCFG* pConfig){
+ UINT8 i, dbEnableAzalia=0, dbPinRouting, dbChannelNum=0, dbTempVariable = 0;
+ UINT16 dwTempVariable = 0;
+ UINT32 ddBAR0, ddTempVariable = 0;
+
+ if (pConfig->AzaliaController == 1) return;
+
+ if (pConfig->AzaliaController != 1){
+ RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT1, BIT1);
+ ReadPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0);
+
+ if (ddBAR0 != 0){ //Keep the flag as disabled if BAR is 0 or all "F"s.
+ if (ddBAR0 != 0xFFFFFFFF){
+ ddBAR0 &= ~(0x03FFF);
+ dbEnableAzalia = 1;
+ TRACE((DMSG_SB_TRACE, "CIMxSB - Enabling Azalia controller (BAR setup is ok) \n"));
+ }
+ }
+ }
+
+ if (dbEnableAzalia){ //if Azalia is enabled
+ //Get SDIN Configuration
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGF8, AccWidthUint32 | S3_SAVE, 0, ddTempVariable);
+ ddTempVariable |= (pConfig->AzaliaSdin3 << 6);
+ ddTempVariable |= (pConfig->AzaliaSdin2 << 4);
+ ddTempVariable |= (pConfig->AzaliaSdin1 << 2);
+ ddTempVariable |= pConfig->AzaliaSdin0;
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8 | S3_SAVE, 0, (ddTempVariable & 0xFF));
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+3, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT2+BIT1+BIT0), 0);
+
+ i=11;
+ do{
+ ReadMEM( ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+ dbTempVariable |= BIT0;
+ WriteMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+ Stall(1000);
+ ReadMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+ i--;
+ } while ( (!(dbTempVariable & BIT0)) && (i > 0) );
+
+ if (i==0){
+ TRACE((DMSG_SB_TRACE, "CIMxSB - Problem in resetting Azalia controller\n"));
+ return;
+ }
+
+ Stall(1000);
+ ReadMEM( ddBAR0+SB_AZ_BAR_REG0E, AccWidthUint16, &dwTempVariable);
+ if (dwTempVariable & 0x0F){
+ TRACE((DMSG_SB_TRACE, "CIMxSB - Atleast One Azalia CODEC found \n"));
+ //atleast one azalia codec found
+ ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8, &dbPinRouting);
+ do{
+ if ( ( !(dbPinRouting & BIT0) ) && (dbPinRouting & BIT1) )
+ configureAzaliaPinCmd(pConfig, ddBAR0, dbChannelNum);
+ dbPinRouting >>= 2;
+ dbChannelNum++;
+ } while (dbChannelNum != 4);
+ }
+ else{
+ TRACE((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC NOT found \n"));
+ //No Azalia codec found
+ if (pConfig->AzaliaController != 2)
+ dbEnableAzalia = 0; //set flag to disable Azalia
+ }
+ }
+
+ if (dbEnableAzalia){
+ //redo clear reset
+ do{
+ dwTempVariable = 0;
+ WriteMEM( ddBAR0+SB_AZ_BAR_REG0C, AccWidthUint16 | S3_SAVE, &dwTempVariable);
+ ReadMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+ dbTempVariable &= ~(UINT8)(BIT0);
+ WriteMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+ ReadMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+ } while (dbTempVariable & BIT0);
+
+ if (pConfig->AzaliaSnoop == 1)
+ RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG42, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0);
+ }
+ else{
+ //disable Azalia controller
+ RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint16 | S3_SAVE, 0, 0);
+ RWPMIO(SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 0);
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8 | S3_SAVE, 0, 0x55);
+ }
+}
+
+
+void configureAzaliaPinCmd (AMDSBCFG* pConfig, UINT32 ddBAR0, UINT8 dbChannelNum){
+ UINT32 ddTempVariable, ddChannelNum;
+ CODECTBLLIST* ptempAzaliaOemCodecTablePtr;
+ CODECENTRY* tempAzaliaCodecEntryPtr;
+
+ if ((pConfig->AzaliaPinCfg) != 1)
+ return;
+
+ ddChannelNum = dbChannelNum << 28;
+ ddTempVariable = 0xF0000;
+ ddTempVariable |= ddChannelNum;
+ WriteMEM(ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddTempVariable);
+ Stall(60);
+ ReadMEM(ddBAR0 + SB_AZ_BAR_REG64, AccWidthUint32 | S3_SAVE, &ddTempVariable);
+
+ if ( ((pConfig->pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) 0xFFFFFFFF)) )
+ ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) FIXUP_PTR(&azaliaCodecTableList[0]);
+ else
+ ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) pConfig->pAzaliaOemCodecTablePtr;
+
+ TRACE((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC table pointer is %x \n", (UINT32)ptempAzaliaOemCodecTablePtr));
+
+ while ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF){
+ if ( ptempAzaliaOemCodecTablePtr->CodecID == ddTempVariable)
+ break;
+ else
+ ++ptempAzaliaOemCodecTablePtr;
+ }
+
+ if ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF){
+ TRACE((DMSG_SB_TRACE, "CIMxSB - Matching CODEC ID found \n"));
+ tempAzaliaCodecEntryPtr = (CODECENTRY*) ptempAzaliaOemCodecTablePtr->CodecTablePtr;
+ TRACE((DMSG_SB_TRACE, "CIMxSB - Matching Azalia CODEC table pointer is %x \n", (UINT32)tempAzaliaCodecEntryPtr));
+
+ if ( ((pConfig->pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) 0xFFFFFFFF)) )
+ tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR(tempAzaliaCodecEntryPtr);
+
+ configureAzaliaSetConfigD4Dword(tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0);
+ if (pConfig->AzaliaFrontPanel != 1){
+ if ( (pConfig->AzaliaFrontPanel == 2) || (pConfig->FrontPanelDetected == 1) ){
+ if ( ((pConfig->pAzaliaOemFpCodecTableptr) == NULL) || ((pConfig->pAzaliaOemFpCodecTableptr) == 0xFFFFFFFF))
+ tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR(&FrontPanelAzaliaCodecTableList[0]);
+ else
+ tempAzaliaCodecEntryPtr = (CODECENTRY*) pConfig->pAzaliaOemFpCodecTableptr;
+ configureAzaliaSetConfigD4Dword(tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0);
+ }
+ }
+ }
+}
+
+
+void configureAzaliaSetConfigD4Dword(CODECENTRY* tempAzaliaCodecEntryPtr, UINT32 ddChannelNum, UINT32 ddBAR0){
+ UINT8 dbtemp1,dbtemp2, i;
+ UINT32 ddtemp=0,ddtemp2=0;
+
+ while ((tempAzaliaCodecEntryPtr->Nid) != 0xFF){
+ dbtemp1=0x20;
+ if ((tempAzaliaCodecEntryPtr->Nid) == 0x1)
+ dbtemp1=0x24;
+ ddtemp = tempAzaliaCodecEntryPtr->Nid;
+ ddtemp &= 0xff;
+ ddtemp <<= 20;
+ ddtemp |= ddChannelNum;
+ ddtemp |= (0x700 << 8);
+ for(i=4; i>0; i--){
+ do{
+ ReadMEM(ddBAR0 + SB_AZ_BAR_REG68, AccWidthUint32, &ddtemp2);
+ } while (ddtemp2 & BIT0);
+ dbtemp2 = ( (tempAzaliaCodecEntryPtr->Byte40) >> ((4-i) * 8 ) ) & 0xff;
+ ddtemp = (ddtemp & 0xFFFF0000)+ ((dbtemp1 - i) << 8) + dbtemp2;
+ WriteMEM(ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddtemp);
+ Stall(60);
+ }
+ ++tempAzaliaCodecEntryPtr;
+ }
+}
+
diff --git a/src/vendorcode/amd/cimx/sb700/DEBUG.c b/src/vendorcode/amd/cimx/sb700/DEBUG.c
deleted file mode 100644
index f40682e..0000000
--- a/src/vendorcode/amd/cimx/sb700/DEBUG.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/*****************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *
- ***************************************************************************/
-
-
-#include "Platform.h"
-
-#define COM_BASE_ADDRESS 0x3f8
-#define DIVISOR 115200
-#define LF 0x0a
-#define CR 0x0d
-
-
-#ifdef CIM_DEBUG
- #ifndef CIM_DEBUG_LEVEL
- #define CIM_DEBUG_LEVEL 0xf
-#endif
-
-void
-TraceCode( UINT32 Level, UINT32 Code){
-
- if (!(Level & CIM_DEBUG_LEVEL)){
- return;
- }
-#if CIM_DEBUG & 1
- if (Code != 0xFF){
- WriteIO(0x80,AccWidthUint8,&Code);
- }
-#endif
-
-}
-
-
-void
-TraceDebug( UINT32 Level, CHAR8 *Format, ...){
- CHAR8 temp[16];
- va_list ArgList;
-
- if (!(Level & CIM_DEBUG_LEVEL)){
- return;
- }
-
-#if CIM_DEBUG & 2
- ArgList = va_start(ArgList,Format);
- Format= (CHAR8*) FIXUP_PTR(Format);
- while (1){
- if (*Format == 0) break;
- if (*Format == '%'){
- int Radix = 0;
- if(*(Format+1)=='s'||*(Format+1)=='S'){
- SendStringPort((CHAR8*) FIXUP_PTR(va_arg(ArgList,CHAR8*)));
- Format+=2;
- continue;
- }
-
- if(*(Format+1)=='d'||*(Format+1)=='D'){
- Radix = 10;
- }
- if(*(Format+1)=='x'||*(Format+1)=='X'){
- Radix = 16;
- }
- if (Radix){
- ItoA(va_arg(ArgList,int),Radix,temp);
- SendStringPort(temp);
- Format+=2;
- continue;
- }
- }
- SendBytePort(*Format);
- if(*(Format)==0x0a) SendBytePort(0x0d);
- Format++;
- }
- va_end(ArgList);
-#endif
-}
-
-
-void
-ItoA( UINT32 Value, int Radix, char* pstr)
-{
- char* tsptr = pstr;
- char* rsptr = pstr;
- char ch1,ch2;
- unsigned int Reminder;
-//Create String
- do{
- Reminder = Value%Radix;
- Value = Value/Radix;
- if (Reminder<0xa) *tsptr=Reminder+'0';
- else *tsptr=Reminder-0xa+'a';
- tsptr++;
- } while(Value);
-//Reverse String
- *tsptr = 0;
- tsptr--;
- while(tsptr>rsptr){
- ch1 = *tsptr;
- ch2 = *rsptr;
- *rsptr = ch1;
- *tsptr = ch2;
- tsptr--;
- rsptr++;
- }
-}
-
-void
-InitSerialOut(){
- UINT8 Data;
- UINT16 Divisor;
- Data = 0x87;
- WriteIO(COM_BASE_ADDRESS + 0x3,AccWidthUint8, &Data);
- Divisor = 115200 / DIVISOR;
- Data = Divisor & 0xFF;
- WriteIO(COM_BASE_ADDRESS + 0x00,AccWidthUint8, &Data);
- Data = Divisor >> 8;
- WriteIO(COM_BASE_ADDRESS + 0x01,AccWidthUint8, &Data);
- Data = 0x07;
- WriteIO(COM_BASE_ADDRESS + 0x3,AccWidthUint8, &Data);
-}
-
-
-void
-SendStringPort(char* pstr){
-
- while (*pstr!=0){
- SendBytePort(*pstr);
- pstr++;
- }
-}
-
-void
-SendBytePort(UINT8 Data)
-{
- int Count = 80;
- UINT8 Status;
- do {
- ReadIO((COM_BASE_ADDRESS + 0x05),AccWidthUint8, &Status);
- if(Status == 0xff) break;
- // Loop port is ready
- } while ( (Status & 0x20) == 0 && (--Count) != 0);
- WriteIO(COM_BASE_ADDRESS + 0x00,AccWidthUint8, &Data);
-}
-#endif
diff --git a/src/vendorcode/amd/cimx/sb700/DISPATCHER.c b/src/vendorcode/amd/cimx/sb700/DISPATCHER.c
deleted file mode 100644
index ae5f9b8..0000000
--- a/src/vendorcode/amd/cimx/sb700/DISPATCHER.c
+++ /dev/null
@@ -1,208 +0,0 @@
-/*****************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *
- ***************************************************************************/
-
-
-#include "Platform.h"
-
-void DispatcherEntry(void *pConfig){
-
-#ifdef B1_IMAGE
- void *pB2ImagePtr = NULL;
- CIM_IMAGE_ENTRY pB2ImageEntry;
-#endif
-
-//#if CIM_DEBUG
-// InitSerialOut();
-//#endif
-
- TRACE((DMSG_SB_TRACE, "CIM - SB700 Entry\n"));
-
-#ifdef B1_IMAGE
- if ((UINT32)(((STDCFG*)pConfig)->pB2ImageBase) != 0xffffffff){
- if (((STDCFG*)pConfig)->pB2ImageBase)
- pB2ImagePtr = CheckImage('007S',(void*)((STDCFG*)pConfig)->pB2ImageBase);
- if (pB2ImagePtr == NULL)
- pB2ImagePtr = LocateImage('007S');
- if (pB2ImagePtr!=NULL){
- TRACE((DMSG_SB_TRACE, "CIM - SB700 Redirect to B2 Image\n"));
- ((STDCFG*)pConfig)->pImageBase = (UINT32)pB2ImagePtr;
- pB2ImageEntry = (CIM_IMAGE_ENTRY)(*((UINT32*)pB2ImagePtr+1) + (UINT32)pB2ImagePtr);
- (*pB2ImageEntry)(pConfig);
- return;
- }
- }
-#endif
- saveConfigPointer(pConfig);
-
- if (((STDCFG*)pConfig)->Func == SB_POWERON_INIT)
- sbPowerOnInit((AMDSBCFG*)pConfig);
-
-#ifndef B1_IMAGE
- if (((STDCFG*)pConfig)->Func == SB_BEFORE_PCI_INIT)
- sbBeforePciInit((AMDSBCFG*)pConfig);
- if (((STDCFG*)pConfig)->Func == SB_AFTER_PCI_INIT)
- sbAfterPciInit((AMDSBCFG*)pConfig);
- if (((STDCFG*)pConfig)->Func == SB_LATE_POST_INIT)
- sbLatePost((AMDSBCFG*)pConfig);
- if (((STDCFG*)pConfig)->Func == SB_BEFORE_PCI_RESTORE_INIT)
- sbBeforePciRestoreInit((AMDSBCFG*)pConfig);
- if (((STDCFG*)pConfig)->Func == SB_AFTER_PCI_RESTORE_INIT)
- sbAfterPciRestoreInit((AMDSBCFG*)pConfig);
- if (((STDCFG*)pConfig)->Func == SB_SMM_SERVICE)
- {
- // sbSmmService((AMDSBCFG*)pConfig);
- }
- if (((STDCFG*)pConfig)->Func == SB_SMM_ACPION)
- sbSmmAcpiOn((AMDSBCFG*)pConfig);
-#endif
- TRACE((DMSG_SB_TRACE, "CIMx - SB Exit\n"));
-}
-
-
-void* LocateImage(UINT32 Signature){
- void *Result;
- UINT8 *ImagePtr = (UINT8*)(0xffffffff - (IMAGE_ALIGN-1));
- while ((UINT32)ImagePtr>=(0xfffffff - (NUM_IMAGE_LOCATION*IMAGE_ALIGN -1))){
- Result = CheckImage(Signature,(void*)ImagePtr);
- if (Result != NULL)
- return Result;
- ImagePtr -= IMAGE_ALIGN;
- }
- return NULL;
-}
-
-
-void* CheckImage(UINT32 Signature, void* ImagePtr){
- UINT8 *TempImagePtr;
- UINT8 Sum = 0;
- UINT32 i;
-// if ((*((UINT32*)ImagePtr) == 'ITA$' && ((CIMFILEHEADER*)ImagePtr)->ModuleLogo == Signature)){
- if ((*((UINT32*)ImagePtr) == Int32FromChar ('$', 'A', 'T', 'I')) && (((CIMFILEHEADER*)ImagePtr)->ModuleLogo == Signature)){
- //GetImage Image size
- TempImagePtr = (UINT8*)ImagePtr;
- for (i=0;i<(((CIMFILEHEADER*)ImagePtr)->ImageSize);i++){
- Sum += *TempImagePtr;
- TempImagePtr++;
- }
- if (Sum == 0)
- return ImagePtr;
- }
- return NULL;
-}
-
-
-UINT32 GetPciebase(){
- AMDSBCFG* Result;
- Result = getConfigPointer();
- return Result->StdHeader.pPcieBase;
-}
-
-
-void saveConfigPointer(AMDSBCFG* pConfig){
- UINT8 dbReg, i;
- UINT32 ddValue;
-
- ddValue = ((UINT32) pConfig);
- dbReg = SB_ECMOS_REG08;
-
- for (i=0; i<=3; i++){
- WriteIO(SB_IOMAP_REG72, AccWidthUint8, &dbReg);
- WriteIO(SB_IOMAP_REG73, AccWidthUint8, (UINT8 *)&ddValue);
- ddValue >>= 8;
- dbReg++;
- }
-}
-
-
-AMDSBCFG* getConfigPointer(){
- UINT8 dbReg, dbValue, i;
- UINT32 ddValue=0;
-
- dbReg = SB_ECMOS_REG08;
- for (i=0; i<=3; i++){
- WriteIO(SB_IOMAP_REG72, AccWidthUint8, &dbReg);
- ReadIO(SB_IOMAP_REG73, AccWidthUint8, &dbValue);
- ddValue |= (dbValue<<(i*8));
- dbReg++;
- }
- return( (AMDSBCFG*) ddValue);
-}
-
-/**
- * AmdSbDispatcher - Dispatch Southbridge function
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-AGESA_STATUS
-AmdSbDispatcher (
- IN VOID *pConfig
- )
-{
- AGESA_STATUS Status = AGESA_SUCCESS;
-
- saveConfigPointer (pConfig);
-
- if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_POWERON_INIT ) {
- sbPowerOnInit ((AMDSBCFG*) pConfig);
- }
-
- if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_INIT ) {
- sbBeforePciInit ((AMDSBCFG*)pConfig);
- }
-
- if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_INIT ) {
- sbAfterPciInit ((AMDSBCFG*)pConfig);
- }
-
- if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_LATE_POST_INIT ) {
- sbLatePost ((AMDSBCFG*)pConfig);
- }
-
- if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_RESTORE_INIT ) {
- sbBeforePciRestoreInit ((AMDSBCFG*)pConfig);
- }
-
- if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_RESTORE_INIT ) {
- sbAfterPciRestoreInit ((AMDSBCFG*)pConfig);
- }
-
- if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_SERVICE ) {
- sbSmmService ((AMDSBCFG*)pConfig);
- }
-
- if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_ACPION ) {
- sbSmmAcpiOn ((AMDSBCFG*)pConfig);
- }
-
- return Status;
-}
diff --git a/src/vendorcode/amd/cimx/sb700/Debug.c b/src/vendorcode/amd/cimx/sb700/Debug.c
new file mode 100644
index 0000000..f40682e
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/Debug.c
@@ -0,0 +1,169 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+#define COM_BASE_ADDRESS 0x3f8
+#define DIVISOR 115200
+#define LF 0x0a
+#define CR 0x0d
+
+
+#ifdef CIM_DEBUG
+ #ifndef CIM_DEBUG_LEVEL
+ #define CIM_DEBUG_LEVEL 0xf
+#endif
+
+void
+TraceCode( UINT32 Level, UINT32 Code){
+
+ if (!(Level & CIM_DEBUG_LEVEL)){
+ return;
+ }
+#if CIM_DEBUG & 1
+ if (Code != 0xFF){
+ WriteIO(0x80,AccWidthUint8,&Code);
+ }
+#endif
+
+}
+
+
+void
+TraceDebug( UINT32 Level, CHAR8 *Format, ...){
+ CHAR8 temp[16];
+ va_list ArgList;
+
+ if (!(Level & CIM_DEBUG_LEVEL)){
+ return;
+ }
+
+#if CIM_DEBUG & 2
+ ArgList = va_start(ArgList,Format);
+ Format= (CHAR8*) FIXUP_PTR(Format);
+ while (1){
+ if (*Format == 0) break;
+ if (*Format == '%'){
+ int Radix = 0;
+ if(*(Format+1)=='s'||*(Format+1)=='S'){
+ SendStringPort((CHAR8*) FIXUP_PTR(va_arg(ArgList,CHAR8*)));
+ Format+=2;
+ continue;
+ }
+
+ if(*(Format+1)=='d'||*(Format+1)=='D'){
+ Radix = 10;
+ }
+ if(*(Format+1)=='x'||*(Format+1)=='X'){
+ Radix = 16;
+ }
+ if (Radix){
+ ItoA(va_arg(ArgList,int),Radix,temp);
+ SendStringPort(temp);
+ Format+=2;
+ continue;
+ }
+ }
+ SendBytePort(*Format);
+ if(*(Format)==0x0a) SendBytePort(0x0d);
+ Format++;
+ }
+ va_end(ArgList);
+#endif
+}
+
+
+void
+ItoA( UINT32 Value, int Radix, char* pstr)
+{
+ char* tsptr = pstr;
+ char* rsptr = pstr;
+ char ch1,ch2;
+ unsigned int Reminder;
+//Create String
+ do{
+ Reminder = Value%Radix;
+ Value = Value/Radix;
+ if (Reminder<0xa) *tsptr=Reminder+'0';
+ else *tsptr=Reminder-0xa+'a';
+ tsptr++;
+ } while(Value);
+//Reverse String
+ *tsptr = 0;
+ tsptr--;
+ while(tsptr>rsptr){
+ ch1 = *tsptr;
+ ch2 = *rsptr;
+ *rsptr = ch1;
+ *tsptr = ch2;
+ tsptr--;
+ rsptr++;
+ }
+}
+
+void
+InitSerialOut(){
+ UINT8 Data;
+ UINT16 Divisor;
+ Data = 0x87;
+ WriteIO(COM_BASE_ADDRESS + 0x3,AccWidthUint8, &Data);
+ Divisor = 115200 / DIVISOR;
+ Data = Divisor & 0xFF;
+ WriteIO(COM_BASE_ADDRESS + 0x00,AccWidthUint8, &Data);
+ Data = Divisor >> 8;
+ WriteIO(COM_BASE_ADDRESS + 0x01,AccWidthUint8, &Data);
+ Data = 0x07;
+ WriteIO(COM_BASE_ADDRESS + 0x3,AccWidthUint8, &Data);
+}
+
+
+void
+SendStringPort(char* pstr){
+
+ while (*pstr!=0){
+ SendBytePort(*pstr);
+ pstr++;
+ }
+}
+
+void
+SendBytePort(UINT8 Data)
+{
+ int Count = 80;
+ UINT8 Status;
+ do {
+ ReadIO((COM_BASE_ADDRESS + 0x05),AccWidthUint8, &Status);
+ if(Status == 0xff) break;
+ // Loop port is ready
+ } while ( (Status & 0x20) == 0 && (--Count) != 0);
+ WriteIO(COM_BASE_ADDRESS + 0x00,AccWidthUint8, &Data);
+}
+#endif
diff --git a/src/vendorcode/amd/cimx/sb700/Dispatcher.c b/src/vendorcode/amd/cimx/sb700/Dispatcher.c
new file mode 100644
index 0000000..ae5f9b8
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/Dispatcher.c
@@ -0,0 +1,208 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+void DispatcherEntry(void *pConfig){
+
+#ifdef B1_IMAGE
+ void *pB2ImagePtr = NULL;
+ CIM_IMAGE_ENTRY pB2ImageEntry;
+#endif
+
+//#if CIM_DEBUG
+// InitSerialOut();
+//#endif
+
+ TRACE((DMSG_SB_TRACE, "CIM - SB700 Entry\n"));
+
+#ifdef B1_IMAGE
+ if ((UINT32)(((STDCFG*)pConfig)->pB2ImageBase) != 0xffffffff){
+ if (((STDCFG*)pConfig)->pB2ImageBase)
+ pB2ImagePtr = CheckImage('007S',(void*)((STDCFG*)pConfig)->pB2ImageBase);
+ if (pB2ImagePtr == NULL)
+ pB2ImagePtr = LocateImage('007S');
+ if (pB2ImagePtr!=NULL){
+ TRACE((DMSG_SB_TRACE, "CIM - SB700 Redirect to B2 Image\n"));
+ ((STDCFG*)pConfig)->pImageBase = (UINT32)pB2ImagePtr;
+ pB2ImageEntry = (CIM_IMAGE_ENTRY)(*((UINT32*)pB2ImagePtr+1) + (UINT32)pB2ImagePtr);
+ (*pB2ImageEntry)(pConfig);
+ return;
+ }
+ }
+#endif
+ saveConfigPointer(pConfig);
+
+ if (((STDCFG*)pConfig)->Func == SB_POWERON_INIT)
+ sbPowerOnInit((AMDSBCFG*)pConfig);
+
+#ifndef B1_IMAGE
+ if (((STDCFG*)pConfig)->Func == SB_BEFORE_PCI_INIT)
+ sbBeforePciInit((AMDSBCFG*)pConfig);
+ if (((STDCFG*)pConfig)->Func == SB_AFTER_PCI_INIT)
+ sbAfterPciInit((AMDSBCFG*)pConfig);
+ if (((STDCFG*)pConfig)->Func == SB_LATE_POST_INIT)
+ sbLatePost((AMDSBCFG*)pConfig);
+ if (((STDCFG*)pConfig)->Func == SB_BEFORE_PCI_RESTORE_INIT)
+ sbBeforePciRestoreInit((AMDSBCFG*)pConfig);
+ if (((STDCFG*)pConfig)->Func == SB_AFTER_PCI_RESTORE_INIT)
+ sbAfterPciRestoreInit((AMDSBCFG*)pConfig);
+ if (((STDCFG*)pConfig)->Func == SB_SMM_SERVICE)
+ {
+ // sbSmmService((AMDSBCFG*)pConfig);
+ }
+ if (((STDCFG*)pConfig)->Func == SB_SMM_ACPION)
+ sbSmmAcpiOn((AMDSBCFG*)pConfig);
+#endif
+ TRACE((DMSG_SB_TRACE, "CIMx - SB Exit\n"));
+}
+
+
+void* LocateImage(UINT32 Signature){
+ void *Result;
+ UINT8 *ImagePtr = (UINT8*)(0xffffffff - (IMAGE_ALIGN-1));
+ while ((UINT32)ImagePtr>=(0xfffffff - (NUM_IMAGE_LOCATION*IMAGE_ALIGN -1))){
+ Result = CheckImage(Signature,(void*)ImagePtr);
+ if (Result != NULL)
+ return Result;
+ ImagePtr -= IMAGE_ALIGN;
+ }
+ return NULL;
+}
+
+
+void* CheckImage(UINT32 Signature, void* ImagePtr){
+ UINT8 *TempImagePtr;
+ UINT8 Sum = 0;
+ UINT32 i;
+// if ((*((UINT32*)ImagePtr) == 'ITA$' && ((CIMFILEHEADER*)ImagePtr)->ModuleLogo == Signature)){
+ if ((*((UINT32*)ImagePtr) == Int32FromChar ('$', 'A', 'T', 'I')) && (((CIMFILEHEADER*)ImagePtr)->ModuleLogo == Signature)){
+ //GetImage Image size
+ TempImagePtr = (UINT8*)ImagePtr;
+ for (i=0;i<(((CIMFILEHEADER*)ImagePtr)->ImageSize);i++){
+ Sum += *TempImagePtr;
+ TempImagePtr++;
+ }
+ if (Sum == 0)
+ return ImagePtr;
+ }
+ return NULL;
+}
+
+
+UINT32 GetPciebase(){
+ AMDSBCFG* Result;
+ Result = getConfigPointer();
+ return Result->StdHeader.pPcieBase;
+}
+
+
+void saveConfigPointer(AMDSBCFG* pConfig){
+ UINT8 dbReg, i;
+ UINT32 ddValue;
+
+ ddValue = ((UINT32) pConfig);
+ dbReg = SB_ECMOS_REG08;
+
+ for (i=0; i<=3; i++){
+ WriteIO(SB_IOMAP_REG72, AccWidthUint8, &dbReg);
+ WriteIO(SB_IOMAP_REG73, AccWidthUint8, (UINT8 *)&ddValue);
+ ddValue >>= 8;
+ dbReg++;
+ }
+}
+
+
+AMDSBCFG* getConfigPointer(){
+ UINT8 dbReg, dbValue, i;
+ UINT32 ddValue=0;
+
+ dbReg = SB_ECMOS_REG08;
+ for (i=0; i<=3; i++){
+ WriteIO(SB_IOMAP_REG72, AccWidthUint8, &dbReg);
+ ReadIO(SB_IOMAP_REG73, AccWidthUint8, &dbValue);
+ ddValue |= (dbValue<<(i*8));
+ dbReg++;
+ }
+ return( (AMDSBCFG*) ddValue);
+}
+
+/**
+ * AmdSbDispatcher - Dispatch Southbridge function
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+AGESA_STATUS
+AmdSbDispatcher (
+ IN VOID *pConfig
+ )
+{
+ AGESA_STATUS Status = AGESA_SUCCESS;
+
+ saveConfigPointer (pConfig);
+
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_POWERON_INIT ) {
+ sbPowerOnInit ((AMDSBCFG*) pConfig);
+ }
+
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_INIT ) {
+ sbBeforePciInit ((AMDSBCFG*)pConfig);
+ }
+
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_INIT ) {
+ sbAfterPciInit ((AMDSBCFG*)pConfig);
+ }
+
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_LATE_POST_INIT ) {
+ sbLatePost ((AMDSBCFG*)pConfig);
+ }
+
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_RESTORE_INIT ) {
+ sbBeforePciRestoreInit ((AMDSBCFG*)pConfig);
+ }
+
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_RESTORE_INIT ) {
+ sbAfterPciRestoreInit ((AMDSBCFG*)pConfig);
+ }
+
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_SERVICE ) {
+ sbSmmService ((AMDSBCFG*)pConfig);
+ }
+
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_ACPION ) {
+ sbSmmAcpiOn ((AMDSBCFG*)pConfig);
+ }
+
+ return Status;
+}
diff --git a/src/vendorcode/amd/cimx/sb700/EC.c b/src/vendorcode/amd/cimx/sb700/EC.c
deleted file mode 100644
index 3ad15e1..0000000
--- a/src/vendorcode/amd/cimx/sb700/EC.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*****************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *
- ***************************************************************************/
-
-
-#include "Platform.h"
-
-#ifndef NO_EC_SUPPORT
-
-REG8MASK sb710PorInitPciTable[] = {
- // SMBUS Device(Bus 0, Dev 20, Func 0)
- {0x00, SMBUS_BUS_DEV_FUN, 0},
- {SB_SMBUS_REG43, ~(UINT8)BIT3, 0x00}, //Make some hidden registers of smbus visible.
- {SB_SMBUS_REG38, (UINT8)~(BIT7+BIT5+BIT4+BIT3+BIT2+BIT1), 0x0D},
- {SB_SMBUS_REG38+1, ~(UINT8)(BIT2+BIT1), BIT3 },
- {SB_SMBUS_REGE1, 0xFF, BIT1},
- {SB_SMBUS_REG43, 0xFF, BIT3}, //Make some hidden registers of smbus invisible.
- {0xFF, 0xFF, 0xFF},
-
- // LPC Device(Bus 0, Dev 20, Func 3)
- {0x00, LPC_BUS_DEV_FUN, 0},
- {SB_LPC_REGB8+3, ~(UINT8)(BIT1), BIT7+BIT2},
- {0xFF, 0xFF, 0xFF},
-};
-
-REG8MASK sb710PorPmioInitTbl[]={
- // index andmask ormask
- {SB_PMIO_REGD7, 0xFF, BIT5},
- {SB_PMIO_REGBB, 0xFF, BIT5},
-};
-
-
-void ecPowerOnInit(BUILDPARAM *pBuildOptPtr, AMDSBCFG* pConfig){
- UINT8 dbVar0, i=0;
-
- if (!(isEcPresent()))
- return; //return if EC is not enabled
-
- for(i=0;i<0xFF;i++){
- ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG40, AccWidthUint8 | S3_SAVE, &dbVar0);
- if ( dbVar0 & BIT7 ) break; //break if EC is ready
- Stall(500); //wait for EC to become ready
- }
-
- if (getRevisionID() >= SB700_A14){
- programPciByteTable( (REG8MASK*)FIXUP_PTR(&sb710PorInitPciTable[0]), sizeof(sb710PorInitPciTable)/sizeof(REG8MASK) );
- programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sb710PorPmioInitTbl[0]), (sizeof(sb710PorPmioInitTbl)/sizeof(REG8MASK)) );
- }
-
- RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBA), AccWidthUint8 | S3_SAVE, 0xFF, BIT2); //Enable SPI Prefetch in EC
-
- //Enable config mode
- EnterEcConfig();
-
- //Do settings for mailbox - logical device 0x09
- RWEC8(0x07, 0x00, 0x09); //switch to device 9 (Mailbox)
- RWEC8(0x60, 0x00, (pBuildOptPtr->EcLdn9MailBoxAddr >> 8)); //set MSB of Mailbox port
- RWEC8(0x61, 0x00, (pBuildOptPtr->EcLdn9MailBoxAddr & 0xFF)); //set LSB of Mailbox port
- RWEC8(0x30, 0x00, 0x01); //;Enable Mailbox Registers Interface, bit0=1
-
- if (pBuildOptPtr->EcKbd == CIMX_OPTION_ENABLED){
- RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+3), AccWidthUint8 | S3_SAVE, 0xFF, BIT7+BIT3);
- //Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC
- RWPMIO(SB_PMIO_REGBB, AccWidthUint8, 0xFF, BIT3+BIT2+BIT1+BIT0);
- //Disable LPC Decoding of port 60/64
- RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG47), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT5, 0);
- //Enable logical device 0x07 (Keyboard controller)
- RWEC8(0x07, 0x00, 0x07);
- RWEC8(0x30, 0x00, 0x01);
- }
-
- if (pBuildOptPtr->EcChannel0 == CIMX_OPTION_ENABLED){
- //Logical device 0x08
- RWEC8(0x07, 0x00, 0x08);
- RWEC8(0x60, 0x00, 0x00);
- RWEC8(0x61, 0x00, 0x62);
- RWEC8(0x30, 0x00, 0x01); //;Enable Device 8
- }
- //Logical device 0x05
- RWEC8(0x07, 0x00, 0x05); //Select logical device 05, IR controller
- RWEC8(0x60, 0x00, pBuildOptPtr->EcLdn5MailBoxAddr >> 8);
- RWEC8(0x61, 0x00, (pBuildOptPtr->EcLdn5MailBoxAddr & 0xFF));
- RWEC8(0x70, 0xF0, (pBuildOptPtr->EcLdn5Irq)); //Set IRQ to 05h
- RWEC8(0x30, 0x00, 0x01); //Enable logical device 5, IR controller
-
- RWPMIO(SB_PMIO_REGBB, AccWidthUint8, 0xFF, BIT4); //Enable EC(IMC) to generate SMI to BIOS
- ExitEcConfig();
-}
-
-
-void ecInitBeforePciEnum(AMDSBCFG* pConfig){
- if (!(isEcPresent()))
- return; //return if EC is not enabled
-}
-
-
-void ecInitLatePost(AMDSBCFG* pConfig){
- if (!(isEcPresent()) )
- return; //return if EC is not enabled
- //Enable config mode
- EnterEcConfig(); //Enable config mode
- //for future use
- ExitEcConfig();
-}
-
-#endif
diff --git a/src/vendorcode/amd/cimx/sb700/Ec.c b/src/vendorcode/amd/cimx/sb700/Ec.c
new file mode 100644
index 0000000..3ad15e1
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/Ec.c
@@ -0,0 +1,132 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+#ifndef NO_EC_SUPPORT
+
+REG8MASK sb710PorInitPciTable[] = {
+ // SMBUS Device(Bus 0, Dev 20, Func 0)
+ {0x00, SMBUS_BUS_DEV_FUN, 0},
+ {SB_SMBUS_REG43, ~(UINT8)BIT3, 0x00}, //Make some hidden registers of smbus visible.
+ {SB_SMBUS_REG38, (UINT8)~(BIT7+BIT5+BIT4+BIT3+BIT2+BIT1), 0x0D},
+ {SB_SMBUS_REG38+1, ~(UINT8)(BIT2+BIT1), BIT3 },
+ {SB_SMBUS_REGE1, 0xFF, BIT1},
+ {SB_SMBUS_REG43, 0xFF, BIT3}, //Make some hidden registers of smbus invisible.
+ {0xFF, 0xFF, 0xFF},
+
+ // LPC Device(Bus 0, Dev 20, Func 3)
+ {0x00, LPC_BUS_DEV_FUN, 0},
+ {SB_LPC_REGB8+3, ~(UINT8)(BIT1), BIT7+BIT2},
+ {0xFF, 0xFF, 0xFF},
+};
+
+REG8MASK sb710PorPmioInitTbl[]={
+ // index andmask ormask
+ {SB_PMIO_REGD7, 0xFF, BIT5},
+ {SB_PMIO_REGBB, 0xFF, BIT5},
+};
+
+
+void ecPowerOnInit(BUILDPARAM *pBuildOptPtr, AMDSBCFG* pConfig){
+ UINT8 dbVar0, i=0;
+
+ if (!(isEcPresent()))
+ return; //return if EC is not enabled
+
+ for(i=0;i<0xFF;i++){
+ ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG40, AccWidthUint8 | S3_SAVE, &dbVar0);
+ if ( dbVar0 & BIT7 ) break; //break if EC is ready
+ Stall(500); //wait for EC to become ready
+ }
+
+ if (getRevisionID() >= SB700_A14){
+ programPciByteTable( (REG8MASK*)FIXUP_PTR(&sb710PorInitPciTable[0]), sizeof(sb710PorInitPciTable)/sizeof(REG8MASK) );
+ programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sb710PorPmioInitTbl[0]), (sizeof(sb710PorPmioInitTbl)/sizeof(REG8MASK)) );
+ }
+
+ RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBA), AccWidthUint8 | S3_SAVE, 0xFF, BIT2); //Enable SPI Prefetch in EC
+
+ //Enable config mode
+ EnterEcConfig();
+
+ //Do settings for mailbox - logical device 0x09
+ RWEC8(0x07, 0x00, 0x09); //switch to device 9 (Mailbox)
+ RWEC8(0x60, 0x00, (pBuildOptPtr->EcLdn9MailBoxAddr >> 8)); //set MSB of Mailbox port
+ RWEC8(0x61, 0x00, (pBuildOptPtr->EcLdn9MailBoxAddr & 0xFF)); //set LSB of Mailbox port
+ RWEC8(0x30, 0x00, 0x01); //;Enable Mailbox Registers Interface, bit0=1
+
+ if (pBuildOptPtr->EcKbd == CIMX_OPTION_ENABLED){
+ RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+3), AccWidthUint8 | S3_SAVE, 0xFF, BIT7+BIT3);
+ //Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC
+ RWPMIO(SB_PMIO_REGBB, AccWidthUint8, 0xFF, BIT3+BIT2+BIT1+BIT0);
+ //Disable LPC Decoding of port 60/64
+ RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG47), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT5, 0);
+ //Enable logical device 0x07 (Keyboard controller)
+ RWEC8(0x07, 0x00, 0x07);
+ RWEC8(0x30, 0x00, 0x01);
+ }
+
+ if (pBuildOptPtr->EcChannel0 == CIMX_OPTION_ENABLED){
+ //Logical device 0x08
+ RWEC8(0x07, 0x00, 0x08);
+ RWEC8(0x60, 0x00, 0x00);
+ RWEC8(0x61, 0x00, 0x62);
+ RWEC8(0x30, 0x00, 0x01); //;Enable Device 8
+ }
+ //Logical device 0x05
+ RWEC8(0x07, 0x00, 0x05); //Select logical device 05, IR controller
+ RWEC8(0x60, 0x00, pBuildOptPtr->EcLdn5MailBoxAddr >> 8);
+ RWEC8(0x61, 0x00, (pBuildOptPtr->EcLdn5MailBoxAddr & 0xFF));
+ RWEC8(0x70, 0xF0, (pBuildOptPtr->EcLdn5Irq)); //Set IRQ to 05h
+ RWEC8(0x30, 0x00, 0x01); //Enable logical device 5, IR controller
+
+ RWPMIO(SB_PMIO_REGBB, AccWidthUint8, 0xFF, BIT4); //Enable EC(IMC) to generate SMI to BIOS
+ ExitEcConfig();
+}
+
+
+void ecInitBeforePciEnum(AMDSBCFG* pConfig){
+ if (!(isEcPresent()))
+ return; //return if EC is not enabled
+}
+
+
+void ecInitLatePost(AMDSBCFG* pConfig){
+ if (!(isEcPresent()) )
+ return; //return if EC is not enabled
+ //Enable config mode
+ EnterEcConfig(); //Enable config mode
+ //for future use
+ ExitEcConfig();
+}
+
+#endif
diff --git a/src/vendorcode/amd/cimx/sb700/FLASH.c b/src/vendorcode/amd/cimx/sb700/FLASH.c
deleted file mode 100644
index 0d84245..0000000
--- a/src/vendorcode/amd/cimx/sb700/FLASH.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*****************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *
- ***************************************************************************/
-
-
-#include "Platform.h"
-
-void fcInitBeforePciEnum(AMDSBCFG* pConfig){
-
- TRACE((DMSG_SB_TRACE, "Entering PreInit Flash \n"));
- RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)BIT1, 00);
-
- //Enable IDE and disable flash
- //Enable IDE and disable flash
- RWPMIO(SB_PMIO_REG59, AccWidthUint8, ~(UINT32)(BIT1+BIT0), 0);
- RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)(BIT3), BIT0); //Configure GPIO3 as IDE_RST# and release RST
- if (pConfig->IdeController){
- //Disabling IDE controller
- RWPCI((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG04, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT2+BIT1+BIT0), 0);
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAE, AccWidthUint8 | S3_SAVE, 0xFF, BIT3);
- }
- else{
- //Enable IDE controller
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAE, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT3), 0);
- }
-
- //RPR 8.2 Enable IDE Data bus DD7 Pull down Resistor if IDE is enabled and FC is disabled
- RWPMIO2(SB_PMIO2_REGE5, AccWidthUint8, 0xFF, BIT2);
- //Slowdown the clock to FC if FC is not enabled, this is a power savings feature
- RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)(BIT4), BIT4);
- RWPMIO(SB_PMIO_REGBC, AccWidthUint8, 0xC0, 0);
-}
diff --git a/src/vendorcode/amd/cimx/sb700/Flash.c b/src/vendorcode/amd/cimx/sb700/Flash.c
new file mode 100644
index 0000000..0d84245
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/Flash.c
@@ -0,0 +1,58 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+void fcInitBeforePciEnum(AMDSBCFG* pConfig){
+
+ TRACE((DMSG_SB_TRACE, "Entering PreInit Flash \n"));
+ RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)BIT1, 00);
+
+ //Enable IDE and disable flash
+ //Enable IDE and disable flash
+ RWPMIO(SB_PMIO_REG59, AccWidthUint8, ~(UINT32)(BIT1+BIT0), 0);
+ RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)(BIT3), BIT0); //Configure GPIO3 as IDE_RST# and release RST
+ if (pConfig->IdeController){
+ //Disabling IDE controller
+ RWPCI((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG04, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT2+BIT1+BIT0), 0);
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAE, AccWidthUint8 | S3_SAVE, 0xFF, BIT3);
+ }
+ else{
+ //Enable IDE controller
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAE, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT3), 0);
+ }
+
+ //RPR 8.2 Enable IDE Data bus DD7 Pull down Resistor if IDE is enabled and FC is disabled
+ RWPMIO2(SB_PMIO2_REGE5, AccWidthUint8, 0xFF, BIT2);
+ //Slowdown the clock to FC if FC is not enabled, this is a power savings feature
+ RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)(BIT4), BIT4);
+ RWPMIO(SB_PMIO_REGBC, AccWidthUint8, 0xC0, 0);
+}
diff --git a/src/vendorcode/amd/cimx/sb700/LEGACY.c b/src/vendorcode/amd/cimx/sb700/LEGACY.c
deleted file mode 100644
index c904d59..0000000
--- a/src/vendorcode/amd/cimx/sb700/LEGACY.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*****************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *
- ***************************************************************************/
-
-
-#include "Platform.h"
-
-UINT32 GetFixUp(){
- STDCFG* Result;
- Result = (STDCFG*) getConfigPointer();
- return Result->pImageBase;
-}
diff --git a/src/vendorcode/amd/cimx/sb700/Legacy.c b/src/vendorcode/amd/cimx/sb700/Legacy.c
new file mode 100644
index 0000000..c904d59
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/Legacy.c
@@ -0,0 +1,38 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+UINT32 GetFixUp(){
+ STDCFG* Result;
+ Result = (STDCFG*) getConfigPointer();
+ return Result->pImageBase;
+}
diff --git a/src/vendorcode/amd/cimx/sb700/Makefile.inc b/src/vendorcode/amd/cimx/sb700/Makefile.inc
index aed81c4..157af0e 100644
--- a/src/vendorcode/amd/cimx/sb700/Makefile.inc
+++ b/src/vendorcode/amd/cimx/sb700/Makefile.inc
@@ -32,35 +32,35 @@ CPPFLAGS_x86_32 += -I$(src)/southbridge/amd/cimx/sb700
CPPFLAGS_x86_32 += -I$(src)/include/cpu/amd/common
CPPFLAGS_x86_32 += -I$(src)/vendorcode/amd/cimx/sb700
-romstage-y += ACPILIB.c
-romstage-y += AMDLIB.c
-romstage-y += AMDSBLIB.c
-romstage-y += AZALIA.c
-romstage-y += DEBUG.c
-romstage-y += DISPATCHER.c
-romstage-y += EC.c
-romstage-y += FLASH.c
-romstage-y += SATA.c
-romstage-y += SBCMN.c
-romstage-y += SBCMNLIB.c
-romstage-y += SBMAIN.c
-romstage-y += SBPort.c
-romstage-y += SMM.c
-romstage-y += USB.c
+romstage-y += AcpiLib.c
+romstage-y += AmdLib.c
+romstage-y += AmdSbLib.c
+romstage-y += Azalia.c
+romstage-y += Debug.c
+romstage-y += Dispatcher.c
+romstage-y += Ec.c
+romstage-y += Flash.c
+romstage-y += Sata.c
+romstage-y += SbCmn.c
+romstage-y += SbCmnLib.c
+romstage-y += SbMain.c
+romstage-y += SbPort.c
+romstage-y += Smm.c
+romstage-y += Usb.c
-ramstage-y += ACPILIB.c
-ramstage-y += AMDLIB.c
-ramstage-y += AMDSBLIB.c
-ramstage-y += AZALIA.c
-ramstage-y += DEBUG.c
-ramstage-y += DISPATCHER.c
-ramstage-y += EC.c
-ramstage-y += FLASH.c
-ramstage-y += SATA.c
-ramstage-y += SBCMN.c
-ramstage-y += SBCMNLIB.c
-ramstage-y += SBMAIN.c
-ramstage-y += SBPort.c
-ramstage-y += SMM.c
-ramstage-y += USB.c
-ramstage-y += LEGACY.c
+ramstage-y += AcpiLib.c
+ramstage-y += AmdLib.c
+ramstage-y += AmdSbLib.c
+ramstage-y += Azalia.c
+ramstage-y += Debug.c
+ramstage-y += Dispatcher.c
+ramstage-y += Ec.c
+ramstage-y += Flash.c
+ramstage-y += Sata.c
+ramstage-y += SbCmn.c
+ramstage-y += SbCmnLib.c
+ramstage-y += SbMain.c
+ramstage-y += SbPort.c
+ramstage-y += Smm.c
+ramstage-y += Usb.c
+ramstage-y += Legacy.c
diff --git a/src/vendorcode/amd/cimx/sb700/SATA.c b/src/vendorcode/amd/cimx/sb700/SATA.c
deleted file mode 100644
index d503239..0000000
--- a/src/vendorcode/amd/cimx/sb700/SATA.c
+++ /dev/null
@@ -1,453 +0,0 @@
-/*****************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *
- ***************************************************************************/
-
-
-#include "Platform.h"
-
-//Table for class code of SATA Controller in different modes
-UINT32 sataIfCodeTable[] = {
- 0x01018f00, //sata class ID of IDE
- 0x01040000, //sata class ID of RAID
- 0x01060100, //sata class ID of AHCI
- 0x01018a00, //sata class ID of Legacy IDE
- 0x01018f00, //sata class ID of IDE to AHCI mode
- 0x01060100, //sata class ID of AMD-AHCI mode
- 0x01018f00 //sata class ID of IDE to AMD-AHCI mode
-};
-
-//Table for device id of SATA Controller in different modes
-UINT16 sataDeviceIDTable[] = {
- 0x4390, //sata device ID of IDE
- 0x4392, //sata device ID of RAID
- 0x4391, //sata class ID of AHCI
- 0x4390, //sata device ID of Legacy IDE
- 0x4390, //sata device ID of IDE->AHCI mode
- 0x4394, //sata device ID for AMD-AHCI mode
- 0x4390 //sata device ID of IDE->AMDAHCI mode
-};
-
-
-void sataInitBeforePciEnum(AMDSBCFG* pConfig){
- UINT32 ddValue, *tempptr;
- UINT16 *pDeviceIdptr, dwDeviceId;
- UINT8 dbValue, dbOrMask, dbAndMask;
-
-
- dbAndMask=0;
- dbOrMask=0;
- // Enable/Disable Combined mode & do primary/secondary selections, enable/disable
- if (pConfig->SataIdeCombinedMode == CIMX_OPTION_DISABLED) dbAndMask= BIT3; //Clear BIT3
- if (pConfig->SataIdeCombMdPriSecOpt == 1) dbOrMask = BIT4; //Set BIT4
- if (pConfig->SataSmbus == 0) dbOrMask = BIT1;
-
- RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAD), AccWidthUint8 | S3_SAVE, ~(dbAndMask), dbOrMask);
-
- if (pConfig->SataController == 0){
- // SATA Controller Disabled & set Power Saving mode to disabled
- RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAD), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, BIT1);
- return;
- }
-
- restrictSataCapabilities(pConfig);
-
- // Get the appropriate class code from the table and write it to PCI register 08h-0Bh
- // Set the appropriate SATA class based on the input parameters
- dbValue=pConfig->SataClass;
- tempptr= (UINT32 *) FIXUP_PTR (&sataIfCodeTable[0]);
- ddValue=tempptr[dbValue];
-
- // BIT0: Enable write access to PCI header (reg 08h-0Bh) by setting SATA PCI register 40h, bit 0
- // BIT4:disable fast boot
- RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT4+BIT0);
-
- // Write the class code to SATA PCI register 08h-0Bh
- RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, ddValue);
-
- if (pConfig->SataClass == LEGACY_IDE_MODE) //SATA = Legacy IDE
- //Set PATA controller to native mode
- RWPCI(((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F);
-
- //Change the appropriate device id
- if (pConfig->SataClass == AMD_AHCI_MODE) {
- RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 3), AccWidthUint8 | S3_SAVE, 0xff, BIT0);
- }
- pDeviceIdptr= (UINT16 *) FIXUP_PTR (&sataDeviceIDTable[0]);
-
- ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, &dwDeviceId);
- if ( !((dwDeviceId==SB750_SATA_DEFAULT_DEVICE_ID) && (pConfig->SataClass == RAID_MODE)) ){
- //if not (SB750 & RAID mode), then program the device id
- dwDeviceId=pDeviceIdptr[dbValue];
- RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, dwDeviceId);
- }
-
- if (pConfig->AcpiS1Supported)
- RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG34), AccWidthUint8 | S3_SAVE, 00, 0x70);//Disable SATA PM & MSI capability
- else
- RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG60+1), AccWidthUint8 | S3_SAVE, 00, 0x70);//Disable SATA MSI capability
-
- if (getRevisionID() >= SB700_A13){
- //Enable test/enhancement mode for A13
- RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40+3), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT5, 00);
- RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG48), AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT24+BIT21), 0xBF80);
- }
-
- if (getRevisionID() >= SB700_A14){
- //Fix for TT SB01352 - LED Stays On When ODD Attached To Slave Port In IDE Mode
- RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG48), AccWidthUint8 | S3_SAVE, 0xFF, BIT6);
- }
-
- // Disable write access to PCI header
- RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0);
-
- // RPR 6.5 SATA PHY Programming Sequence
- RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG86, AccWidthUint16 | S3_SAVE, 0x00, 0x2C00);
- RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG88, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016);
- RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG8C, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016);
- RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG90, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016);
- RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG94, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016);
- RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG98, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016);
- RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG9C, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016);
- RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REGA0, AccWidthUint32 | S3_SAVE, 0x00, 0xA07AA07A);
- RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REGA4, AccWidthUint32 | S3_SAVE, 0x00, 0xA07AA07A);
- RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REGA8, AccWidthUint32 | S3_SAVE, 0x00, 0xA07AA07A);
-
- CallBackToOEM(SATA_PHY_PROGRAMMING, NULL, pConfig);
-}
-
-void sataInitAfterPciEnum(AMDSBCFG* pConfig){
- UINT32 ddAndMask=0, ddOrMask=0, ddBar5=0;
- UINT8 dbVar, dbPortNum;
-
- if (pConfig->SataController == 0) return; //return if SATA controller is disabled.
-
- //Enable write access to pci header, pm capabilities
- RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
-
- //Disable AHCI enhancement function (RPR 7.2)
- RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8 | S3_SAVE, 0xFF, BIT7);
-
- restrictSataCapabilities(pConfig);
-
- ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5);
-
- if ( (ddBar5 == 0) || (ddBar5 == -1) ) {
- //assign temporary BAR5
- if ( (pConfig->TempMMIO == 0) || (pConfig->TempMMIO == -1))
- ddBar5 = 0xFEC01000;
- else
- ddBar5=pConfig->TempMMIO;
-
- WritePCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5);
- }
-
- ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
- RWPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8,0xFF, 0x03); //memory and io access enable
-
- ddBar5 &= 0xFFFFFC00; //Clear Bits 9:0
- if (!pConfig->SataPortMultCap)
- ddAndMask |= BIT12;
- if (!pConfig->SataAggrLinkPmCap)
- ddAndMask |= BIT11;
- if (pConfig->SataSscPscCap)
- ddOrMask |= BIT1;
-
- RWMEM((ddBar5 + SB_SATA_BAR5_REGFC),AccWidthUint32 | S3_SAVE, ~ddAndMask, ddOrMask);
-
-
- //Clear HPCP and ESP by default
- RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, 0xFFFC0FC0, 0);
-
- if (pConfig->SataHpcpButNonESP !=0) {
- RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, 0xFFFFFFC0, pConfig->SataHpcpButNonESP);
- }
-
- // SATA ESP port setting
- // These config bits are set for SATA driver to identify which ports are external SATA ports and need to
- // support hotplug. If a port is set as an external SATA port and need to support hotplug, then driver will
- // not enable power management(HIPM & DIPM) for these ports.
- if (pConfig->SataEspPort !=0) {
- RWMEM((ddBar5 + SB_SATA_BAR5_REGFC),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT20);
- RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, ~(pConfig->SataEspPort), 0);
- RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT17+BIT16+BIT15+BIT14+BIT13+BIT12),(pConfig->SataEspPort << 12));
- }
-
- if ( ((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE) )
- RWPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50+2), AccWidthUint8, ~(UINT32)(BIT3+BIT2+BIT1), BIT2+BIT1); //set MSI to 8 messages
-
- if ( ((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE) && ((pConfig->SataIdeCombinedMode) == CIMX_OPTION_DISABLED) ){
- RWMEM((ddBar5 + SB_SATA_BAR5_REG00),AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT2+BIT1+BIT0), BIT2+BIT0);
- RWMEM((ddBar5 + SB_SATA_BAR5_REG0C),AccWidthUint8 | S3_SAVE, 0xC0, 0x3F);
- }
-
- for (dbPortNum=0;dbPortNum<=5;dbPortNum++){
- if (pConfig->SataPortMode & (1 << dbPortNum)){
- //downgrade to GEN1
- RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0x0F, 0x10);
- RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFF, 0x01);
- Stall(1000);
- RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00);
- }
- }
-
- //If this is not S3 resume and also if SATA set to one of IDE mode, then implement drive detection workaround.
- if ( !(pConfig->S3Resume) && ( ((pConfig->SataClass) != AHCI_MODE) && ((pConfig->SataClass) != RAID_MODE) && ((pConfig->SataClass) != AMD_AHCI_MODE) ) )
- sataDriveDetection(pConfig, ddBar5);
-
- if ( (pConfig->SataPhyWorkaround==1) || ( (pConfig->SataPhyWorkaround==0) && (getRevisionID() < SB700_A13)) )
- sataPhyWorkaround(pConfig, ddBar5);
-
- // Set the handshake bit for IDE driver to detect the disabled IDE channel correctly.
- // Set IDE PCI Config 0x63 [3] if primary channel disabled, [4] if secondary channel disabled.
- if (pConfig->SataIdeCombinedMode == CIMX_OPTION_DISABLED)
- RWPCI( ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG63), AccWidthUint8 , 0xF9, (0x02 << (pConfig->SataIdeCombMdPriSecOpt)) );
-
- WritePCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
-
- //Disable write access to pci header, pm capabilities
- RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0);
-}
-
-
-void sataDriveDetection(AMDSBCFG* pConfig, UINT32 ddBar5){
- UINT32 ddVar0;
- UINT8 dbPortNum, dbVar0;
- UINT32 dwIoBase, dwVar0;
-
- TRACE((DMSG_SB_TRACE, "CIMx - Entering sata drive detection procedure\n\n"));
- TRACE((DMSG_SB_TRACE, "SATA BAR5 is %X \n", ddBar5));
-
- if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE) ){
- for (dbPortNum=0;dbPortNum<4;dbPortNum++){
- ReadMEM(ddBar5+ SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint32, &ddVar0);
- if ( ( ddVar0 & 0x0F ) == 0x03){
- if ( dbPortNum & BIT0)
- //this port belongs to secondary channel
- ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG18), AccWidthUint16, &dwIoBase);
- else
- //this port belongs to primary channel
- ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG10), AccWidthUint16, &dwIoBase);
-
- //if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them
- if (pConfig->SataClass == LEGACY_IDE_MODE)
- dwIoBase = ( (0x170) | ( (~((dbPortNum & BIT0) << 7)) & 0x80 ) );
-
- if ( dbPortNum & BIT1)
- //this port is slave
- dbVar0=0xB0;
- else
- //this port is master
- dbVar0=0xA0;
- dwIoBase &= 0xFFF8;
- WriteIO(dwIoBase+6, AccWidthUint8, &dbVar0);
-
- //Wait in loop for 30s for the drive to become ready
- for (dwVar0=0;dwVar0<3000;dwVar0++){
- ReadIO(dwIoBase+7, AccWidthUint8, &dbVar0);
- if ( (dbVar0 & 0x88) == 0)
- break;
- Stall(10000);
- }
- } //end of if ( ( ddVar0 & 0x0F ) == 0x03)
- } //for (dbPortNum=0;dbPortNum<4;dbPortNum++)
- } //if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE) )
-}
-
-
-//This patch is to workaround the SATA PHY logic hardware issue in the SB700.
-//Internally this workaround is called as 7NewA
-void sataPhyWorkaround(AMDSBCFG* pConfig, UINT32 ddBar5){
-
- UINT8 dbPortNum, dbVar0;
-
- if (pConfig->Gen1DeviceShutdownDuringPhyWrknd == 0x01){
- for (dbPortNum=0;dbPortNum<=5;dbPortNum++){
- ReadMEM(ddBar5+ SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint8, &dbVar0);
- if ( (dbVar0 & 0xF0) == 0x10){
- RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40+2, AccWidthUint8 | S3_SAVE, 0xFF, (01 << dbPortNum));
- }
-
- }
- }
-
- RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)(BIT4+BIT3), BIT4+BIT3);//set PMIO_D0[4:3] = 11b // this is to tell SATA PHY to use the internal 100MHz clock
- RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG86, AccWidthUint8 | S3_SAVE, 0x00, 0x40);// set SATA PCI_CFG 0x86[7:0] = 0x40 //after the reset is done, perform this to turn on the diff clock path into SATA PHY
- Stall(2000);// Wait for 2ms
- RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)(BIT4+BIT3), 00);//13. set PMIO_D0[4:3] = 00b
- Stall(20000);// Wait 20ms
- forceOOB(ddBar5);// Force OOB
-
- RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40+2, AccWidthUint8 | S3_SAVE, ~(0x03F), 00);
-}
-
-
-void forceOOB(UINT32 ddBar5){
- UINT8 dbPortNum;
- for (dbPortNum=0;dbPortNum<=5;dbPortNum++)
- RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFF, 0x01);
- Stall(2000);
- for (dbPortNum=0;dbPortNum<=5;dbPortNum++)
- RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00);
- Stall(2000);// Wait for 2ms
-}
-
-/*++
-
-Routine Description:
-
- SATA Late Configuration
-
- if the mode is selected as IDE->AHCI
- { 1. Set class ID to AHCI
- 2. Enable AHCI interrupt
- }
-
-Arguments:
-
- pConfig - SBconfiguration
-
-Returns:
-
- void
-
---*/
-void sataInitLatePost(AMDSBCFG* pConfig){
- UINT32 ddBar5;
- UINT8 dbVar;
-
- //Return immediately is sata controller is not enabled
- if (pConfig->SataController == 0) return;
-
- restrictSataCapabilities(pConfig);
-
- //Get BAR5 value
- ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5);
-
- //Assign temporary BAR if is not already assigned
- if ( (ddBar5 == 0) || (ddBar5 == -1) ){
- //assign temporary BAR5
- if ( (pConfig->TempMMIO == 0) || (pConfig->TempMMIO == -1))
- ddBar5 = 0xFEC01000;
- else
- ddBar5=pConfig->TempMMIO;
- WritePCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5);
- }
-
- ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
- //Enable memory and io access
- RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, 0xFF, 0x03);
- //Enable write access to pci header, pm capabilities
- RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0);
-
- shutdownUnconnectedSataPortClock(pConfig, ddBar5);
-
- if ( (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE)){
- //program the AHCI class code
- RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, 0x01060100);
- //Set interrupt enable bit
- RWMEM((ddBar5 + 0x04),AccWidthUint8,~(UINT32)0,BIT1);
- //program the correct device id for AHCI mode
- RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, 0x4391);
-
- if (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE)
- //program the correct device id for AMD-AHCI mode
- RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 3), AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
- }
-
- //Disable write access to pci header and pm capabilities
- RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0);
- //Clear error status
- RWMEM((ddBar5 + SB_SATA_BAR5_REG130),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
- RWMEM((ddBar5 + SB_SATA_BAR5_REG1B0),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
- RWMEM((ddBar5 + SB_SATA_BAR5_REG230),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
- RWMEM((ddBar5 + SB_SATA_BAR5_REG2B0),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
- //Restore memory and io access bits
- WritePCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar );
-}
-
-
-void shutdownUnconnectedSataPortClock(AMDSBCFG* pConfig, UINT32 ddBar5){
- UINT8 dbPortNum, dbPortSataStatus, NumOfPorts=0;
- UINT8 UnusedPortBitMap;
- UINT8 SataType;
- UINT8 ClockOffEnabled ;
-
- UnusedPortBitMap = 0;
-
- // First scan for all unused SATA ports
- for (dbPortNum = 5; dbPortNum <= 5; dbPortNum--) {
- ReadMEM (ddBar5 + SB_SATA_BAR5_REG128 + (dbPortNum * 0x80), AccWidthUint8, &dbPortSataStatus);
- if ((!(dbPortSataStatus & 0x01)) && (!((pConfig->SataEspPort) & (1 << dbPortNum)))) {
- UnusedPortBitMap |= (1 << dbPortNum);
- }
- }
-
- // Decide if we need to shutdown the clock for all unused ports
- SataType = pConfig->SataClass;
- ClockOffEnabled = (pConfig->SataClkAutoOff && ((SataType == NATIVE_IDE_MODE) || (SataType == LEGACY_IDE_MODE) || \
- (SataType == IDE_TO_AHCI_MODE) || (SataType == IDE_TO_AMD_AHCI_MODE))) || \
- (pConfig->SataClkAutoOffAhciMode && ((SataType == AHCI_MODE) || (SataType == AMD_AHCI_MODE)));
-
- if (ClockOffEnabled) {
- //Shutdown the clock for the port and do the necessary port reporting changes.
- TRACE((DMSG_SB_TRACE, "Shutting down clock for SATA ports %X \n", UnusedPortBitMap));
- RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, UnusedPortBitMap);
- RWMEM(ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, ~UnusedPortBitMap, 00);
- }
-
- // If all ports are in disabled state, report at least one
- ReadMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, &dbPortSataStatus);
- if ( (dbPortSataStatus & 0x3F) == 0) {
- dbPortSataStatus = 1;
- RWMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, ~(0x3F), dbPortSataStatus);
- }
-
- // Decide if we need to hide unused ports from being seen by OS (this saves OS startup time)
- if (pConfig->SataHideUnusedPort && ClockOffEnabled) {
- dbPortSataStatus &= ~UnusedPortBitMap; // Mask off unused ports
- for (dbPortNum = 0; dbPortNum <= 6; dbPortNum++) {
- if (dbPortSataStatus & (1 << dbPortNum))
- NumOfPorts++;
- }
- if (NumOfPorts == 0 ) {
- NumOfPorts = 0x01;
- }
- RWMEM (ddBar5 + SB_SATA_BAR5_REG00, AccWidthUint8, 0xE0, NumOfPorts - 1);
- }
-}
-
-
-void restrictSataCapabilities(AMDSBCFG* pConfig){
- //Restrict capabilities
- if ( ((getSbCapability(Sb_Raid0_1_Capability)== 0x02) && (pConfig->SataClass == RAID_MODE)) || \
- ((getSbCapability(Sb_Raid5_Capability)== 0x02) && (pConfig->SataClass == RAID_MODE)) || \
- ((getSbCapability(Sb_Ahci_Capability)== 0x02) && ((pConfig->SataClass == AHCI_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE)))){
- pConfig->SataClass = NATIVE_IDE_MODE;
- }
-}
diff --git a/src/vendorcode/amd/cimx/sb700/SBCMN.c b/src/vendorcode/amd/cimx/sb700/SBCMN.c
deleted file mode 100644
index 7d5b4f4..0000000
--- a/src/vendorcode/amd/cimx/sb700/SBCMN.c
+++ /dev/null
@@ -1,572 +0,0 @@
-/*****************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *
- ***************************************************************************/
-
-
-#include "Platform.h"
-
-
-REG8MASK sbEarlyPostByteInitTable[]={
- // SMBUS Device(Bus 0, Dev 20, Func 0)
- {0x00, SMBUS_BUS_DEV_FUN, 0},
- {SB_SMBUS_REG43, ~(UINT8)BIT3, 0x00}, //Make BAR registers of smbus visible.
- {SB_SMBUS_REG24, 0X00, (CIMx_Version & 0xFF)}, //Program the version information
- {SB_SMBUS_REG24+1, 0x00, (CIMx_Version >> 8)},
- {SB_SMBUS_REG24+2, 0x00, RC_Information},
- {SB_SMBUS_REG24+3, 0x00, Additional_Changes_Indicator},
- {SB_SMBUS_REG43, ~(UINT8)BIT3, BIT3}, //Make BAR registers of smbus invisible.
- {SB_SMBUS_REGAE, ~(UINT8)(BIT6 + BIT5), BIT6 + BIT5}, //Disable Timer IRQ enhancement for proper operation of the 8254 timer.
- // [6] - IoApicPicArbEn, set 1 to enable arbiter between APIC and PIC interrupts
- {SB_SMBUS_REGAD, ~(UINT8)(BIT0+BIT1+BIT2+BIT4), BIT0+BIT3}, // Initialize SATA to default values, SATA Enabled,
- // Combined mode enabled, SATA as primary, power saving enable
- {SB_SMBUS_REGAF, 0xE3, 6 << 2}, // Set SATA Interrupt to INTG#
- {SB_SMBUS_REG68, BIT3, 0 }, // First disable all usb controllers and then enable then according to setup selection
- {0xFF, 0xFF, 0xFF},
-
- // IDE Device(Bus 0, Dev 20, Func 1)
- {0x00, IDE_BUS_DEV_FUN, 0},
- {SB_IDE_REG62+1, ~(UINT8)BIT0, BIT5}, // Enabling IDE Explicit Pre-Fetch IDE PCI Config 0x62[8]=0
- // Allow MSI capability of IDE controller to be visible. IDE PCI Config 0x62[13]=1
- {0xFF, 0xFF, 0xFF},
-
- // Azalia Device(Bus 0, Dev 20, Func 2)
- {0x00, AZALIA_BUS_DEV_FUN, 0},
- {SB_AZ_REG4C, ~(UINT8)BIT0, BIT0},
- {0xFF, 0xFF, 0xFF},
-
- // LPC Device(Bus 0, Dev 20, Func 3)
- {0x00, LPC_BUS_DEV_FUN, 0},
-
- {SB_LPC_REG40, ~(UINT8)BIT2, BIT2}, // Enabling LPC DMA Function 0x40[2]
- {SB_LPC_REG78, ~(UINT8)BIT1, 00}, // Disables MSI capability
- {0xFF, 0xFF, 0xFF},
-
- // P2P Bridge(Bus 0, Dev 20, Func 4)
- {0x00, SBP2P_BUS_DEV_FUN, 0},
-
- {SB_P2P_REG64+1, 0xFF, BIT7+BIT6}, //Adjusting CLKRUN#, PCIB_PCI_Config 0x64[15]=01
- //Enabling arbiter fix, PCIB_PCI_Config 0x64[14]=01
- {SB_P2P_REG64+2, 0xFF, BIT4}, //Enabling One-Prefetch-Channel Mode, PCIB_PCI_config 0x64 [20]
-
- {SB_P2P_REG0D, 0x00, 0x40}, //Setting Latency Timers to 0x40, Enables the PCIB to retain ownership
- {SB_P2P_REG1B, 0x00, 0x40}, // of the bus on the Primary side and on the Secondary side when GNT# is deasserted.
-
- {0xFF, 0xFF, 0xFF},
-
- // SATA Device(Bus 0, Dev 17, Func 0)
- {0x00, SATA_BUS_DEV_FUN, 0},
- {SB_SATA_REG44, 0xff, BIT0}, // Enables the SATA watchdog timer register prior to the SATA BIOS post
- {SB_SATA_REG40+3, 0xff, BIT5}, // RPR setting: Disable the testing/enhancement mode SATA_PCI_config 0x40 [29] = 1
- {SB_SATA_REG48+2, 0xff, BIT5}, // RPR setting: Disable the testing/enhancement mode SATA_PCI_config 0x48 [24] = 1, [21] = 1
- {SB_SATA_REG48+3, 0xff, BIT0},
- {SB_SATA_REG44 + 2, 0, 0x10}, // Program watchdog timer with 16 retries before timer time-out.
- {0xFF, 0xFF, 0xFF},
-};
-
-
-REG8MASK sbEarlyPostPmioInitTbl[]={
- // index andmask ormask
- {SB_PMIO_REG55, ~(UINT8)(BIT3+BIT4+BIT5), BIT5+BIT3}, //BIT3(PcieNative)=1b, BIT4(Pcie_Wak_Mask)=0b, BIT5(Pcie_WAK_Sci)=1b
- {SB_PMIO_REG01, 0xff, BIT1},
- {SB_PMIO_REG0E, 0xff, BIT2 + BIT3},
- {SB_PMIO_REG10, 0x3E, (BIT6+BIT5+BIT3+BIT1)}, // RTC_En_En + TMR_En_En + GLB_EN_EN and clear EOS_EN + PciExpWakeDisEn
- {SB_PMIO_REG61, 0xFF, 0x40}, // USB Device Support to Wakeup System from S3/S4 state, USB PME & PCI Act from NB
- {SB_PMIO_REG59, 0xFC, 0x00 }, // Clear the flash controller bits BIT1:0
- {SB_PMIO_REG01, 0xFF, 0x97 }, // Clear all the status
- {SB_PMIO_REG05, 0xFF, 0xFF },
- {SB_PMIO_REG06, 0xFF, 0xFF },
- {SB_PMIO_REG07, 0xFF, 0xFF },
- {SB_PMIO_REG0F, 0xFF, 0x1F },
- {SB_PMIO_REG1D, 0xFF, 0xFF },
- {SB_PMIO_REG39, 0xFF, 0xFF },
- {SB_PMIO_REG7C, ~(UINT8)(BIT5+BIT3+BIT2), BIT3+BIT2}, //Turn on BLink LED
- {SB_PMIO_REG67, 0xFF, 0x06}, // C State enable, must be set in order to exercise C state
- {SB_PMIO_REG68, 0x38, 0x84},
- {SB_PMIO_REG8D, 0xFF, 0x01}, // Set PM_Reg_0x8D[0] to enable PmeTurnOff/PmeMsgAck handshake to fix PCIE LAN S3/S4 wake failure
- {SB_PMIO_REG84, 0xFD, BIT3+BIT0},
- {SB_PMIO_REG53, 0xFF, BIT7+BIT6}, //ACPI System Clock setting, PMIO Reg 0x53[6]=1. Our reference clock
- //is either 25 or 100Mhz and so the default acpi clock is actually
- //running at 12.5Mhz and so the system time will run slow. We have
- //generated another internal clock which runs at 14.318Mhz which is the
- //correct frequency. We should set this bit to turn on this feature PMIO_REG53[6]=1
- //PCI Clock Period, PM_IO 0x53 [7] = 1. By setting this, PCI clock period
- //increase to 30.8 ns.
- {SB_PMIO_REG95, ~(UINT8)(BIT2+BIT1+BIT0), BIT2+BIT1}, //USB Advanced Sleep Control, Enables USB EHCI controller
- //to sleep for 6 uframes in stead of the standard 10us to
- //improve power saving.
- {SB_PMIO_REGD7, 0xFF, BIT6+BIT1},
-
-};
-
-
-// commonInitEarlyBoot - set /SMBUS/ACPI/IDE/LPC/PCIB. This settings should be done during S3 resume also
-void commonInitEarlyBoot(AMDSBCFG* pConfig) {
- UINT16 dwTempVar;
- CPUID_DATA CpuId;
- CPUID_DATA CpuId_Brand;
- UINT8 dbValue;
- UINT32 ddValue;
- UINT8 Family, Model, Stepping;
-
- TRACE((DMSG_SB_TRACE, "CIMx - Entering commonInitEarlyBoot \n"));
- CpuidRead (0x01, &CpuId);
- CpuidRead (0x80000001, &CpuId_Brand); //BrandID
-
- //Early post initialization of pci config space
- programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbEarlyPostByteInitTable[0]), sizeof(sbEarlyPostByteInitTable)/sizeof(REG8MASK) );
-
- // RPR 5.5 Clear PM_IO 0x65[4] UsbResetByPciRstEnable, Set this bit so that usb gets reset whenever there is PCIRST.
- RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT4, BIT4);
-
-
- #if 0 //KZ [083011]-It's used wrong BIOS SIZE for Coreboot.
- //For being compatible with earlier revision, check whether ROM decoding is changed already outside CIMx before
- //changing it.
- ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG68, AccWidthUint16 | S3_SAVE, &dwTempVar);
- if ( (dwTempVar == 0x08) || (dwTempVar == 0x00))
- RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG68, AccWidthUint8 | S3_SAVE, 0, 0x0E);// Change the 1Mb below ROM decoding range to 0xE0000 to 0xFFFFF
- #endif
-
- if (pConfig->AzaliaController == 1)
- RWPMIO(SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 0);
- else
- RWPMIO(SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, 0xFF, BIT3);
-
- //Disable or Enable PCI Clks based on input
- RWPCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG42, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT5+BIT4+BIT3+BIT2), ((pConfig->PciClks) & 0x0F) << 2 );
- RWPCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG4A, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT1+BIT0), ((pConfig->PciClks) >> 4) | ((pConfig->PciClk5) << 1) );
- ReadPMIO(SB_PMIO_REG2C, AccWidthUint16, &dwTempVar); // Read Arbiter address, Arbiter address is in PMIO 2Ch
- RWIO(dwTempVar, AccWidthUint8, 0, 0); // Write 0 to enable the arbiter
-
- abLinkInitBeforePciEnum(pConfig); // Set ABCFG registers
- // Set LDTSTP# duration to 10us for HydraD CPU model 8, 9 or A; or when HT link is 200MHz; or Family15 Orochi CPU C32/G34 package
- ddValue = CpuId.REG_EAX & 0x00FF00F0;
- dbValue = 1;
-
- if((CpuId.REG_EAX & 0x00F00F00) == 0x00600F00) {
- if(((CpuId_Brand.REG_EBX & 0xF0000000) == 0x30000000) || ((CpuId_Brand.REG_EBX & 0xF0000000) == 0x50000000)) {
- //Orochi processor G34/C32, set to 10us
- dbValue = 10;
- }
- else {
- // Orochi processor AM3, set to 5us
- dbValue = 5;
- }
- }
-
- if ((pConfig->AnyHT200MhzLink) || (ddValue == 0x100080) || (ddValue == 0x100090) || (ddValue == 0x1000A0)) {
- //any kind of CPU run HT at 200Mhz , or HydraD CPU model 8, 9 or A, set to 10us
- dbValue = 10;
- }
-
-
- RWPMIO(SB_PMIO_REG8B, AccWidthUint8 | S3_SAVE, 0x00, dbValue);
-
- // Enable/Disable watchdog timer
- RWPMIO(SB_PMIO_REG69, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, (UINT8)(!pConfig->WatchDogTimerEnable));
-
- // Per SB700/SP5100 RPR 2.5
- //
- // Enable C1e stutter timer for any system with chip revision >= A14
- // Set SMBUS:0x5c[22:16] = 16 -- Set amount of idle time to 16ms
- //
-
- if (getRevisionID() >= SB700_A14) {
- dwTempVar = 0x0010;
-
- // Set PMIO:0xcb[5] = 1 -- AutoStutterTimerEn, set 1 to enable
- // Set PMIO:0xcb[6] = 1 -- AutoStutterTimeSel, 1=1ms timer tick increment; 0=2us increment
- RWPMIO(SB_PMIO_REGCB, AccWidthUint8 | S3_SAVE, 0xff, BIT6 + BIT5);
-
- Family = (UINT8)((CpuId.REG_EAX & 0x00ff0000)>> 16);
- Model = (UINT8)((CpuId.REG_EAX & 0x000000f0)>> 4);
- Stepping = (UINT8) (CpuId.REG_EAX & 0x0000000f);
-
- // For Server system (SP5100) with CPU type = Family 10h with LS2 mode enabled:
- // Model=6 && Stepping=2 || Model=(4I5|6) && Stepping >=3 || Model=(8|9) && Stepping >= 1 || Model Ah
- // Set SMBUS:0x5c[22:16] = 20 -- Set amount of idle time to 20ms
- if (IsLs2Mode() && (Family == 0x10)) {
- switch( Model ){
- case 0x4:
- case 0x5:
- if( Stepping >= 3 ) dwTempVar = 0x14;
- break;
- case 0x6:
- if( Stepping >= 2 ) dwTempVar = 0x14;
- break;
- case 0x8:
- if( Stepping >= 1 ) dwTempVar = 0x14;
- break;
- case 0x9:
- if( Stepping >= 1 ) dwTempVar = 0x14;
- break;
- case 0xA:
- dwTempVar = 0x14;
- break;
- }
- }
- // Set SMBUS:0x5c[7] = 1 -- CheckC3, set 1 to check for C3 state
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG5C, AccWidthUint32 | S3_SAVE, ~(0x7F << 16), (dwTempVar << 16) + BIT7);
- }
-
- //Message-Triggered C1E is not supported in Family 10h G34r1 HY-D0 (0x00100F90) and Family 10h C32 HY-D0 (0x00100F80) processor.
- ddValue = CpuId.REG_EAX;
- if ((getRevisionID() == SB700_A15) && (pConfig->MTC1e == CIMX_OPTION_ENABLED) && (ddValue != 0x00100F90) && (ddValue != 0x00100F80)) {
- //
- // MTC1e: For A15 (server only) - The settings here borrow the existing legacy ACPI BM_STS and BM_RLD bits as a
- // mechanism to break out from C1e under a non-OS controlled C3 state. Under this scheme, the logic will automatically
- // clear the BM_STS bit whenever it enters C1e state. Whenever BM_REQ#/IDLE_EXIT# is detected, it will cause the
- // BM_STS bit to be set and therefore causing the C state logic to exit.
- //
- // Set BMReqEnable (SMBUS:0x64[5]=1) to enable the pin as BM_REQ#/IDLE_EXIT# to the C state logic
- // Set CheckOwnReq (SMBUS:0x64[4]=0) to force IDLE_EXIT# to set BM_STS and wake from C3
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64, AccWidthUint8 | S3_SAVE, 0xEF, BIT5);
-
- // Set PCI_Active_enable (PMIO:0x61[2]=1), the secondary enable bit for SB to monitor BM_REQ#/IDLE_EXIT#
- RWPMIO(SB_PMIO_REG61, AccWidthUint8 | S3_SAVE, 0xff, BIT2);
-
- // Set auto_bm_rld (PMIO:0x9a[4]=1) so that assertion on BM_REQ#/IDLE_EXIT# pin will cause C state logic to break out from C1e
- // Set auto_clr_bm_sts (PMIO:0x9a[5]=1) will cause the C state logic to automatically clear the BM_STS bit whenever it sees a C1e entry
- RWPMIO(SB_PMIO_REG9A, AccWidthUint8 | S3_SAVE, 0xff, BIT5 + BIT4);
-
-
- // MTC1e: The logic basically counts the number of HALT_ENTER messages. When it has received the number of HALT_ENTER
- // messages equal to NumOfCpu (PMIO:0xc9[3:0]), it will generate an internal C1e command to the C state logic.
- // The count increments when it sees HALT_ENTER message after it has generated the C1e command, and it treats the
- // HALT_EXIT message as a break event.
- //
- // Set ServerCEn
- RWPMIO(SB_PMIO_REGBB, AccWidthUint8 | S3_SAVE, 0xFF, BIT7);
-
- // Enable counting HALT
- // PMIO:0xc9[4] = CountHaltMsgEn
- // PMIO:0xc9[3:0] = NumOfCpu, set to 1 since CPU logic will coordinate among cores and only generate one HALT message
- RWPMIO(SB_PMIO_REGC9, AccWidthUint8 | S3_SAVE, 0xE0, BIT4 + 1);
- }
-
- c3PopupSetting(pConfig);
-
- TRACE((DMSG_SB_TRACE, "CIMx - Exiting commonInitEarlyBoot \n"));
-}
-
-
-void commonInitEarlyPost(AMDSBCFG* pConfig){
- //early post initialization of pmio space
- programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sbEarlyPostPmioInitTbl[0]), (sizeof(sbEarlyPostPmioInitTbl)/sizeof(REG8MASK)) );
- CallBackToOEM(PULL_UP_PULL_DOWN_SETTINGS, NULL, pConfig);
-}
-
-
-// AB-Link Configuration Table
-ABTBLENTRY abTblEntry600[]={
- // Enabling Downstream Posted Transactions to Pass Non-Posted Transactions for the K8 Platform ABCFG 0x10090[8] = 1
- // ABCFG 0x10090 [16] = 1, ensures the SMI# message to be sent before the IO command is completed. The ordering of
- // SMI# and IO is important for the IO trap to work properly.
- {ABCFG,SB_AB_REG10090 ,BIT16+BIT8 ,BIT16+BIT8 },
- // Enabling UpStream DMA Access AXCFG: 0x04[2]=1
- {AXCFG,SB_AB_REG04 ,BIT2 ,BIT2 },
- // Setting B-Link Prefetch Mode ABCFG 0x80 [17] = 1 ABCFG 0x80 [18] = 1
- {ABCFG,SB_AB_REG80 ,BIT17+BIT18 ,BIT17+BIT18 },
- // Disable B-Link client's credit variable in downstream arbitration equation (for All Revisions)
- // ABCFG 0x9C[0] = 1 Disable credit variable in downstream arbitration equation
- // Enabling Additional Address Bits Checking in Downstream Register Programming
- // ABCFG 0x9C[1] = 1
- {ABCFG,SB_AB_REG9C ,BIT8+BIT1+BIT0 ,BIT8+BIT1+BIT0 },
- // Enabling IDE/PCIB Prefetch for Performance Enhancement
- // IDE prefetch ABCFG 0x10060 [17] = 1 ABCFG 0x10064 [17] = 1
- // PCIB prefetch ABCFG 0x10060 [20] = 1 ABCFG 0x10064 [20] = 1
- {ABCFG,SB_AB_REG10060 ,BIT17+BIT20 ,BIT17+BIT20 }, // IDE+PCIB prefetch enable
- {ABCFG,SB_AB_REG10064 ,BIT17+BIT20 ,BIT17+BIT20 }, // IDE+PCIB prefetch enable
- // Enabling Detection of Upstream Interrupts ABCFG 0x94 [20] = 1
- // ABCFG 0x94 [19:0] = cpu interrupt delivery address [39:20]
- {ABCFG,SB_AB_REG94 ,BIT20 ,BIT20+0x00FEE },
- // Programming cycle delay for AB and BIF clock gating
- // Enabling AB and BIF Clock Gating
- // Enabling AB Int_Arbiter Enhancement
- // Enabling Requester ID
- {ABCFG,SB_AB_REG10054, 0x00FFFFFF , 0x010407FF },
- {ABCFG,SB_AB_REG98 , 0xFFFF00FF , 0x00014700 }, // Enable the requestor ID for upstream traffic ABCFG 0x98[16]=1
-// {ABCFG,SB_AB_REG54 , 0x00FF0000 , 0x01040000 },
- {ABCFG,SB_AB_REG54 , 0x00FF0000 , 0x00040000 },
-
- {ABCFG,0,0,-1}, // This dummy entry is to clear ab index
- {-1, -1, -1, -1 },
-};
-
-
-// AB-Link Configuration Table
-ABTBLENTRY abTblForA15[]={
-
- //SMI Reordering fix
- {ABCFG, SB_AB_REG90 ,BIT21 , BIT21 },
- {ABCFG, SB_AB_REG9C ,BIT15+BIT9+BIT5 ,BIT15+BIT9+BIT5},
-
- //Posted pass NP Downstream feature
- {AX_INDXC, SB_AB_REG02, BIT9 ,BIT9 },
- {ABCFG, SB_AB_REG9C, BIT14+BIT13+BIT12+BIT11+BIT10+BIT7+BIT6 , BIT14+BIT13+BIT12+BIT11+BIT10+BIT7+BIT6},
- {ABCFG, SB_AB_REG1009C, BIT5+BIT4 , BIT5+BIT4},
-
- //Posted pass NP upstream feature
- {ABCFG, SB_AB_REG58, BIT15+BIT14+BIT13+BIT12+BIT11, BIT15+BIT14+BIT13+BIT11},
-
- //64 bit Non-posted memory write support
- {AX_INDXC, SB_AB_REG02, BIT10 ,BIT10 },
-
- {ABCFG, SB_AB_REG10090, BIT12+BIT11+BIT10+BIT9 , BIT12+BIT11+BIT10+BIT9},
-
- {ABCFG,0,0,-1}, // This dummy entry is to clear ab index
- {-1, -1, -1, -1 },
-};
-
-
-// abLinkInitBeforePciEnum - Set ABCFG registers
-void abLinkInitBeforePciEnum(AMDSBCFG* pConfig){
- ABTBLENTRY *pAbTblPtr;
-
- // disable PMIO decoding when AB is set
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT2, 0);
-
- pAbTblPtr = (ABTBLENTRY *)FIXUP_PTR(&abTblEntry600[0]);
- abcfgTbl(pAbTblPtr);
-
- if (getRevisionID() > SB700_A11){
- //Enable OHCI Prefetch
- writeAlink( (SB_AB_REG80 | (ABCFG << 30)), (readAlink((SB_AB_REG80 | (ABCFG << 30)))) | BIT0);
- //Register bit to maintain correct ordering of SMI and IO write completion
- writeAlink( (SB_AB_REG8C | (ABCFG << 30)), (readAlink((SB_AB_REG8C | (ABCFG << 30)))) | BIT8);
- }
-
- if (getRevisionID() >= SB700_A14){
- //Enable fix for TT SB01345
- writeAlink( (SB_AB_REG90 | (ABCFG << 30)), (readAlink((SB_AB_REG90 | (ABCFG << 30)))) | BIT17);
- //Disable IO Write and SMI ordering enhancement
- writeAlink( (SB_AB_REG9C | (ABCFG << 30)), (readAlink((SB_AB_REG9C | (ABCFG << 30)))) & (0xFFFFFEFF));
- }
-
- if (getRevisionID() >= SB700_A15) {
- pAbTblPtr = (ABTBLENTRY *)FIXUP_PTR(&abTblForA15[0]);
- abcfgTbl(pAbTblPtr);
- }
-
-
- // enable pmio decoding after ab is configured
- // or BYTE PTR es:[ebp+SMBUS_BUS_DEV_FUN shl 12 + SB_SMBUS_REG64], BIT2
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT2, BIT2);
-}
-
-
-void abcfgTbl(ABTBLENTRY* pABTbl){
- UINT32 ddValue;
-
- while ((pABTbl->regType) != 0xFF){
- TRACE((DMSG_SB_TRACE, "RegType: %X, RegNumber:%X, AndMask=%X, OrMask=%X \n",pABTbl->regType , pABTbl->regIndex, pABTbl->regMask, pABTbl->regData));
- if (pABTbl->regType > AX_INDXP){
- ddValue = pABTbl->regIndex | (pABTbl->regType << 30);
- writeAlink(ddValue, ((readAlink(ddValue)) & (0xFFFFFFFF^(pABTbl->regMask)))|pABTbl->regData);
- }
- else{
- ddValue = 0x30 | (pABTbl->regType << 30);
- writeAlink(ddValue, pABTbl->regIndex);
- ddValue = 0x34 | (pABTbl->regType << 30);
- writeAlink(ddValue, ((readAlink(ddValue)) & (0xFFFFFFFF^(pABTbl->regMask)))|pABTbl->regData);
- }
- ++pABTbl;
- }
-
- //Clear ALink Access Index
- ddValue = 0;
- WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &ddValue);
- TRACE((DMSG_SB_TRACE, "Exiting abcfgTbl\n"));
-}
-
-
-// programSubSystemIDs - Config Subsystem ID for all SB devices.
-void programSubSystemIDs(AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions){
- UINT32 ddTempVar;
- UINT16 dwDeviceId;
-
- RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci0Ssid);
- RWPCI((USB1_OHCI1_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci1Ssid);
- RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci2Ssid);
- RWPCI((USB2_OHCI1_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci3Ssid);
- RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci4Ssid);
-
- RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ehci0Ssid);
- RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ehci1Ssid);
-
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->SmbusSsid);
- RWPCI((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->IdeSsid);
- RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->LpcSsid);
- RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->AzaliaSsid);
-
- ddTempVar = pStaticOptions->SataIDESsid;
- if ( ((pConfig->SataClass) == AHCI_MODE) || ((pConfig->SataClass)== IDE_TO_AHCI_MODE) )
- ddTempVar = pStaticOptions->SataAHCISsid;
-
- ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, &dwDeviceId);
- if ((pConfig->SataClass) == RAID_MODE){
- ddTempVar = pStaticOptions->SataRAIDSsid;
- if (dwDeviceId==SB750_SATA_DEFAULT_DEVICE_ID)
- ddTempVar = pStaticOptions->SataRAID5Ssid;
- }
-
- if ( ((pConfig->SataClass) == AMD_AHCI_MODE) || ((pConfig->SataClass) == IDE_TO_AMD_AHCI_MODE) ) {
- ddTempVar = pStaticOptions->SataAHCISsid;
- }
- RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG2C, AccWidthUint32 | S3_SAVE, 0x00, ddTempVar);
-}
-
-void commonInitLateBoot(AMDSBCFG* pConfig){
- UINT8 dbValue;
- UINT32 ddVar;
-
- // We need to do the following setting in late post also because some bios core pci enumeration changes these values
- // programmed during early post.
- // RPR 4.5 Master Latency Timer
- // Master Latency Timer PCIB_PCI_config 0x0D/0x1B = 0x40
- // Enables the PCIB to retain ownership of the bus on the
- // Primary side and on the Secondary side when GNT# is deasserted.
- //mov BYTE PTR es:[ebp+SBP2P_BUS_DEV_FUN shl 12 + SB_P2P_REG0D], 40h
- //mov BYTE PTR es:[ebp+SBP2P_BUS_DEV_FUN shl 12 + SB_P2P_REG1B], 40h
- dbValue = 0x40;
- WritePCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG0D, AccWidthUint8, &dbValue);
- WritePCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG1B, AccWidthUint8, &dbValue);
-
- //SB P2P AutoClock control settings.
- ddVar = (pConfig->PcibAutoClkCtrlLow) | (pConfig->PcibAutoClkCtrlLow);
- WritePCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG4C, AccWidthUint32, &ddVar);
- ddVar = (pConfig->PcibClkStopOverride);
- RWPCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG50, AccWidthUint16, 0x3F, (UINT16) (ddVar << 6));
-
- if (pConfig->MobilePowerSavings){
- //If RTC clock is not driven to any chip, it should be shut-off. If system uses external RTC, then SB needs to
- //drive out RTC clk to external RTC chip. If system uses internal RTC, then this clk can be shut off.
- RWPMIO(SB_PMIO_REG68, AccWidthUint8, ~(UINT32)BIT4, (pConfig->ExternalRTCClock)<<4);
- if (!getClockMode()){
- if (!(pConfig->UsbIntClock) ){
- //If the external clock is used, the second PLL should be shut down
- RWPMIO(SB_PMIO_REGD0, AccWidthUint8, 0xFF, BIT0);
- // If external clock mode is used, the 25Mhz oscillator buffer can be turned-off by setting PMIO 0xD4[7]=1
- RWPMIO(SB_PMIO_REGD4, AccWidthUint8, 0xFF, BIT7);
- //Disable unused clocks
- RWPMIO(SB_PMIO_REGCA, AccWidthUint8, 0xFF, 0x7E);
- }
- }
- writeAlink(0x30, SB_AB_REG40);
- writeAlink(0x34, ((readAlink(0x34)) & 0xFFFF0000) | 0x008A);
-
- }
- else{
- //Don't shutoff RTC clock
- RWPMIO(SB_PMIO_REG68, AccWidthUint8, ~(UINT32)BIT4, 0);
- //Dont disable second PLL
- RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)BIT0, 0);
- //Enable the 25Mhz oscillator
- RWPMIO(SB_PMIO_REGD4, AccWidthUint8, ~(UINT32)BIT7, 0);
- RWPMIO(SB_PMIO_REGCA, AccWidthUint8, 0xFF, 0x00);
- }
-}
-
-
-void
-hpetInit (AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions)
-{
- DESCRIPTION_HEADER* pHpetTable;
-
- if (pConfig->HpetTimer == 1) {
- UINT8 dbTemp;
-
- RWPMIO(SB_PMIO_REG9A, AccWidthUint8, 0xFF, BIT7);
- // Program the HPET BAR address
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGB4, AccWidthUint32 | S3_SAVE, 0, pStaticOptions->HpetBase);
-
- // Enable HPET MMIO decoding: SMBUS:0x43[4] = 1
- // Enable HPET MSI support only when HpetMsiDis == 0
- dbTemp = (pConfig->HpetMsiDis)? BIT4 : BIT7 + BIT6 + BIT5 + BIT4;
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, dbTemp);
- // Program HPET default clock period
- if (getRevisionID() >= SB700_A13) {
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG34, AccWidthUint32 | S3_SAVE, 0x00, 0x429B17E);
- }
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT3);
- // Enable High Precision Event Timer (also called Multimedia Timer) interrupt
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + (SB_SMBUS_REG64+1), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT2, BIT2);
- }
- else {
- if (!(pConfig->S3Resume)) {
-// pHpetTable = (DESCRIPTION_HEADER*)ACPI_LocateTable('TEPH');
- pHpetTable = (DESCRIPTION_HEADER*)ACPI_LocateTable(Int32FromChar ('T', 'E', 'P', 'H'));
- if (pHpetTable != NULL) {
-// pHpetTable->Signature = 'HPET';
- pHpetTable->Signature = Int32FromChar ('T', 'E', 'P', 'H');
- }
- }
- }
-}
-
-
-void c3PopupSetting(AMDSBCFG* pConfig){
- UINT8 dbTemp;
- CPUID_DATA CpuId;
-
- CpuidRead (0x01, &CpuId);
- //RPR 2.3 C-State and VID/FID Change
- dbTemp = GetNumberOfCpuCores();
- if (dbTemp > 1){
- //PM_IO 0x9A[5]=1, For system with dual core CPU, set this bit to 1 to automatically clear BM_STS when the C3 state is being initiated.
- //PM_IO 0x9A[4]=1, For system with dual core CPU, set this bit to 1 and BM_STS will cause C3 to wakeup regardless of BM_RLD
- //PM_IO 0x9A[2]=1, Enable pop-up for C3. For internal bus mastering or BmReq# from the NB, the SB will de-assert
- //LDTSTP# (pop-up) to allow DMA traffic, then assert LDTSTP# again after some idle time.
- RWPMIO(SB_PMIO_REG9A, AccWidthUint8, 0xFF, BIT5+BIT4+BIT2);
- }
-
- //SB700 needs to changed for RD790 support
- //PM_IO 0x8F [4] = 0 for system with RS690
- //Note: RS690 north bridge has AllowLdtStop built for both display and PCIE traffic to wake up the HT link.
- //BmReq# needs to be ignored otherwise may cause LDTSTP# not to toggle.
- //PM_IO 0x8F[5]=1, Ignore BM_STS_SET message from NB
- RWPMIO(SB_PMIO_REG8F, AccWidthUint8, ~(UINT32)(BIT5+BIT4), BIT5);
-
- //LdtStartTime = 10h for minimum LDTSTP# de-assertion duration of 16us in StutterMode. This is to guarantee that
- //the HT link has been safely reconnected before it can be disconnected again. If C3 pop-up is enabled, the 16us also
- //serves as the minimum idle time before LDTSTP# can be asserted again. This allows DMA to finish before the HT
- //link is disconnected.
- //Increase LDTSTOP Deassertion time for SP5100 to 20us, SB700 remains the same
- dbTemp = (IsServer())? 0x14 : 0x10;
- RWPMIO(SB_PMIO_REG88, AccWidthUint8, 0x00, dbTemp);
-
- //This setting provides 16us delay before the assertion of LDTSTOP# when C3 is entered. The
- //delay will allow USB DMA to go on in a continous manner
- RWPMIO(SB_PMIO_REG89, AccWidthUint8, 0x00, 0x10);
-
- //Set this bit to allow pop-up request being latched during the minimum LDTSTP# assertion time
- RWPMIO(SB_PMIO_REG52, AccWidthUint8, 0xFF, BIT7);
-
-}
-
diff --git a/src/vendorcode/amd/cimx/sb700/SBCMNLIB.c b/src/vendorcode/amd/cimx/sb700/SBCMNLIB.c
deleted file mode 100644
index 130dbc4..0000000
--- a/src/vendorcode/amd/cimx/sb700/SBCMNLIB.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/*****************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *
- ***************************************************************************/
-
-
-#include "Platform.h"
-
-UINT8 isEcPresent(){
- UINT8 dbFlag;
- UINT16 dwVar0;
-
- //Read the EC configuration register base address from LPCCfg_A4[15:1]
- //Write 0x5A to the EC config index register to unlock the access
- //Write 0x20 to the EC config index register to select the device ID register
- //Read the value of device ID register from the EC config data register
- //If the value read is 0xB7, then EC is enabled.
- //Write 0xA5 to re-lock the EC config index register if EC is enabled.
-
- ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwVar0);
- dwVar0 &= 0xFFFE;
- RWIO(dwVar0, AccWidthUint8, 0, 0x5A);
- RWIO(dwVar0, AccWidthUint8, 0, 0x20);
- ReadIO(dwVar0+1, AccWidthUint8, &dbFlag);
- RWIO(dwVar0, AccWidthUint8, 0, 0xA5);
-
- return ( dbFlag == 0xB7);
-}
-
-void
-getSbInformation (
-SB_INFORMATION *sbInfo){
- UINT16 dwDevId;
- UINT8 dbRev;
-
- ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG02, AccWidthUint16 | S3_SAVE, &dwDevId);
- ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08, AccWidthUint8 | S3_SAVE, &dbRev);
- sbInfo->sbModelMask = SB_MODEL_UNKNOWN;
- if ( (dwDevId == SB7XX_DEVICE_ID) && (dbRev <= SB_Rev_Sb7xx_A14) ){
- sbInfo->sbModelMask |= SB_MODEL_SB700;
- sbInfo->sbModelMask |= SB_MODEL_SR5690;
- sbInfo->sbRev = dbRev;
- ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint8 | S3_SAVE, &dbRev);
- if (dbRev & 01)
- sbInfo->sbModelMask |= SB_MODEL_SB750;
- if (isEcPresent())
- sbInfo->sbModelMask |= SB_MODEL_SB710;
- return;
- }
-}
-
-
-SB_CAPABILITY_SETTING
-getSbCapability (
-SB_CAPABILITY_ITEM sbCapabilityItem
-)
-{
- SB_CAPABILITY_SETTING sbCapSetting=SB_UNKNOWN;
- UINT32 ddTemp0;
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 00);
- ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG10, AccWidthUint32, &ddTemp0);
-
- if (sbCapabilityItem < Sb_Unknown_Capability)
- sbCapSetting = ((ddTemp0 >> (sbCapabilityItem << 1) ) & 0x03);
-
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT3);
- return sbCapSetting;
-}
-
-
-void
-setSbCapability (
-SB_CAPABILITY_ITEM sbCapabilityItem, SB_CAPABILITY_SETTING sbCapSetting
-)
-{
- UINT32 ddTemp0;
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 00);
- ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG10, AccWidthUint32, &ddTemp0);
- if ( (sbCapabilityItem < Sb_Unknown_Capability) & (sbCapSetting < Sb_Cap_Setting_Unknown) )
- ddTemp0 = (ddTemp0 & ~(0x03 << (sbCapabilityItem << 1))) | ( (sbCapSetting & 0x03) << (sbCapabilityItem << 1));
- WritePCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG10, AccWidthUint32, &ddTemp0);
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT3);
-}
diff --git a/src/vendorcode/amd/cimx/sb700/SBCMNLIB.h b/src/vendorcode/amd/cimx/sb700/SBCMNLIB.h
deleted file mode 100644
index e737bc9..0000000
--- a/src/vendorcode/amd/cimx/sb700/SBCMNLIB.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*;********************************************************************************
-;
-; Copyright (C) 2012 Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#ifndef _AMD_SBLIB_H_
-#define _AMD_SBLIB_H_
-
-//SB7xx Family
-#define SB7xx_DEVICE_ID 0x4385
-#define SB700 0x00
-#define SB750 0x01
-#define SB710 0x02
-
-//SB800 Family
-#define SB800 0x10
-
-#define SB_UNKNOWN 0xFF
-
-//SB700 Revision IDs
-#define SB700_A11 0x39
-#define SB700_A12 0x3A
-#define SB700_A13 0x3B
-#define SB700_A14 0x3C
-
-#define SB_Rev_Sb7xx_A11 0x39
-#define SB_Rev_Sb7xx_A12 0x3A
-#define SB_Rev_Sb7xx_A13 0x3B
-#define SB_Rev_Sb7xx_A14 0x3C
-
-
-typedef enum {
- Sb_Raid0_1_Capability, ///
- Sb_Raid5_Capability, ///
- Sb_Ahci_Capability, ///
- Sb_Unknown_Capability
-} SB_CAPABILITY_ITEM;
-
-
-typedef enum {
- Sb_Cap_Setting_Auto,
- Sb_Cap_Setting_Enabled,
- Sb_Cap_Setting_Disabled,
- Sb_Cap_Setting_Unknown
-} SB_CAPABILITY_SETTING;
-
-
-#define SB_MODEL_SB700 BIT0
-#define SB_MODEL_SB750 BIT1
-#define SB_MODEL_SB710 BIT2
-#define SB_MODEL_SR5690 BIT3
-#define SB_MODEL_UNKNOWN BIT31
-
-typedef struct
-{
- UINT32 sbModelMask;
- UINT8 sbRev;
-}SB_INFORMATION;
-
-
-void getSbInformation (SB_INFORMATION *sbInfo);
-SB_CAPABILITY_SETTING getSbCapability (SB_CAPABILITY_ITEM sbCapabilityItem);
-void setSbCapability (SB_CAPABILITY_ITEM sbCapabilityItem, SB_CAPABILITY_SETTING sbCapSetting);
-
-#endif //#ifndef _AMD_SBLIB_H_
diff --git a/src/vendorcode/amd/cimx/sb700/SBDEF.h b/src/vendorcode/amd/cimx/sb700/SBDEF.h
deleted file mode 100644
index 01fc1b5..0000000
--- a/src/vendorcode/amd/cimx/sb700/SBDEF.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/*;********************************************************************************
-;
-; Copyright (C) 2012 Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#ifndef _AMD_SBDEF_H_
-#define _AMD_SBDEF_H_
-
-//AMD Library Routines
-
-UINT64
-MsrRead (
- IN UINT32 MsrAddress
- );
-
-VOID
-MsrWrite (
- IN UINT32 MsrAddress,
- IN UINT64 Value
- );
-
-void ReadIO(UINT16 Address, UINT8 OpFlag, void *Value);
-void WriteIO(UINT16 Address, UINT8 OpFlag, void *Value);
-void ReadPCI(UINT32 Address, UINT8 OpFlag, void *Value);
-void WritePCI(UINT32 Address,UINT8 OpFlag, void *Value);
-void RWPCI(UINT32 Address,UINT8 OpFlag,UINT32 Mask,UINT32 Data);
-void ReadIndexPCI32(UINT32 PciAddress,UINT32 IndexAddress,void* Value);
-void WriteIndexPCI32(UINT32 PciAddress,UINT32 IndexAddress,UINT8 OpFlag,void* Value);
-void RWIndexPCI32(UINT32 PciAddress,UINT32 IndexAddress,UINT8 OpFlag,UINT32 Mask,UINT32 Data);
-void RWIO (UINT16 Address, UINT8 OpFlag, UINT32 Mask, UINT32 Data);
-void ReadMEM(UINT32 Address,UINT8 OpFlag, void* Value);
-void WriteMEM(UINT32 Address,UINT8 OpFlag, void* Value);
-void RWMEM(UINT32 Address,UINT8 OpFlag,UINT32 Mask,UINT32 Data);
-UINT32 IsFamily10(void);
-UINT64 ReadMSR(UINT32 Address);
-void WriteMSR(UINT32 Address,UINT64 Value);
-void RWMSR(UINT32 Address, UINT64 Mask, UINT64 Value);
-void* LocateImage(UINT32 Signature);
-void* CheckImage( UINT32 Signature, void* ImagePtr);
-void Stall(UINT32 uSec);
-void Reset(void);
-CIM_STATUS RWSMBUSBlock(UINT8 Controller, UINT8 Address, UINT8 Offset, UINT8 BufferSize, UINT8* BufferPrt);
-void InitSerialOut(void);
-void ReadPMIO(UINT8 Address, UINT8 OpFlag, void* Value);
-void WritePMIO(UINT8 Address, UINT8 OpFlag, void* Value);
-void RWPMIO(UINT8 Address, UINT8 OpFlag, UINT32 AndMask, UINT32 OrMask);
-void ReadPMIO2(UINT8 Address, UINT8 OpFlag, void* Value);
-void WritePMIO2(UINT8 Address, UINT8 OpFlag, void* Value);
-void RWPMIO2(UINT8 Address, UINT8 OpFlag, UINT32 AndMask, UINT32 OrMask);
-void outPort80(UINT32 pcode);
-UINT8 GetNumberOfCpuCores(void);
-UINT8 ReadNumberOfCpuCores(void);
-UINT8 GetByteSum(void* pData, UINT32 Length);
-UINT32 readAlink(UINT32 Index);
-void writeAlink(UINT32 Index,UINT32 Data);
-
-//----------------------------------------------------------------------------------------------
-//----------------------------------------------------------------------------------------------
-void azaliaInitAfterPciEnum (AMDSBCFG* pConfig);
-
-void SendBytePort(UINT8 Data);
-void SendStringPort(char* pstr);
-void ItoA(UINT32 Value,int Radix,char* pstr);
-AMDSBCFG* getConfigPointer(void);
-void saveConfigPointer(AMDSBCFG* pConfig);
-
-
-UINT32 GetFixUp(void);
-
-void sataInitAfterPciEnum(AMDSBCFG* pConfig);
-void sataInitBeforePciEnum(AMDSBCFG* pConfig);
-void sataInitLatePost(AMDSBCFG* pConfig);
-void sataDriveDetection(AMDSBCFG* pConfig, UINT32 ddBar5);
-void sataPhyWorkaround(AMDSBCFG* pConfig, UINT32 ddBar5);
-void forceOOB(UINT32 ddBar5);
-void shutdownUnconnectedSataPortClock(AMDSBCFG* pConfig, UINT32 ddBar5);
-void restrictSataCapabilities(AMDSBCFG* pConfig);
-
-
-void commonInitEarlyBoot(AMDSBCFG* pConfig);
-void commonInitEarlyPost(AMDSBCFG* pConfig);
-void setRevisionID(void);
-UINT8 getRevisionID(void);
-UINT8 IsServer (void);
-UINT8 IsLs2Mode (void);
-void abLinkInitBeforePciEnum(AMDSBCFG* pConfig);
-void abcfgTbl(ABTBLENTRY* pABTbl);
-void programSubSystemIDs(AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions);
-void commonInitLateBoot(AMDSBCFG* pConfig);
-void hpetInit(AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions);
-void c3PopupSetting(AMDSBCFG* pConfig);
-
-void sbBeforePciInit (AMDSBCFG* pConfig);
-void sbAfterPciInit(AMDSBCFG* pConfig);
-void sbLatePost(AMDSBCFG* pConfig);
-void sbBeforePciRestoreInit(AMDSBCFG* pConfig);
-void sbAfterPciRestoreInit(AMDSBCFG* pConfig);
-void sbSmmAcpiOn(AMDSBCFG* pConfig);
-UINT32 GetPciebase(void);
-UINT32 CallBackToOEM(UINT32 Func, UINTN Data,AMDSBCFG* pConfig);
-void sbSmmService(AMDSBCFG* pConfig);
-void softwareSMIservice(void);
-
-void sbPowerOnInit (AMDSBCFG *pConfig);
-void programPciByteTable(REG8MASK* pPciByteTable, UINT16 dwTableSize);
-void programPmioByteTable(REG8MASK* pPmioByteTable, UINT16 dwTableSize);
-UINT8 getClockMode(void);
-UINT16 readStrapStatus (void);
-
-void usbInitBeforePciEnum(AMDSBCFG* pConfig);
-void usbInitAfterPciInit(AMDSBCFG* pConfig);
-void usbInitMidPost(AMDSBCFG* pConfig);
-void programOhciMmioForEmulation(void);
-
-void fcInitBeforePciEnum(AMDSBCFG* pConfig);
-
-unsigned char ReadIo8 (IN unsigned short Address);
-unsigned short ReadIo16 (IN unsigned short Address);
-unsigned int ReadIo32 (IN unsigned short Address);
-void WriteIo8 (IN unsigned short Address, IN unsigned char Data);
-void WriteIo16 (IN unsigned short Address, IN unsigned short Data);
-void WriteIo32 (IN unsigned short Address, IN unsigned int Data);
-unsigned long long ReadTSC (void);
-void CpuidRead (IN unsigned int Func, IN OUT CPUID_DATA* Data);
-
-#ifndef NO_EC_SUPPORT
-void EnterEcConfig(void);
-void ExitEcConfig(void);
-void ReadEC8(UINT8 Address, UINT8* Value);
-void WriteEC8(UINT8 Address, UINT8* Value);
-void RWEC8(UINT8 Address, UINT8 AndMask, UINT8 OrMask);
-void ecPowerOnInit(BUILDPARAM *pBuildOptPtr, AMDSBCFG *pConfig);
-void ecInitBeforePciEnum(AMDSBCFG* pConfig);
-void ecInitLatePost(AMDSBCFG* pConfig);
-#endif
-UINT8 isEcPresent(void);
-
-void DispatcherEntry(void *pConfig);
-AGESA_STATUS AmdSbDispatcher(void *pConfig);
-void AMDFamily15CpuLdtStopReq(void);
-
-#endif //#ifndef _AMD_SBDEF_H_
diff --git a/src/vendorcode/amd/cimx/sb700/SBMAIN.c b/src/vendorcode/amd/cimx/sb700/SBMAIN.c
deleted file mode 100644
index 7468eb2..0000000
--- a/src/vendorcode/amd/cimx/sb700/SBMAIN.c
+++ /dev/null
@@ -1,289 +0,0 @@
-/*****************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *
- ***************************************************************************/
-
-
-#include "Platform.h"
-
-#ifndef B1_IMAGE
-
-BUILDPARAM DfltStaticOptions={
- BIOS_SIZE, // BIOS Size
- LEGACY_FREE, // Legacy Free Option
- 0x00, // Dummy space holder
-
- 0x00, // ECKbd disable/enable
- 0x00, // EcChannel0 disable/enable
- 0x00, // Dummy space holder1
-
- SMBUS0_BASE_ADDRESS, // Smbus Base Address;
- SMBUS1_BASE_ADDRESS, // Smbus Base Address;
- SIO_PME_BASE_ADDRESS, // SIO PME Base Address
- WATCHDOG_TIMER_BASE_ADDRESS, // Watchdog Timer Base Address
- SPI_BASE_ADDRESS,
-
- PM1_EVT_BLK_ADDRESS, // AcpiPm1EvtBlkAddr;
- PM1_CNT_BLK_ADDRESS, // AcpiPm1CntBlkAddr;
- PM1_TMR_BLK_ADDRESS, // AcpiPmTmrBlkAddr;
- CPU_CNT_BLK_ADDRESS, // CpuControlBlkAddr;
- GPE0_BLK_ADDRESS, // AcpiGpe0BlkAddr;
- SMI_CMD_PORT, // SmiCmdPortAddr;
- ACPI_PMA_CNT_BLK_ADDRESS, // AcpiPmaCntBlkAddr;
-
- EC_LDN5_MAILBOX_ADDRESS,
- EC_LDN5_IRQ,
- EC_LDN9_MAILBOX_ADDRESS, // EC LDN9 Mailbox address
- RESERVED_VALUE,
- RESERVED_VALUE,
- RESERVED_VALUE,
- RESERVED_VALUE,
-
- HPET_BASE_ADDRESS, // HPET Base address
-
- SATA_IDE_MODE_SSID,
- SATA_RAID_MODE_SSID,
- SATA_RAID5_MODE_SSID,
- SATA_AHCI_SSID,
-
- OHCI0_SSID,
- OHCI1_SSID,
- EHCI0_SSID,
- OHCI2_SSID,
- OHCI3_SSID,
- EHCI1_SSID,
- OHCI4_SSID,
- SMBUS_SSID,
- IDE_SSID,
- AZALIA_SSID,
- LPC_SSID,
- P2P_SSID,
-};
-
-
-/*********************************************************************************
-*
-* Routine Description: Config SB Before PCI INIT
-*
-* Arguments:
-*
-* pConfig - SBconfiguration
-*
-* Returns:
-*
-* void
-*
-**********************************************************************************/
-void sbBeforePciInit (AMDSBCFG* pConfig){
- BUILDPARAM *pStaticOptions;
-
- pStaticOptions = &pConfig->BuildParameters;
- TRACE((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciInit \n"));
- commonInitEarlyBoot(pConfig);
- commonInitEarlyPost(pConfig);
-#ifndef NO_EC_SUPPORT
- ecInitBeforePciEnum(pConfig);
-#endif
- usbInitBeforePciEnum(pConfig); // USB POST TIME Only
- fcInitBeforePciEnum(pConfig); // Preinit flash controller
- sataInitBeforePciEnum(pConfig); // Init SATA class code and PHY
- programSubSystemIDs(pConfig, pStaticOptions); // Set subsystem/vendor ID
-
- TRACE((DMSG_SB_TRACE, "CIMx - Exiting sbBeforePciInit \n"));
-}
-
-
-/*********************************************************************************
-*
-* Routine Description: Config SB After PCI INIT
-*
-* Arguments:
-*
-* pConfig - SBconfiguration
-*
-* Returns: void
-*
-* Reference: atiSbAfterPciInit
-*
-**********************************************************************************/
-void sbAfterPciInit(AMDSBCFG* pConfig){
- BUILDPARAM *pStaticOptions;
-
- TRACE((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciInit \n"));
-
- pStaticOptions = &pConfig->BuildParameters;
- usbInitMidPost(pConfig); //usb initialization which is required only during post
- usbInitAfterPciInit(pConfig); // Init USB MMIO
- sataInitAfterPciEnum(pConfig); // SATA port enumeration
- azaliaInitAfterPciEnum(pConfig); // Detect and configure High Definition Audio
-
- TRACE((DMSG_SB_TRACE, "CIMx - Exiting sbAfterPciInit \n"));
-}
-
-
-/*********************************************************************************
-*
-* Routine Description: Config SB during late POST
-*
-* Arguments:
-*
-* pConfig - SBconfiguration
-*
-* Returns: void
-*
-* Reference: atiSbLatePost
-*
-**********************************************************************************/
-void sbLatePost(AMDSBCFG* pConfig){
- UINT16 dwVar;
- BUILDPARAM *pStaticOptions;
- pStaticOptions = &pConfig->BuildParameters;
- TRACE((DMSG_SB_TRACE, "CIMx - Entering sbLatePost \n"));
- ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG02, AccWidthUint16, &dwVar);
- if (dwVar != SB7XX_DEVICE_ID){
- // Display message that the SB is wrong and stop the system
- TRACE((DMSG_SB_TRACE, "Current system does not have SB700 chipset. Stopping\n"));
- for(;;);
- }
- commonInitLateBoot(pConfig);
- sataInitLatePost(pConfig);
- hpetInit(pConfig, pStaticOptions); // SB Configure HPET base and enable bit
-#ifndef NO_EC_SUPPORT
- ecInitLatePost(pConfig);
-#endif
-}
-
-/*********************************************************************************
-*
-* Routine Description: Config SB before ACPI S3 resume PCI config device restore
-*
-* Arguments:
-*
-* pConfig - SBconfiguration
-*
-* Returns: void
-*
-* Reference: AtiSbBfPciRestore
-*
-**********************************************************************************/
-void sbBeforePciRestoreInit(AMDSBCFG* pConfig){
- BUILDPARAM *pStaticOptions;
-
- TRACE((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciRestoreInit \n"));
-
- pConfig->S3Resume = 1;
-
- pStaticOptions = &pConfig->BuildParameters;
- commonInitEarlyBoot(pConfig); // set /SMBUS/ACPI/IDE/LPC/PCIB
- abLinkInitBeforePciEnum(pConfig); // Set ABCFG registers
- usbInitBeforePciEnum(pConfig); // USB POST TIME Only
- fcInitBeforePciEnum(pConfig); // Preinit flash controller
- sataInitBeforePciEnum(pConfig);
- programSubSystemIDs(pConfig, pStaticOptions); // Set subsystem/vendor ID
-}
-
-
-/*********************************************************************************
-*
-* Routine Description: Config SB after ACPI S3 resume PCI config device restore
-*
-* Arguments:
-*
-* pConfig - SBconfiguration
-*
-* Returns: void
-*
-* Reference: AtiSbAfPciRestore
-*
-**********************************************************************************/
-void sbAfterPciRestoreInit(AMDSBCFG* pConfig){
- BUILDPARAM *pStaticOptions;
-
- pConfig->S3Resume = 1;
-
- pStaticOptions = &pConfig->BuildParameters;
- TRACE((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciRestoreInit \n"));
-
- commonInitLateBoot(pConfig);
- sataInitAfterPciEnum(pConfig);
- azaliaInitAfterPciEnum(pConfig); // Detect and configure High Definition Audio
- hpetInit(pConfig, pStaticOptions); // SB Configure HPET base and enable bit
- sataInitLatePost(pConfig);
- sbSmmAcpiOn(pConfig);
-}
-
-
-/*++
-
-Routine Description:
-
- SB config hook during ACPI_ON
-
-Arguments:
-
- pConfig - SBconfiguration
-
-Returns:
-
- void
-
---*/
-
-void sbSmmAcpiOn(AMDSBCFG* pConfig){
- UINT32 ddBar5;
- UINT8 dbPort;
-
- //RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+2, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT1+BIT0), 0);
- if (getRevisionID() >= SB700_A13)
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); //Enable Legacy DMA prefetch enhancement
-
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+2, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT1+BIT0), 0);
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64+3, AccWidthUint8| S3_SAVE, ~(UINT32)BIT7, 0);
- programOhciMmioForEmulation();
-
- // For IDE_TO_AHCI_MODE and IDE_TO_AMD_AHCI_MODE, clear Interrupt Status register for all ports
- ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5);
- if ((pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE)){
- for (dbPort = 0; dbPort <= 5; dbPort++) {
- RWMEM(ddBar5 + SB_SATA_BAR5_REG110 + dbPort * 0x80, AccWidthUint32, 0x00, 0xFFFFFFFF);
- }
- }
-}
-
-
-UINT32 CallBackToOEM(UINT32 Func, UINTN Data,AMDSBCFG* pConfig){
- UINT32 Result=0;
- TRACE((DMSG_SB_TRACE,"OEM Call Back Func [%x] Data [%x]\n",Func,Data));
- if (pConfig->StdHeader.pCallBack==NULL)
- return Result;
- Result = (*(pConfig->StdHeader.pCallBack))(Func,Data,pConfig);
- TRACE((DMSG_SB_TRACE,"SB Hook Status [%x]\n",Result));
- return Result;
-}
-
-#endif
diff --git a/src/vendorcode/amd/cimx/sb700/SBPort.c b/src/vendorcode/amd/cimx/sb700/SBPort.c
deleted file mode 100644
index 6c5740b..0000000
--- a/src/vendorcode/amd/cimx/sb700/SBPort.c
+++ /dev/null
@@ -1,441 +0,0 @@
-/*****************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *
- ***************************************************************************/
-
-
-#include "Platform.h"
-
-REG8MASK sbPorInitPciTable[] = {
- // SMBUS Device(Bus 0, Dev 20, Func 0)
- {0x00, SMBUS_BUS_DEV_FUN, 0},
- {SB_SMBUS_REGD0+2, 0x00, 0x01},
- {SB_SMBUS_REG40, 0x00, 0x44},
- {SB_SMBUS_REG40+1, 0xFF, 0xE9}, //Set smbus pci config 0x40[14]=1, This bit is used for internal bus flow control.
- {SB_SMBUS_REG64, 0x00, 0xBF}, //SB_SMBUS_REG64[13]=1, delays back to back interrupts to the CPU
- {SB_SMBUS_REG64+1, 0x00, 0x78},
- {SB_SMBUS_REG64+2, ~(UINT8)BIT6, 0x9E},
- {SB_SMBUS_REG64+3, 0x0F, 0x02},
- {SB_SMBUS_REG68+1, 0x00, 0x90},
- {SB_SMBUS_REG6C, 0x00, 0x20},
- {SB_SMBUS_REG78, 0x00, 0xFF},
- {SB_SMBUS_REG04, 0x00, 0x07},
- {SB_SMBUS_REG04+1, 0x00, 0x04},
- {SB_SMBUS_REGE1, 0x00, 0x99}, //RPR recommended setting, Sections "SMBUS Pci Config" & "IMC Access Control"
- {SB_SMBUS_REGAC, ~(UINT8)BIT4, BIT1},
- {SB_SMBUS_REG60+2, ~(UINT8)(BIT1+BIT0) , 0x24}, // Disabling Legacy USB Fast SMI# Smbus_PCI_config 0x62 [5] = 1. Legacy USB
- // can request SMI# to be sent out early before IO completion.
- // Some applications may have problems with this feature. The BIOS should set this bit
- // to 1 to disable the feature. Enabling Legacy Interrupt Smbus_PCI_Config 0x62[2]=1.
- {0xFF, 0xFF, 0xFF},
-
- // LPC Device(Bus 0, Dev 20, Func 3)
- {0x00, LPC_BUS_DEV_FUN, 0},
- {SB_LPC_REG40, 0x00, 0x04},
- {SB_LPC_REG48, 0x00, 0x07},
- {SB_LPC_REG4A, 0x00, 0x20}, // Port Enable for IO Port 80h.
- {SB_LPC_REG78, ~(UINT8)BIT0, 0x00},
- {SB_LPC_REG7C, 0x00, 0x05},
- {SB_LPC_REGB8+3, ~(UINT8)BIT0, BIT7+BIT6+BIT5+BIT3+BIT0}, //RPR recommended setting,Section "IO / Mem Decoding" & "SPI bus"
- {0xFF, 0xFF, 0xFF},
-
- // P2P Bridge(Bus 0, Dev 20, Func 4)
- {0x00, SBP2P_BUS_DEV_FUN, 0},
- {SB_P2P_REG40, 0x00, 0x26}, // Enabling PCI-bridge subtractive decoding & PCI Bus 64-byte DMA Read Access
- {SB_P2P_REG4B, 0xFF, BIT6+BIT7+BIT4},
- {SB_P2P_REG1C, 0x00, 0x11},
- {SB_P2P_REG1D, 0x00, 0x11},
- {SB_P2P_REG04, 0x00, 0x21},
- {SB_P2P_REG50, 0x02, 0x01}, // PCI Bridge upstream dual address window
- {0xFF, 0xFF, 0xFF},
-};
-
-
-REG8MASK sbA13PorInitPciTable[] = {
- // SMBUS Device(Bus 0, Dev 20, Func 0)
- {0x00, SMBUS_BUS_DEV_FUN, 0},
- {SB_SMBUS_REG43, ~(UINT8)BIT3, 0x00}, //Make some hidden registers of smbus visible.
- {SB_SMBUS_REG38, (UINT8)~BIT7, 00},
- {SB_SMBUS_REGAC+1, ~(UINT8)BIT5, 0}, //Enable SATA test/enhancement mode
- {SB_SMBUS_REG43, 0xFF, BIT3}, //Make some hidden registers of smbus invisible.
- {0xFF, 0xFF, 0xFF},
-};
-
-
-REG8MASK sbA14PorInitPciTable[] = {
- // LPC Device(Bus 0, Dev 20, Func 3)
- {0x00, LPC_BUS_DEV_FUN, 0},
- {SB_LPC_REG8C+2, ~(UINT8)BIT1, 00},
- {0xFF, 0xFF, 0xFF},
-};
-
-REG8MASK sbPorPmioInitTbl[] = {
- // index andmask ormask
- {SB_PMIO_REG67, 0xFF, 0x02},
- {SB_PMIO_REG37, 0xFF, 0x04}, // Configure pciepme as rising edge
- {SB_PMIO_REG50, 0x00, 0xE0}, // Enable CPU_STP (except S5) & PCI_STP
- {SB_PMIO_REG60, 0xFF, 0x20}, // Enable Speaker
- {SB_PMIO_REG65, (UINT8)~(BIT4+BIT7), 0x00},// Clear PM_IO 0x65[4] UsbResetByPciRstEnable to avoid S3 reset to reset USB
- {SB_PMIO_REG55, ~(UINT8)BIT6, 0x07}, // Select CIR wake event to ACPI.GEVENT[23] & Clear BIT6 SoftPciRst for safety
- {SB_PMIO_REG66, 0xFF, BIT5}, // Configure keyboard reset to generate pci reset
- {SB_PMIO_REGB2, 0xFF, BIT7},
- {SB_PMIO_REG0E, 0xFF, BIT3}, // Enable ACPI IO decoding
- {SB_PMIO_REGD7, 0xF6, 0x80},
- {SB_PMIO_REG7C, 0xFF, BIT4}, // enable RTC AltCentury register
-
- {SB_PMIO_REG75, 0xC0, 0x05}, // PME_TURN_OFF_MSG during ASF shutdown
- {SB_PMIO_REG52, 0xC0, 0x08},
-
- {SB_PMIO_REG8B, 0x00, 0x10},
- {SB_PMIO_REG69, 0xF9, 0x01 << 1}, // [Updated RPR] Set default WDT resolution to 10ms
-};
-
-REG8MASK sbA13PorPmioInitTbl[]={
- // index andmask ormask
- {SB_PMIO_REGD7, 0xFF, BIT5+BIT0}, //Fixes for TT SB00068 & SB01054 (BIT5 & BIT0 correspondingly)
- {SB_PMIO_REGBB, (UINT8)~BIT7, BIT6+BIT5}, //Fixes for TT SB00866 & SB00696 (BIT6 & BIT5 correspondingly)
- // Always clear [7] to begin with SP5100 C1e disabled
-
-// {SB_PMIO_REG65, 0xFF, BIT7},
-// {SB_PMIO_REG75, 0xC0, 0x01}, // PME_TURN_OFF_MSG during ASF shutdown
-// {SB_PMIO_REG52, 0xC0, 0x02},
-
-};
-
-
-void sbPowerOnInit (AMDSBCFG *pConfig){
- UINT8 dbVar0, dbVar1, dbValue;
- UINT16 dwTempVar;
- BUILDPARAM *pBuildOptPtr;
-
- TRACE((DMSG_SB_TRACE, "CIMx - Entering sbPowerOnInit \n"));
-
- setRevisionID();
- ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, &dwTempVar);
- if (dwTempVar == SB750_SATA_DEFAULT_DEVICE_ID)
- RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint8 | S3_SAVE, 0xFF, 0x01);
-
- // Set A-Link bridge access address. This address is set at device 14h, function 0,
- // register 0f0h. This is an I/O address. The I/O address must be on 16-byte boundry.
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGF0, AccWidthUint32, 00, ALINK_ACCESS_INDEX);
-
- writeAlink(0x80000004, 0x04); // RPR 3.3 Enabling upstream DMA Access
- writeAlink(0x30, 0x10); //AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform.
- writeAlink(0x34, readAlink(0x34) | BIT9);
-
- if (!(pConfig->ResetCpuOnSyncFlood)){
- //Enable reset on sync flood
- writeAlink( (UINT32)( ((UINT32)SB_AB_REG10050) | ((UINT32)ABCFG << 30)),
- (UINT32)( readAlink((((UINT32)SB_AB_REG10050) | ((UINT32)ABCFG << 30))) | ((UINT32)BIT2) ));
- }
-
- pBuildOptPtr = &(pConfig->BuildParameters);
-
- WritePCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG90, AccWidthUint32 | S3_SAVE, &(pBuildOptPtr->Smbus0BaseAddress) );
-
- dwTempVar = pBuildOptPtr->Smbus1BaseAddress & (UINT16)~BIT0;
- if( dwTempVar != 0 ){
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG58, AccWidthUint16 | S3_SAVE, 00, (dwTempVar|BIT0));
- // Disable ASF Slave controller on SB700 rev A15.
- if (getRevisionID() == SB700_A15) {
- RWIO((dwTempVar+0x0D), AccWidthUint8, (UINT8)~BIT6, BIT6);
- }
- }
-
- WritePCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pBuildOptPtr->SioPmeBaseAddress));
- RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F,(pBuildOptPtr->SpiRomBaseAddress));
-
- WritePMIO(SB_PMIO_REG20, AccWidthUint16, &(pBuildOptPtr->AcpiPm1EvtBlkAddr));
- WritePMIO(SB_PMIO_REG22, AccWidthUint16, &(pBuildOptPtr->AcpiPm1CntBlkAddr));
- WritePMIO(SB_PMIO_REG24, AccWidthUint16, &(pBuildOptPtr->AcpiPmTmrBlkAddr));
- WritePMIO(SB_PMIO_REG26, AccWidthUint16, &(pBuildOptPtr->CpuControlBlkAddr));
- WritePMIO(SB_PMIO_REG28, AccWidthUint16, &(pBuildOptPtr->AcpiGpe0BlkAddr));
- WritePMIO(SB_PMIO_REG2A, AccWidthUint16, &(pBuildOptPtr->SmiCmdPortAddr));
- WritePMIO(SB_PMIO_REG2C, AccWidthUint16, &(pBuildOptPtr->AcpiPmaCntBlkAddr));
- RWPMIO(SB_PMIO_REG2E, AccWidthUint16, 0x00,(pBuildOptPtr->SmiCmdPortAddr)+8);
- WritePMIO(SB_PMIO_REG6C, AccWidthUint32, &(pBuildOptPtr->WatchDogTimerBase));
-
- //Program power on pci init table
- programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbPorInitPciTable[0]), sizeof(sbPorInitPciTable)/sizeof(REG8MASK) );
- //Program power on pmio init table
- programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sbPorPmioInitTbl[0]), (sizeof(sbPorPmioInitTbl)/sizeof(REG8MASK)) );
-
- dbValue = 0x00;
- ReadIO (SB_IOMAP_REGC14, AccWidthUint8, &dbValue);
- dbValue &= 0xF3;
- WriteIO (SB_IOMAP_REGC14, AccWidthUint8, &dbValue);
-
- dbValue = 0x0A;
- WriteIO (SB_IOMAP_REG70, AccWidthUint8, &dbValue);
- ReadIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
- dbValue &= 0xEF;
- WriteIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
-
-
- if (getRevisionID() >= SB700_A13){
- programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbA13PorInitPciTable[0]), sizeof(sbA13PorInitPciTable)/sizeof(REG8MASK) );
- programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sbA13PorPmioInitTbl[0]), (sizeof(sbA13PorPmioInitTbl)/sizeof(REG8MASK)) );
- }
-
- if ((getRevisionID() >= SB700_A14) )
- programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbA14PorInitPciTable[0]), sizeof(sbA14PorInitPciTable)/sizeof(REG8MASK) );
-
- if ( (getRevisionID() >= SB700_A14) && ( (pConfig->TimerClockSource == 1) || (pConfig->TimerClockSource == 2) )){
- ReadPMIO(SB_PMIO_REGD4, AccWidthUint8, &dbVar1);
- if (!(dbVar1 & BIT6)){
- RWPMIO(SB_PMIO_REGD4, AccWidthUint8, 0xFF, BIT6);
- pConfig->RebootRequired=1;
- }
- }
-
- if (getRevisionID() > SB700_A11) {
- if (pConfig->PciClk5 == 1)
- RWPMIO(SB_PMIO_REG41, AccWidthUint8, ~(UINT32)BIT1, BIT1); // Enabled PCICLK5 for A12
- }
-
- dbVar0 = (pBuildOptPtr->BiosSize + 1) & 7;
- if (dbVar0 > 4) {
- dbVar0 = 0;
- }
- //KZ [061811]-It's used wrong BIOS SIZE for Coreboot. RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint8 | S3_SAVE, 0x00, 0xF8 << dbVar0);
-
- if (pConfig->Spi33Mhz)
- //spi reg0c[13:12] to 01h to run spi 33Mhz in system bios
- RWMEM((pBuildOptPtr->SpiRomBaseAddress)+SB_SPI_MMIO_REG0C,AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT13+BIT12), BIT12);
-
- //SB internal spread spectrum settings. A reboot is required if the spread spectrum settings have to be changed
- //from the existing value.
- ReadPMIO(SB_PMIO_REG42, AccWidthUint8, &dbVar0);
- if (pConfig->SpreadSpectrum != (dbVar0 >> 7) )
- pConfig->RebootRequired = 1;
- if (pConfig->SpreadSpectrum)
- RWPMIO(SB_PMIO_REG42, AccWidthUint8, ~(UINT32)BIT7, BIT7);
- else
- RWPMIO(SB_PMIO_REG42, AccWidthUint8, ~(UINT32)BIT7, 0);
-
- if ( !(pConfig->S3Resume) ){
- //To detect whether internal clock chip is used, do the following procedure
- //set PMIO_B2[7]=1, then read PMIO_B0[4]; if it is 1, we are strapped to CLKGEN mode.
- //if it is 0, we are using clock chip on board.
- RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT7);
-
- //Do the following programming only for SB700-A11.
- //1. Set PMIO_B2 [7]=1 and read B0 and B1 and save those values.
- //2. Set PMIO_B2 [7]=0
- //3. Write the saved values from step 1, back to B0 and B1.
- //4. Set PMIO_B2 [6]=1.
- ReadPMIO(SB_PMIO_REGB0, AccWidthUint16, &dwTempVar);
- if (getRevisionID() == SB700_A11){
- RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)BIT7, 00);
- WritePMIO(SB_PMIO_REGB0, AccWidthUint16, &dwTempVar);
- RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT6);
- }
-
- if (!(dwTempVar & BIT4)){
- RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)BIT0, 0); //Enable PLL2
-
- //we are in external clock chip on the board
- if (pConfig->UsbIntClock == CIMX_OPTION_ENABLED){
- //Configure usb clock to come from internal PLL
- RWPMIO(SB_PMIO_REGD2, AccWidthUint8, 0xFF, BIT3); //Enable 48Mhz clock from PLL2
- RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, BIT4); //Tell USB PHY to use internal 48Mhz clock from PLL2
- }
- else{
- //Configure usb clock to come from external clock
- RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, 0); //Tell USB PHY to use external 48Mhz clock from PLL2
- RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, 00); //Disable 48Mhz clock from PLL2
- }
- }
- else{
- //we are using internal clock chip on this board
- if (pConfig->UsbIntClock == CIMX_OPTION_ENABLED){
- //Configure usb clock to come from internal PLL
- RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, 0); //Enable 48Mhz clock from PLL2
- RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, BIT4); //Tell USB PHY to use internal 48Mhz clock from PLL2
- }
- else{
- //Configure usb clock to come from external clock
- RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, 0); //Tell USB PHY to use external 48Mhz clock from PLL2
- RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, BIT3); //Disable 48Mhz clock from PLL2
- }
- }
-
- ReadPMIO(SB_PMIO_REG43, AccWidthUint8, &dbVar0);
- RWPMIO(SB_PMIO_REG43, AccWidthUint8, ~(UINT32)(BIT6+BIT5+BIT0), (pConfig->UsbIntClock << 5));
- //Check whether our usb clock settings changed compared to previous boot, if yes then we need to reboot.
- if ( (dbVar0 & BIT0) || ( (pConfig->UsbIntClock) != ((dbVar0 & (BIT6+BIT5)) >> 5)) ) pConfig->RebootRequired = 1;
- }
-
- if (pBuildOptPtr->LegacyFree) //if LEGACY FREE system
- RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000);
- else
- RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5);
-
- if ( (getRevisionID() == SB700_A14) || (getRevisionID() == SB700_A13)){
- RWPMIO(SB_PMIO_REG65, AccWidthUint8, 0xFF, BIT7);
- RWPMIO(SB_PMIO_REG75, AccWidthUint8, 0xC0, BIT0);
- RWPMIO(SB_PMIO_REG52, AccWidthUint8, 0xC0, BIT1);
- }
-
- if (getRevisionID() >= SB700_A15) {
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40+3, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT3), 0);
- //Enable unconditional shutdown fix in A15
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG38+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT4);
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40+3, AccWidthUint8 | S3_SAVE, 0xFF, BIT3);
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG06+1, AccWidthUint8 | S3_SAVE, 0xFF, 0xD0);
- }
-
- // [Updated RPR] Set ImcHostSmArbEn(SMBUS:0xE1[5]) only when IMC is enabled
- if (isEcPresent()) {
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGE1, AccWidthUint8 | S3_SAVE, 0xFF, BIT5);
- }
-
- //According to AMD Family 15h Models 00h-0fh processor BKDG section 2.12.8 LDTSTOP requirement
- // to program VID/FID LDTSTP# duration selection register
- AMDFamily15CpuLdtStopReq();
-
-#ifndef NO_EC_SUPPORT
- ecPowerOnInit(pBuildOptPtr, pConfig);
-#endif
-}
-
-
-void setRevisionID(void){
- UINT8 dbVar0, dbVar1;
-
- ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0);
- ReadPMIO(SB_PMIO_REG53, AccWidthUint8, &dbVar1);
- if ( (dbVar0 == 0x39) && (dbVar1 & BIT6) && !(dbVar1 & BIT7)){
- RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40), AccWidthUint8, ~(UINT32)BIT0, BIT0);
- RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, 00, SB700_A12);
- RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40), AccWidthUint8, ~(UINT32)BIT0, 00);
- }
- ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0);
-}
-
-
-UINT8 getRevisionID(void){
- UINT8 dbVar0;
-
- ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0);
- return dbVar0;
-}
-
-
-void AMDFamily15CpuLdtStopReq(void) {
- CPUID_DATA CpuId;
- CPUID_DATA CpuId_Brand;
- UINT8 dbVar0, dbVar1, dbVar2;
-
- //According to AMD Family 15h Models 00h-0fh processor BKDG section 2.12.8 LDTSTOP requirement
- //to program VID/FID LDTSTP# duration selection register
- //If any of the following system configuration properties are true LDTSTP# assertion time required by the processor is 10us:
- // 1. Any link in the system operating at a Gen 1 Frequency.
- // 2. Also for server platform (G34/C32) set PM_REG8A[6:4]=100b (16us)
-
- CpuidRead (0x01, &CpuId);
- CpuidRead (0x80000001, &CpuId_Brand); //BrandID, to read socket type
- if ((CpuId.REG_EAX & 0xFFFFFF00) == 0x00600F00) {
-
- //Program to Gen 3 default value - 001b
- RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x10); //set [6:4]=001b
-
- //Any link in the system operating at a Gen 1 Frequency.
- //Check Link 0 - Link connected regsister
- ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG98), AccWidthUint8, &dbVar2);
- dbVar2 = dbVar2 & 0x01;
-
- if(dbVar2 == 0x01) {
- //Check Link 0 - Link Frequency Freq[4:0]
- ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG89), AccWidthUint8, &dbVar0);
- ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG9C), AccWidthUint8, &dbVar1);
- dbVar0 = dbVar0 & 0x0F; //Freq[3:0]
- dbVar1 = dbVar1 & 0x01; //Freq[4]
- dbVar0 = (dbVar1 << 4) | dbVar0; //Freq[4:0]
- //Value 6 or less indicate Gen1
- if(dbVar0 <= 0x6) {
- RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b
- }
- }
-
- //Check Link 1 - Link connected regsister
- ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGB8), AccWidthUint8, &dbVar2);
- dbVar2 = dbVar2 & 0x01;
- if(dbVar2 == 0x01) {
- //Check Link 1 - Link Frequency Freq[4:0]
- ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGA9), AccWidthUint8, &dbVar0);
- ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGBC), AccWidthUint8, &dbVar1);
- dbVar0 = dbVar0 & 0x0F; //Freq[3:0]
- dbVar1 = dbVar1 & 0x01; //Freq[4]
- dbVar0 = (dbVar1 << 4) | dbVar0; //Freq[4:0]
- //Value 6 or less indicate Gen1
- if(dbVar0 <= 0x6) {
- RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b
- }
- }
-
- //Check Link 2 - Link connected regsister
- ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGD8), AccWidthUint8, &dbVar2);
- dbVar2 = dbVar2 & 0x01;
- if(dbVar2 == 0x01) {
- //Check Link 2 - Link Frequency Freq[4:0]
- ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGC9), AccWidthUint8, &dbVar0);
- ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGDC), AccWidthUint8, &dbVar1);
- dbVar0 = dbVar0 & 0x0F; //Freq[3:0]
- dbVar1 = dbVar1 & 0x01; //Freq[4]
- dbVar0 = (dbVar1 << 4) | dbVar0; //Freq[4:0]
- //Value 6 or less indicate Gen1
- if(dbVar0 <= 0x6) {
- RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b
- }
- }
-
- //Check Link 3 - Link connected regsister
- ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGF8), AccWidthUint8, &dbVar2);
- dbVar2 = dbVar2 & 0x01;
- if(dbVar2 == 0x01) {
- //Check Link 3 - Link Frequency Freq[4:0]
- ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGE9), AccWidthUint8, &dbVar0);
- ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGFC), AccWidthUint8, &dbVar1);
- dbVar0 = dbVar0 & 0x0F; //Freq[3:0]
- dbVar1 = dbVar1 & 0x01; //Freq[4]
- dbVar0 = ((dbVar1 << 4) | dbVar0); //Freq[4:0]
- //Value 6 or less indicate Gen1
- if(dbVar0 <= 0x6) {
- RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b
- }
- }
-
- // Server platform (G34/C32) set PM_REG8A[6:4]=100b (16us)
- if(((CpuId_Brand.REG_EBX & 0xF0000000) == 0x30000000) || ((CpuId_Brand.REG_EBX & 0xF0000000) == 0x50000000)) {
- RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b
- }
- }
-
-}
-
diff --git a/src/vendorcode/amd/cimx/sb700/SBTYPE.h b/src/vendorcode/amd/cimx/sb700/SBTYPE.h
deleted file mode 100644
index faeae5d..0000000
--- a/src/vendorcode/amd/cimx/sb700/SBTYPE.h
+++ /dev/null
@@ -1,249 +0,0 @@
-/*;********************************************************************************
-;
-; Copyright (C) 2012 Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#ifndef _AMD_SBTYPE_H_
-#define _AMD_SBTYPE_H_
-
-#pragma pack(push,1)
-
-typedef UINT32 (*CIM_HOOK_ENTRY)(UINT32 Param1, UINTN Param2, void* pConfig);
-typedef void (*SMM_SERVICE_ROUTINE) (void);
-
-typedef struct _STDCFG{
- UINT32 pImageBase;
- UINT32 pPcieBase;
- UINT8 Func;
- CIM_HOOK_ENTRY pCallBack;
- UINT32 pB2ImageBase;
-}STDCFG; //Size of stdcfg is 17 bytes
-
-typedef struct _BUILDPARAM
-{
- UINT16 BiosSize:3; //0-1MB, 1-2MB, 2-4MB, 3-8MB, 7-512KB, all other values reserved
- UINT16 LegacyFree:1;
- UINT16 Dummy0:12;
-
- UINT16 EcKbd:1;
- UINT16 EcChannel0:1;
- UINT16 Dummy1:14;
-
- UINT32 Smbus0BaseAddress;
- UINT16 Smbus1BaseAddress;
- UINT32 SioPmeBaseAddress;
- UINT32 WatchDogTimerBase;
- UINT32 SpiRomBaseAddress;
-
- UINT16 AcpiPm1EvtBlkAddr;
- UINT16 AcpiPm1CntBlkAddr;
- UINT16 AcpiPmTmrBlkAddr;
- UINT16 CpuControlBlkAddr;
- UINT16 AcpiGpe0BlkAddr;
- UINT16 SmiCmdPortAddr;
- UINT16 AcpiPmaCntBlkAddr;
-
- UINT16 EcLdn5MailBoxAddr;
- UINT8 EcLdn5Irq;
- UINT16 EcLdn9MailBoxAddr;
- UINT32 ReservedDword0;
- UINT32 ReservedDword1;
- UINT32 ReservedDword2;
- UINT32 ReservedDword3;
-
- UINT32 HpetBase; //HPET Base address
-
- UINT32 SataIDESsid;
- UINT32 SataRAIDSsid;
- UINT32 SataRAID5Ssid;
- UINT32 SataAHCISsid;
-
- UINT32 Ohci0Ssid;
- UINT32 Ohci1Ssid;
- UINT32 Ehci0Ssid;
- UINT32 Ohci2Ssid;
- UINT32 Ohci3Ssid;
- UINT32 Ehci1Ssid;
- UINT32 Ohci4Ssid;
- UINT32 SmbusSsid;
- UINT32 IdeSsid;
- UINT32 AzaliaSsid;
- UINT32 LpcSsid;
- UINT32 P2PSsid;
-}BUILDPARAM;
-
-typedef struct _CODECENTRY{
- UINT8 Nid;
- UINT32 Byte40;
-}CODECENTRY;
-
-typedef struct _CODECTBLLIST{
- UINT32 CodecID;
- CODECENTRY* CodecTablePtr;
-}CODECTBLLIST;
-
-typedef struct _AMDSBCFG
-{
- STDCFG StdHeader; //offset 0:16 - 17 bytes
- //UINT32 MsgXchgBiosCimx; //offset 17:20 - 4 bytes
- UINT32 S3Resume:1;
- UINT32 RebootRequired:1;
- UINT32 Spi33Mhz:1;
- UINT32 SpreadSpectrum:1;
- UINT32 UsbIntClock:1; //0:Use external clock, 1:Use internal clock
- UINT32 PciClk5:1; //0:disable, 1:enable
- UINT32 TimerClockSource:2; //0:100Mhz PCIE Reference clock (same as SB700-A12,
- //1: 14Mhz using 25M_48M_66M_OSC pin, 2: Auto (100Mhz for SB700-A12, 14Mhz
- //using 25M_48m_66m_0SC pin for SB700-A14, SB710, SP5100
- UINT32 ResetCpuOnSyncFlood:1; //0:Reset CPU on Sync Flood, 1:Do not reset CPU on sync flood
- UINT32 MsgXchgBiosCimxDummyBB:23;
-
- /** BuildParameters - The STATIC platform information for CIMx Module. */
- BUILDPARAM BuildParameters;
-
- //SATA Configuration
- UINT32 SataController :1; //0, 0:disable 1:enable* //offset 25:28 - 4 bytes
- UINT32 SataClass :3; //1, 0:IDE* 1:RAID 2:AHCI 3:Legacy IDE 4:IDE->AHCI 5:AMD_AHCI, 6:IDE->AMD_AHCI
- UINT32 SataSmbus :1; //4, 0:disable 1:enable*
- UINT32 SataAggrLinkPmCap:1; //5, 0:OFF 1:ON
- UINT32 SataPortMultCap :1; //6, 0:OFF 1:ON
- UINT32 SataReserved :2; //8:7, Reserved
- UINT32 SataClkAutoOff :1; //9, AutoClockOff for IDE modes 0:Disabled, 1:Enabled
- UINT32 SataIdeCombinedMode :1; //10, SataIDECombinedMode 0:Disabled, 1:Enabled
- UINT32 SataIdeCombMdPriSecOpt:1; //11, Combined Mode, SATA as primary or secondary 0:primary 1:secondary
- UINT32 SataReserved1 :6; //17:12, Not used currently
- UINT32 SataEspPort :6; //23:18 SATA port is external accessiable on a signal only connector (eSATA:)
- UINT32 SataClkAutoOffAhciMode:1; //24: Sata Auto clock off for AHCI mode
- UINT32 SataHpcpButNonESP:6; //25:30 Hotplug capable but not e-sata port
- UINT32 SataHideUnusedPort:1; //31, 0:Disabled 1:Enabled
-
- //Flash Configuration //offset 29:30 - 2 bytes
- UINT16 FlashController :1; //0, 0:disable FC & enable IDE 1:enable FC & disable IDE
- UINT16 FlashControllerMode:1; //1, 0:Flash behind SATA 1:Flash as standalone
- UINT16 FlashHcCrc:1; //2,
- UINT16 FlashErrorMode:1; //3
- UINT16 FlashNumOfBankMode:1; //4
- UINT16 FlashDummy:11; //5:15
-
- //USB Configuration //offset 31:32 - 2 bytes
- UINT16 Usb1Ohci0 :1; //0, 0:disable 1:enable* Bus 0 Dev 18 Func0
- UINT16 Usb1Ohci1 :1; //1, 0:disable 1:enable* Bus 0 Dev 18 Func1
- UINT16 Usb1Ehci :1; //2, 0:disable 1:enable* Bus 0 Dev 18 Func2
- UINT16 Usb2Ohci0 :1; //3, 0:disable 1:enable* Bus 0 Dev 19 Func0
- UINT16 Usb2Ohci1 :1; //4, 0:disable 1:enable* Bus 0 Dev 19 Func1
- UINT16 Usb2Ehci :1; //5, 0:disable 1:enable* Bus 0 Dev 19 Func2
- UINT16 Usb3Ohci :1; //6, 0:disable 1:enable* Bus 0 Dev 20 Func5
- UINT16 UsbOhciLegacyEmulation:1; //7, 0:Enabled, 1:Disabled
- UINT16 UsbDummy :8; //8:15
-
- //Azalia Configuration //offset 33:36 - 4 bytes
- UINT32 AzaliaController:2; //0, 0:AUTO, 1:disable, 2:enable
- UINT32 AzaliaPinCfg :1; //2, 0:disable, 1:enable
- UINT32 AzaliaFrontPanel:2; //3, 0:AUTO, 1:disable, 2:enable
- UINT32 FrontPanelDetected:1; //5, 0:Not detected, 1:detected
- UINT32 AzaliaSdin0 :2; //6
- UINT32 AzaliaSdin1 :2; //8
- UINT32 AzaliaSdin2 :2; //10
- UINT32 AzaliaSdin3 :2; //12
- UINT32 AzaliaDummy :18; //14:31
-
- CODECTBLLIST* pAzaliaOemCodecTablePtr; //offset 37:40 - 4 bytes
- UINT32 pAzaliaOemFpCodecTableptr; //offset 41:44 - 4 bytes
-
- //Miscellaneous Configuration //offset 45:48 - 4 bytes
- UINT32 MiscReserved0:1; //0
- UINT32 HpetTimer:1; //1, 0:disable 1:enable
- UINT32 PciClks:5; //2:6, 0:disable, 1:enable
- UINT32 MiscReserved1:3; //9:7, Reserved
- UINT32 IdeController:1; //10, 0:Enable, 1:Disabled
- UINT32 MobilePowerSavings:1; //11, 0:Disable, 1:Enable Power saving features especially for Mobile platform
- UINT32 ExternalRTCClock:1; //12, 0:Don't Shut Off, 1:Shut Off, external RTC clock
- UINT32 AcpiS1Supported:1; //13, 0:S1 not supported, 1:S1 supported
- UINT32 AnyHT200MhzLink:1; //14, 0:No HT 200Mhz Link in platform, 1; There is 200MHz HT Link in platform
- UINT32 WatchDogTimerEnable:1; //15, [0]: WDT disabled; 1: WDT enabled
- UINT32 MTC1e:1; //16, Message Triggered C1e - 0:Disabled*, 1:Enabled
- UINT32 HpetMsiDis:1; //17, HPET MSI - 0:Enable HPET MSI, 1:Disable
- UINT32 EhciDataCacheDis:1; //18, 0:Date Cache Enabled, 1:Date Cache Disabled /** EHCI Async Data Cache Disable */
- UINT32 MiscDummy:13;
-
- UINT32 AsmAslInfoExchange0; //offset 49:52 - 4 bytes
- UINT32 AsmAslInfoExchange1; //offset 53:56
-
- //DebugOptions_1 //offset 57:60
- UINT32 FlashPinConfig :1; //0, 0:desktop mode 1:mobile mode
- UINT32 UsbPhyPowerDown :1; //1
- UINT32 PcibClkStopOverride :10; //11:2
- UINT32 Debug1Reserved0:4; //15:11
- UINT32 AzaliaSnoop:1; //16 0:Disable, 1:Enable
- UINT32 SataSscPscCap:1; //17, 0:Enable SSC/PSC capability, 1:Disable SSC/PSC capability
- UINT32 SataPortMode:6; //23:18, 0: AUTO, 1:Force SATA port(6/5/4/3/2/1) to GEN1
- UINT32 SataPhyWorkaround:2; //25:24, 0:AUTO, 1:Enable, 2:Disable
- UINT32 Gen1DeviceShutdownDuringPhyWrknd:2; //27:26, 0:AUTO, 1:YES, 2:NO
- UINT32 OhciIsoOutPrefetchDis:1; //28, 0:Enable OHCI ISO OUT prefetch, 1:Disable
- UINT32 Debug1Dummy:3; //
-
- //DebugOptions_2
- UINT32 PcibAutoClkCtrlLow:16;
- UINT32 PcibAutoClkCtrlHigh:16;
-
- //TempMMIO
- UINT32 TempMMIO:32;
-
-}AMDSBCFG;
-
-typedef struct _SMMSERVICESTRUC
-{
- UINT8 enableRegNum;
- UINT8 enableBit;
- UINT8 statusRegNum;
- UINT8 statusBit;
- CHAR8 *debugMessage;
- SMM_SERVICE_ROUTINE serviceRoutine;
-}SMMSERVICESTRUC;
-
-typedef struct _ABTblEntry
-{
- UINT8 regType;
- UINT32 regIndex;
- UINT32 regMask;
- UINT32 regData;
-}ABTBLENTRY;
-
-#define PCI_ADDRESS(bus,dev,func,reg) \
-(UINT32) ( (((UINT32)bus) << 24) + (((UINT32)dev) << 19) + (((UINT32)func) << 16) + ((UINT32)reg) )
-
-typedef UINT32 CIM_STATUS;
-#define CIM_SUCCESS 0x00000000
-#define CIM_ERROR 0x80000000
-#define CIM_UNSUPPORTED 0x80000001
-
-#pragma pack(pop)
-
-#define CIMX_OPTION_DISABLED 0
-#define CIMX_OPTION_ENABLED 1
-
-#endif // _AMD_SBTYPE_H_
diff --git a/src/vendorcode/amd/cimx/sb700/SMM.c b/src/vendorcode/amd/cimx/sb700/SMM.c
deleted file mode 100644
index 0d752fb..0000000
--- a/src/vendorcode/amd/cimx/sb700/SMM.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*****************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *
- ***************************************************************************/
-
-
-#include "Platform.h"
-
-SMMSERVICESTRUC smmItemsTable[]={
- {SB_PMIO_REG0E, BIT2, SB_PMIO_REG0F, BIT2, (CHAR8 *)"Software SMI through SMI CMD port \n ", softwareSMIservice},
- {SB_PMIO_REG00, BIT4, SB_PMIO_REG01, BIT4, (CHAR8 *)"Software initiated SMI \n ", NULL},
- {SB_PMIO_REG02, 0xFF, SB_PMIO_REG05, 0xFF, (CHAR8 *)"SMI on IRQ15-8 \n ", NULL},
- {SB_PMIO_REG03, 0xFF, SB_PMIO_REG06, 0xFF, (CHAR8 *)"SMI on IRQ7-0 \n ", NULL},
- {SB_PMIO_REG04, 0xFF, SB_PMIO_REG07, 0xFF, (CHAR8 *)"SMI on legacy devices activity(Serial, FDD etc) \n ", NULL},
- {SB_PMIO_REG1C, 0xFF, SB_PMIO_REG1D, 0xFF, (CHAR8 *)"SMI on PIO 0123 \n ", NULL},
- {SB_PMIO_REGA8, 0x0F, SB_PMIO_REGA9, 0xFF, (CHAR8 *)"SMI on PIO 4567 \n ", NULL},
-};
-
-
-/*++
-
-Routine Description:
-
- SB SMI service
-
-Arguments:
-
- pConfig - SBconfiguration
-
-Returns:
-
- void
-
---*/
-
-void sbSmmService(AMDSBCFG* pConfig){
- UINT8 i, dbEnableValue, dbStatusValue;
- SMMSERVICESTRUC *pSmmItems;
- SMM_SERVICE_ROUTINE serviceRoutine;
-
- pSmmItems = (SMMSERVICESTRUC *)FIXUP_PTR(&smmItemsTable[0]);
- TRACE((DMSG_SB_TRACE, "CIMx - Entering SMM services \n"));
- for (i = 1; i <= (sizeof(smmItemsTable)/sizeof(SMMSERVICESTRUC)); i++){
- dbEnableValue = pSmmItems->enableRegNum;
- ReadPMIO(pSmmItems->enableRegNum, AccWidthUint8, &dbEnableValue);
- ReadPMIO(pSmmItems->statusRegNum, AccWidthUint8, &dbStatusValue);
- if ( (dbEnableValue & (pSmmItems->enableBit)) && (dbStatusValue & (pSmmItems->statusBit)) ){
- TRACE((DMSG_SB_TRACE, "\n \nSmi source is: %s \n", pSmmItems->debugMessage));
- TRACE((DMSG_SB_TRACE, "Enable Reg:%d Value:%d\n", pSmmItems->enableRegNum, dbEnableValue));
- TRACE((DMSG_SB_TRACE, "Status Reg:%d Value:%d\n\n", pSmmItems->statusRegNum, dbStatusValue));
- if ( (pSmmItems->serviceRoutine)!= NULL){
- serviceRoutine = (void *)FIXUP_PTR(pSmmItems->serviceRoutine);
- serviceRoutine();
- }
- }
- }
- TRACE((DMSG_SB_TRACE, "CIMx - Exiting SMM services \n"));
-}
-
-
-void softwareSMIservice(void){
- UINT16 dwSmiCmdPort, dwVar;
- ReadPMIO(SB_PMIO_REG2A, AccWidthUint16, &dwSmiCmdPort);
- ReadIO(dwSmiCmdPort, AccWidthUint16, &dwVar);
- TRACE((DMSG_SB_TRACE, "SMI CMD Port Address: %X SMICMD Port value is %X \n", dwSmiCmdPort, dwVar));
-}
diff --git a/src/vendorcode/amd/cimx/sb700/Sata.c b/src/vendorcode/amd/cimx/sb700/Sata.c
new file mode 100644
index 0000000..d503239
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/Sata.c
@@ -0,0 +1,453 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+//Table for class code of SATA Controller in different modes
+UINT32 sataIfCodeTable[] = {
+ 0x01018f00, //sata class ID of IDE
+ 0x01040000, //sata class ID of RAID
+ 0x01060100, //sata class ID of AHCI
+ 0x01018a00, //sata class ID of Legacy IDE
+ 0x01018f00, //sata class ID of IDE to AHCI mode
+ 0x01060100, //sata class ID of AMD-AHCI mode
+ 0x01018f00 //sata class ID of IDE to AMD-AHCI mode
+};
+
+//Table for device id of SATA Controller in different modes
+UINT16 sataDeviceIDTable[] = {
+ 0x4390, //sata device ID of IDE
+ 0x4392, //sata device ID of RAID
+ 0x4391, //sata class ID of AHCI
+ 0x4390, //sata device ID of Legacy IDE
+ 0x4390, //sata device ID of IDE->AHCI mode
+ 0x4394, //sata device ID for AMD-AHCI mode
+ 0x4390 //sata device ID of IDE->AMDAHCI mode
+};
+
+
+void sataInitBeforePciEnum(AMDSBCFG* pConfig){
+ UINT32 ddValue, *tempptr;
+ UINT16 *pDeviceIdptr, dwDeviceId;
+ UINT8 dbValue, dbOrMask, dbAndMask;
+
+
+ dbAndMask=0;
+ dbOrMask=0;
+ // Enable/Disable Combined mode & do primary/secondary selections, enable/disable
+ if (pConfig->SataIdeCombinedMode == CIMX_OPTION_DISABLED) dbAndMask= BIT3; //Clear BIT3
+ if (pConfig->SataIdeCombMdPriSecOpt == 1) dbOrMask = BIT4; //Set BIT4
+ if (pConfig->SataSmbus == 0) dbOrMask = BIT1;
+
+ RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAD), AccWidthUint8 | S3_SAVE, ~(dbAndMask), dbOrMask);
+
+ if (pConfig->SataController == 0){
+ // SATA Controller Disabled & set Power Saving mode to disabled
+ RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAD), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, BIT1);
+ return;
+ }
+
+ restrictSataCapabilities(pConfig);
+
+ // Get the appropriate class code from the table and write it to PCI register 08h-0Bh
+ // Set the appropriate SATA class based on the input parameters
+ dbValue=pConfig->SataClass;
+ tempptr= (UINT32 *) FIXUP_PTR (&sataIfCodeTable[0]);
+ ddValue=tempptr[dbValue];
+
+ // BIT0: Enable write access to PCI header (reg 08h-0Bh) by setting SATA PCI register 40h, bit 0
+ // BIT4:disable fast boot
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT4+BIT0);
+
+ // Write the class code to SATA PCI register 08h-0Bh
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, ddValue);
+
+ if (pConfig->SataClass == LEGACY_IDE_MODE) //SATA = Legacy IDE
+ //Set PATA controller to native mode
+ RWPCI(((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F);
+
+ //Change the appropriate device id
+ if (pConfig->SataClass == AMD_AHCI_MODE) {
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 3), AccWidthUint8 | S3_SAVE, 0xff, BIT0);
+ }
+ pDeviceIdptr= (UINT16 *) FIXUP_PTR (&sataDeviceIDTable[0]);
+
+ ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, &dwDeviceId);
+ if ( !((dwDeviceId==SB750_SATA_DEFAULT_DEVICE_ID) && (pConfig->SataClass == RAID_MODE)) ){
+ //if not (SB750 & RAID mode), then program the device id
+ dwDeviceId=pDeviceIdptr[dbValue];
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, dwDeviceId);
+ }
+
+ if (pConfig->AcpiS1Supported)
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG34), AccWidthUint8 | S3_SAVE, 00, 0x70);//Disable SATA PM & MSI capability
+ else
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG60+1), AccWidthUint8 | S3_SAVE, 00, 0x70);//Disable SATA MSI capability
+
+ if (getRevisionID() >= SB700_A13){
+ //Enable test/enhancement mode for A13
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40+3), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT5, 00);
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG48), AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT24+BIT21), 0xBF80);
+ }
+
+ if (getRevisionID() >= SB700_A14){
+ //Fix for TT SB01352 - LED Stays On When ODD Attached To Slave Port In IDE Mode
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG48), AccWidthUint8 | S3_SAVE, 0xFF, BIT6);
+ }
+
+ // Disable write access to PCI header
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0);
+
+ // RPR 6.5 SATA PHY Programming Sequence
+ RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG86, AccWidthUint16 | S3_SAVE, 0x00, 0x2C00);
+ RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG88, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016);
+ RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG8C, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016);
+ RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG90, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016);
+ RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG94, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016);
+ RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG98, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016);
+ RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG9C, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016);
+ RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REGA0, AccWidthUint32 | S3_SAVE, 0x00, 0xA07AA07A);
+ RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REGA4, AccWidthUint32 | S3_SAVE, 0x00, 0xA07AA07A);
+ RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REGA8, AccWidthUint32 | S3_SAVE, 0x00, 0xA07AA07A);
+
+ CallBackToOEM(SATA_PHY_PROGRAMMING, NULL, pConfig);
+}
+
+void sataInitAfterPciEnum(AMDSBCFG* pConfig){
+ UINT32 ddAndMask=0, ddOrMask=0, ddBar5=0;
+ UINT8 dbVar, dbPortNum;
+
+ if (pConfig->SataController == 0) return; //return if SATA controller is disabled.
+
+ //Enable write access to pci header, pm capabilities
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
+
+ //Disable AHCI enhancement function (RPR 7.2)
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8 | S3_SAVE, 0xFF, BIT7);
+
+ restrictSataCapabilities(pConfig);
+
+ ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5);
+
+ if ( (ddBar5 == 0) || (ddBar5 == -1) ) {
+ //assign temporary BAR5
+ if ( (pConfig->TempMMIO == 0) || (pConfig->TempMMIO == -1))
+ ddBar5 = 0xFEC01000;
+ else
+ ddBar5=pConfig->TempMMIO;
+
+ WritePCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5);
+ }
+
+ ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
+ RWPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8,0xFF, 0x03); //memory and io access enable
+
+ ddBar5 &= 0xFFFFFC00; //Clear Bits 9:0
+ if (!pConfig->SataPortMultCap)
+ ddAndMask |= BIT12;
+ if (!pConfig->SataAggrLinkPmCap)
+ ddAndMask |= BIT11;
+ if (pConfig->SataSscPscCap)
+ ddOrMask |= BIT1;
+
+ RWMEM((ddBar5 + SB_SATA_BAR5_REGFC),AccWidthUint32 | S3_SAVE, ~ddAndMask, ddOrMask);
+
+
+ //Clear HPCP and ESP by default
+ RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, 0xFFFC0FC0, 0);
+
+ if (pConfig->SataHpcpButNonESP !=0) {
+ RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, 0xFFFFFFC0, pConfig->SataHpcpButNonESP);
+ }
+
+ // SATA ESP port setting
+ // These config bits are set for SATA driver to identify which ports are external SATA ports and need to
+ // support hotplug. If a port is set as an external SATA port and need to support hotplug, then driver will
+ // not enable power management(HIPM & DIPM) for these ports.
+ if (pConfig->SataEspPort !=0) {
+ RWMEM((ddBar5 + SB_SATA_BAR5_REGFC),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT20);
+ RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, ~(pConfig->SataEspPort), 0);
+ RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT17+BIT16+BIT15+BIT14+BIT13+BIT12),(pConfig->SataEspPort << 12));
+ }
+
+ if ( ((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE) )
+ RWPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50+2), AccWidthUint8, ~(UINT32)(BIT3+BIT2+BIT1), BIT2+BIT1); //set MSI to 8 messages
+
+ if ( ((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE) && ((pConfig->SataIdeCombinedMode) == CIMX_OPTION_DISABLED) ){
+ RWMEM((ddBar5 + SB_SATA_BAR5_REG00),AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT2+BIT1+BIT0), BIT2+BIT0);
+ RWMEM((ddBar5 + SB_SATA_BAR5_REG0C),AccWidthUint8 | S3_SAVE, 0xC0, 0x3F);
+ }
+
+ for (dbPortNum=0;dbPortNum<=5;dbPortNum++){
+ if (pConfig->SataPortMode & (1 << dbPortNum)){
+ //downgrade to GEN1
+ RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0x0F, 0x10);
+ RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFF, 0x01);
+ Stall(1000);
+ RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00);
+ }
+ }
+
+ //If this is not S3 resume and also if SATA set to one of IDE mode, then implement drive detection workaround.
+ if ( !(pConfig->S3Resume) && ( ((pConfig->SataClass) != AHCI_MODE) && ((pConfig->SataClass) != RAID_MODE) && ((pConfig->SataClass) != AMD_AHCI_MODE) ) )
+ sataDriveDetection(pConfig, ddBar5);
+
+ if ( (pConfig->SataPhyWorkaround==1) || ( (pConfig->SataPhyWorkaround==0) && (getRevisionID() < SB700_A13)) )
+ sataPhyWorkaround(pConfig, ddBar5);
+
+ // Set the handshake bit for IDE driver to detect the disabled IDE channel correctly.
+ // Set IDE PCI Config 0x63 [3] if primary channel disabled, [4] if secondary channel disabled.
+ if (pConfig->SataIdeCombinedMode == CIMX_OPTION_DISABLED)
+ RWPCI( ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG63), AccWidthUint8 , 0xF9, (0x02 << (pConfig->SataIdeCombMdPriSecOpt)) );
+
+ WritePCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
+
+ //Disable write access to pci header, pm capabilities
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0);
+}
+
+
+void sataDriveDetection(AMDSBCFG* pConfig, UINT32 ddBar5){
+ UINT32 ddVar0;
+ UINT8 dbPortNum, dbVar0;
+ UINT32 dwIoBase, dwVar0;
+
+ TRACE((DMSG_SB_TRACE, "CIMx - Entering sata drive detection procedure\n\n"));
+ TRACE((DMSG_SB_TRACE, "SATA BAR5 is %X \n", ddBar5));
+
+ if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE) ){
+ for (dbPortNum=0;dbPortNum<4;dbPortNum++){
+ ReadMEM(ddBar5+ SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint32, &ddVar0);
+ if ( ( ddVar0 & 0x0F ) == 0x03){
+ if ( dbPortNum & BIT0)
+ //this port belongs to secondary channel
+ ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG18), AccWidthUint16, &dwIoBase);
+ else
+ //this port belongs to primary channel
+ ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG10), AccWidthUint16, &dwIoBase);
+
+ //if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them
+ if (pConfig->SataClass == LEGACY_IDE_MODE)
+ dwIoBase = ( (0x170) | ( (~((dbPortNum & BIT0) << 7)) & 0x80 ) );
+
+ if ( dbPortNum & BIT1)
+ //this port is slave
+ dbVar0=0xB0;
+ else
+ //this port is master
+ dbVar0=0xA0;
+ dwIoBase &= 0xFFF8;
+ WriteIO(dwIoBase+6, AccWidthUint8, &dbVar0);
+
+ //Wait in loop for 30s for the drive to become ready
+ for (dwVar0=0;dwVar0<3000;dwVar0++){
+ ReadIO(dwIoBase+7, AccWidthUint8, &dbVar0);
+ if ( (dbVar0 & 0x88) == 0)
+ break;
+ Stall(10000);
+ }
+ } //end of if ( ( ddVar0 & 0x0F ) == 0x03)
+ } //for (dbPortNum=0;dbPortNum<4;dbPortNum++)
+ } //if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE) )
+}
+
+
+//This patch is to workaround the SATA PHY logic hardware issue in the SB700.
+//Internally this workaround is called as 7NewA
+void sataPhyWorkaround(AMDSBCFG* pConfig, UINT32 ddBar5){
+
+ UINT8 dbPortNum, dbVar0;
+
+ if (pConfig->Gen1DeviceShutdownDuringPhyWrknd == 0x01){
+ for (dbPortNum=0;dbPortNum<=5;dbPortNum++){
+ ReadMEM(ddBar5+ SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint8, &dbVar0);
+ if ( (dbVar0 & 0xF0) == 0x10){
+ RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40+2, AccWidthUint8 | S3_SAVE, 0xFF, (01 << dbPortNum));
+ }
+
+ }
+ }
+
+ RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)(BIT4+BIT3), BIT4+BIT3);//set PMIO_D0[4:3] = 11b // this is to tell SATA PHY to use the internal 100MHz clock
+ RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG86, AccWidthUint8 | S3_SAVE, 0x00, 0x40);// set SATA PCI_CFG 0x86[7:0] = 0x40 //after the reset is done, perform this to turn on the diff clock path into SATA PHY
+ Stall(2000);// Wait for 2ms
+ RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)(BIT4+BIT3), 00);//13. set PMIO_D0[4:3] = 00b
+ Stall(20000);// Wait 20ms
+ forceOOB(ddBar5);// Force OOB
+
+ RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40+2, AccWidthUint8 | S3_SAVE, ~(0x03F), 00);
+}
+
+
+void forceOOB(UINT32 ddBar5){
+ UINT8 dbPortNum;
+ for (dbPortNum=0;dbPortNum<=5;dbPortNum++)
+ RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFF, 0x01);
+ Stall(2000);
+ for (dbPortNum=0;dbPortNum<=5;dbPortNum++)
+ RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00);
+ Stall(2000);// Wait for 2ms
+}
+
+/*++
+
+Routine Description:
+
+ SATA Late Configuration
+
+ if the mode is selected as IDE->AHCI
+ { 1. Set class ID to AHCI
+ 2. Enable AHCI interrupt
+ }
+
+Arguments:
+
+ pConfig - SBconfiguration
+
+Returns:
+
+ void
+
+--*/
+void sataInitLatePost(AMDSBCFG* pConfig){
+ UINT32 ddBar5;
+ UINT8 dbVar;
+
+ //Return immediately is sata controller is not enabled
+ if (pConfig->SataController == 0) return;
+
+ restrictSataCapabilities(pConfig);
+
+ //Get BAR5 value
+ ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5);
+
+ //Assign temporary BAR if is not already assigned
+ if ( (ddBar5 == 0) || (ddBar5 == -1) ){
+ //assign temporary BAR5
+ if ( (pConfig->TempMMIO == 0) || (pConfig->TempMMIO == -1))
+ ddBar5 = 0xFEC01000;
+ else
+ ddBar5=pConfig->TempMMIO;
+ WritePCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5);
+ }
+
+ ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
+ //Enable memory and io access
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, 0xFF, 0x03);
+ //Enable write access to pci header, pm capabilities
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0);
+
+ shutdownUnconnectedSataPortClock(pConfig, ddBar5);
+
+ if ( (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE)){
+ //program the AHCI class code
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, 0x01060100);
+ //Set interrupt enable bit
+ RWMEM((ddBar5 + 0x04),AccWidthUint8,~(UINT32)0,BIT1);
+ //program the correct device id for AHCI mode
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, 0x4391);
+
+ if (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE)
+ //program the correct device id for AMD-AHCI mode
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 3), AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
+ }
+
+ //Disable write access to pci header and pm capabilities
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0);
+ //Clear error status
+ RWMEM((ddBar5 + SB_SATA_BAR5_REG130),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
+ RWMEM((ddBar5 + SB_SATA_BAR5_REG1B0),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
+ RWMEM((ddBar5 + SB_SATA_BAR5_REG230),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
+ RWMEM((ddBar5 + SB_SATA_BAR5_REG2B0),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
+ //Restore memory and io access bits
+ WritePCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar );
+}
+
+
+void shutdownUnconnectedSataPortClock(AMDSBCFG* pConfig, UINT32 ddBar5){
+ UINT8 dbPortNum, dbPortSataStatus, NumOfPorts=0;
+ UINT8 UnusedPortBitMap;
+ UINT8 SataType;
+ UINT8 ClockOffEnabled ;
+
+ UnusedPortBitMap = 0;
+
+ // First scan for all unused SATA ports
+ for (dbPortNum = 5; dbPortNum <= 5; dbPortNum--) {
+ ReadMEM (ddBar5 + SB_SATA_BAR5_REG128 + (dbPortNum * 0x80), AccWidthUint8, &dbPortSataStatus);
+ if ((!(dbPortSataStatus & 0x01)) && (!((pConfig->SataEspPort) & (1 << dbPortNum)))) {
+ UnusedPortBitMap |= (1 << dbPortNum);
+ }
+ }
+
+ // Decide if we need to shutdown the clock for all unused ports
+ SataType = pConfig->SataClass;
+ ClockOffEnabled = (pConfig->SataClkAutoOff && ((SataType == NATIVE_IDE_MODE) || (SataType == LEGACY_IDE_MODE) || \
+ (SataType == IDE_TO_AHCI_MODE) || (SataType == IDE_TO_AMD_AHCI_MODE))) || \
+ (pConfig->SataClkAutoOffAhciMode && ((SataType == AHCI_MODE) || (SataType == AMD_AHCI_MODE)));
+
+ if (ClockOffEnabled) {
+ //Shutdown the clock for the port and do the necessary port reporting changes.
+ TRACE((DMSG_SB_TRACE, "Shutting down clock for SATA ports %X \n", UnusedPortBitMap));
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, UnusedPortBitMap);
+ RWMEM(ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, ~UnusedPortBitMap, 00);
+ }
+
+ // If all ports are in disabled state, report at least one
+ ReadMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, &dbPortSataStatus);
+ if ( (dbPortSataStatus & 0x3F) == 0) {
+ dbPortSataStatus = 1;
+ RWMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, ~(0x3F), dbPortSataStatus);
+ }
+
+ // Decide if we need to hide unused ports from being seen by OS (this saves OS startup time)
+ if (pConfig->SataHideUnusedPort && ClockOffEnabled) {
+ dbPortSataStatus &= ~UnusedPortBitMap; // Mask off unused ports
+ for (dbPortNum = 0; dbPortNum <= 6; dbPortNum++) {
+ if (dbPortSataStatus & (1 << dbPortNum))
+ NumOfPorts++;
+ }
+ if (NumOfPorts == 0 ) {
+ NumOfPorts = 0x01;
+ }
+ RWMEM (ddBar5 + SB_SATA_BAR5_REG00, AccWidthUint8, 0xE0, NumOfPorts - 1);
+ }
+}
+
+
+void restrictSataCapabilities(AMDSBCFG* pConfig){
+ //Restrict capabilities
+ if ( ((getSbCapability(Sb_Raid0_1_Capability)== 0x02) && (pConfig->SataClass == RAID_MODE)) || \
+ ((getSbCapability(Sb_Raid5_Capability)== 0x02) && (pConfig->SataClass == RAID_MODE)) || \
+ ((getSbCapability(Sb_Ahci_Capability)== 0x02) && ((pConfig->SataClass == AHCI_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE)))){
+ pConfig->SataClass = NATIVE_IDE_MODE;
+ }
+}
diff --git a/src/vendorcode/amd/cimx/sb700/SbAmdLib.h b/src/vendorcode/amd/cimx/sb700/SbAmdLib.h
new file mode 100644
index 0000000..e8f6b38
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/SbAmdLib.h
@@ -0,0 +1,196 @@
+/*;********************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; * Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; * Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; * Neither the name of Advanced Micro Devices, Inc. nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*********************************************************************************/
+
+#ifndef _AMD_AMDLIB_H_
+#define _AMD_AMDLIB_H_
+
+typedef CHAR8 *va_list;
+#ifndef _INTSIZEOF
+ #define _INTSIZEOF(n)( (sizeof(n) + sizeof(UINTN) - 1) & ~(sizeof(UINTN) - 1) )
+#endif
+
+// Also support coding convention rules for var arg macros
+#ifndef va_start
+#define va_start(ap,v) ( ap = (va_list)&(v) + _INTSIZEOF(v) )
+#endif
+#define va_arg(ap,t) ( *(t *)((ap += _INTSIZEOF(t)) - _INTSIZEOF(t)) )
+#define va_end(ap) ( ap = (va_list)0 )
+
+#ifndef CIMx_DEBUG
+ #define CIMx_DEBUG 0
+#endif
+
+
+#pragma pack(push,1)
+
+#define IMAGE_ALIGN 32*1024
+#define NUM_IMAGE_LOCATION 32
+
+//Entry Point Call
+typedef void (*CIM_IMAGE_ENTRY)(void* pConfig);
+
+//Hook Call
+
+typedef struct _Reg8Mask
+{
+ UINT8 bRegIndex;
+ UINT8 bANDMask;
+ UINT8 bORMask;
+}REG8MASK;
+
+
+typedef struct _CIMFILEHEADER{
+ UINT32 AtiLogo;
+ UINT32 EntryPoint;
+ UINT32 ModuleLogo;
+ UINT32 ImageSize;
+ UINT16 Version;
+ UINT8 CheckSum;
+ UINT8 Reserved1;
+ UINT32 Reserved2;
+}CIMFILEHEADER;
+
+typedef struct _CPUID_DATA{
+ UINT32 REG_EAX;
+ UINT32 REG_EBX;
+ UINT32 REG_ECX;
+ UINT32 REG_EDX;
+}CPUID_DATA;
+
+#ifndef BIT0
+ #define BIT0 (1 << 0)
+#endif
+#ifndef BIT1
+ #define BIT1 (1 << 1)
+#endif
+#ifndef BIT2
+ #define BIT2 (1 << 2)
+#endif
+#ifndef BIT3
+ #define BIT3 (1 << 3)
+#endif
+#ifndef BIT4
+ #define BIT4 (1 << 4)
+#endif
+#ifndef BIT5
+ #define BIT5 (1 << 5)
+#endif
+#ifndef BIT6
+ #define BIT6 (1 << 6)
+#endif
+#ifndef BIT7
+ #define BIT7 (1 << 7)
+#endif
+#ifndef BIT8
+ #define BIT8 (1 << 8)
+#endif
+#ifndef BIT9
+ #define BIT9 (1 << 9)
+#endif
+#ifndef BIT10
+ #define BIT10 (1 << 10)
+#endif
+#ifndef BIT11
+ #define BIT11 (1 << 11)
+#endif
+#ifndef BIT12
+ #define BIT12 (1 << 12)
+#endif
+#ifndef BIT13
+ #define BIT13 (1 << 13)
+#endif
+#ifndef BIT14
+ #define BIT14 (1 << 14)
+#endif
+#ifndef BIT15
+ #define BIT15 (1 << 15)
+#endif
+#ifndef BIT16
+ #define BIT16 (1 << 16)
+#endif
+#ifndef BIT17
+ #define BIT17 (1 << 17)
+#endif
+#ifndef BIT18
+ #define BIT18 (1 << 18)
+#endif
+#ifndef BIT19
+ #define BIT19 (1 << 19)
+#endif
+#ifndef BIT20
+ #define BIT20 (1 << 20)
+#endif
+#ifndef BIT21
+ #define BIT21 (1 << 21)
+#endif
+#ifndef BIT22
+ #define BIT22 (1 << 22)
+#endif
+#ifndef BIT23
+ #define BIT23 (1 << 23)
+#endif
+#ifndef BIT24
+ #define BIT24 (1 << 24)
+#endif
+#ifndef BIT25
+ #define BIT25 (1 << 25)
+#endif
+#ifndef BIT26
+ #define BIT26 (1 << 26)
+#endif
+#ifndef BIT27
+ #define BIT27 (1 << 27)
+#endif
+#ifndef BIT28
+ #define BIT28 (1 << 28)
+#endif
+#ifndef BIT29
+ #define BIT29 (1 << 29)
+#endif
+#ifndef BIT30
+ #define BIT30 (1 << 30)
+#endif
+#ifndef BIT31
+ #define BIT31 (1 << 31)
+#endif
+
+#define PCI_ADDRESS(bus,dev,func,reg) \
+(UINT32) ( (((UINT32)bus) << 24) + (((UINT32)dev) << 19) + (((UINT32)func) << 16) + ((UINT32)reg) )
+
+#pragma pack(pop)
+
+typedef enum {
+ AccWidthUint8 = 0,
+ AccWidthUint16,
+ AccWidthUint32,
+} ACC_WIDTH;
+
+#define S3_SAVE 0x80
+
+#endif //#ifndef _AMD_AMDLIB_H_
diff --git a/src/vendorcode/amd/cimx/sb700/SbCmn.c b/src/vendorcode/amd/cimx/sb700/SbCmn.c
new file mode 100644
index 0000000..7d5b4f4
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/SbCmn.c
@@ -0,0 +1,572 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+
+REG8MASK sbEarlyPostByteInitTable[]={
+ // SMBUS Device(Bus 0, Dev 20, Func 0)
+ {0x00, SMBUS_BUS_DEV_FUN, 0},
+ {SB_SMBUS_REG43, ~(UINT8)BIT3, 0x00}, //Make BAR registers of smbus visible.
+ {SB_SMBUS_REG24, 0X00, (CIMx_Version & 0xFF)}, //Program the version information
+ {SB_SMBUS_REG24+1, 0x00, (CIMx_Version >> 8)},
+ {SB_SMBUS_REG24+2, 0x00, RC_Information},
+ {SB_SMBUS_REG24+3, 0x00, Additional_Changes_Indicator},
+ {SB_SMBUS_REG43, ~(UINT8)BIT3, BIT3}, //Make BAR registers of smbus invisible.
+ {SB_SMBUS_REGAE, ~(UINT8)(BIT6 + BIT5), BIT6 + BIT5}, //Disable Timer IRQ enhancement for proper operation of the 8254 timer.
+ // [6] - IoApicPicArbEn, set 1 to enable arbiter between APIC and PIC interrupts
+ {SB_SMBUS_REGAD, ~(UINT8)(BIT0+BIT1+BIT2+BIT4), BIT0+BIT3}, // Initialize SATA to default values, SATA Enabled,
+ // Combined mode enabled, SATA as primary, power saving enable
+ {SB_SMBUS_REGAF, 0xE3, 6 << 2}, // Set SATA Interrupt to INTG#
+ {SB_SMBUS_REG68, BIT3, 0 }, // First disable all usb controllers and then enable then according to setup selection
+ {0xFF, 0xFF, 0xFF},
+
+ // IDE Device(Bus 0, Dev 20, Func 1)
+ {0x00, IDE_BUS_DEV_FUN, 0},
+ {SB_IDE_REG62+1, ~(UINT8)BIT0, BIT5}, // Enabling IDE Explicit Pre-Fetch IDE PCI Config 0x62[8]=0
+ // Allow MSI capability of IDE controller to be visible. IDE PCI Config 0x62[13]=1
+ {0xFF, 0xFF, 0xFF},
+
+ // Azalia Device(Bus 0, Dev 20, Func 2)
+ {0x00, AZALIA_BUS_DEV_FUN, 0},
+ {SB_AZ_REG4C, ~(UINT8)BIT0, BIT0},
+ {0xFF, 0xFF, 0xFF},
+
+ // LPC Device(Bus 0, Dev 20, Func 3)
+ {0x00, LPC_BUS_DEV_FUN, 0},
+
+ {SB_LPC_REG40, ~(UINT8)BIT2, BIT2}, // Enabling LPC DMA Function 0x40[2]
+ {SB_LPC_REG78, ~(UINT8)BIT1, 00}, // Disables MSI capability
+ {0xFF, 0xFF, 0xFF},
+
+ // P2P Bridge(Bus 0, Dev 20, Func 4)
+ {0x00, SBP2P_BUS_DEV_FUN, 0},
+
+ {SB_P2P_REG64+1, 0xFF, BIT7+BIT6}, //Adjusting CLKRUN#, PCIB_PCI_Config 0x64[15]=01
+ //Enabling arbiter fix, PCIB_PCI_Config 0x64[14]=01
+ {SB_P2P_REG64+2, 0xFF, BIT4}, //Enabling One-Prefetch-Channel Mode, PCIB_PCI_config 0x64 [20]
+
+ {SB_P2P_REG0D, 0x00, 0x40}, //Setting Latency Timers to 0x40, Enables the PCIB to retain ownership
+ {SB_P2P_REG1B, 0x00, 0x40}, // of the bus on the Primary side and on the Secondary side when GNT# is deasserted.
+
+ {0xFF, 0xFF, 0xFF},
+
+ // SATA Device(Bus 0, Dev 17, Func 0)
+ {0x00, SATA_BUS_DEV_FUN, 0},
+ {SB_SATA_REG44, 0xff, BIT0}, // Enables the SATA watchdog timer register prior to the SATA BIOS post
+ {SB_SATA_REG40+3, 0xff, BIT5}, // RPR setting: Disable the testing/enhancement mode SATA_PCI_config 0x40 [29] = 1
+ {SB_SATA_REG48+2, 0xff, BIT5}, // RPR setting: Disable the testing/enhancement mode SATA_PCI_config 0x48 [24] = 1, [21] = 1
+ {SB_SATA_REG48+3, 0xff, BIT0},
+ {SB_SATA_REG44 + 2, 0, 0x10}, // Program watchdog timer with 16 retries before timer time-out.
+ {0xFF, 0xFF, 0xFF},
+};
+
+
+REG8MASK sbEarlyPostPmioInitTbl[]={
+ // index andmask ormask
+ {SB_PMIO_REG55, ~(UINT8)(BIT3+BIT4+BIT5), BIT5+BIT3}, //BIT3(PcieNative)=1b, BIT4(Pcie_Wak_Mask)=0b, BIT5(Pcie_WAK_Sci)=1b
+ {SB_PMIO_REG01, 0xff, BIT1},
+ {SB_PMIO_REG0E, 0xff, BIT2 + BIT3},
+ {SB_PMIO_REG10, 0x3E, (BIT6+BIT5+BIT3+BIT1)}, // RTC_En_En + TMR_En_En + GLB_EN_EN and clear EOS_EN + PciExpWakeDisEn
+ {SB_PMIO_REG61, 0xFF, 0x40}, // USB Device Support to Wakeup System from S3/S4 state, USB PME & PCI Act from NB
+ {SB_PMIO_REG59, 0xFC, 0x00 }, // Clear the flash controller bits BIT1:0
+ {SB_PMIO_REG01, 0xFF, 0x97 }, // Clear all the status
+ {SB_PMIO_REG05, 0xFF, 0xFF },
+ {SB_PMIO_REG06, 0xFF, 0xFF },
+ {SB_PMIO_REG07, 0xFF, 0xFF },
+ {SB_PMIO_REG0F, 0xFF, 0x1F },
+ {SB_PMIO_REG1D, 0xFF, 0xFF },
+ {SB_PMIO_REG39, 0xFF, 0xFF },
+ {SB_PMIO_REG7C, ~(UINT8)(BIT5+BIT3+BIT2), BIT3+BIT2}, //Turn on BLink LED
+ {SB_PMIO_REG67, 0xFF, 0x06}, // C State enable, must be set in order to exercise C state
+ {SB_PMIO_REG68, 0x38, 0x84},
+ {SB_PMIO_REG8D, 0xFF, 0x01}, // Set PM_Reg_0x8D[0] to enable PmeTurnOff/PmeMsgAck handshake to fix PCIE LAN S3/S4 wake failure
+ {SB_PMIO_REG84, 0xFD, BIT3+BIT0},
+ {SB_PMIO_REG53, 0xFF, BIT7+BIT6}, //ACPI System Clock setting, PMIO Reg 0x53[6]=1. Our reference clock
+ //is either 25 or 100Mhz and so the default acpi clock is actually
+ //running at 12.5Mhz and so the system time will run slow. We have
+ //generated another internal clock which runs at 14.318Mhz which is the
+ //correct frequency. We should set this bit to turn on this feature PMIO_REG53[6]=1
+ //PCI Clock Period, PM_IO 0x53 [7] = 1. By setting this, PCI clock period
+ //increase to 30.8 ns.
+ {SB_PMIO_REG95, ~(UINT8)(BIT2+BIT1+BIT0), BIT2+BIT1}, //USB Advanced Sleep Control, Enables USB EHCI controller
+ //to sleep for 6 uframes in stead of the standard 10us to
+ //improve power saving.
+ {SB_PMIO_REGD7, 0xFF, BIT6+BIT1},
+
+};
+
+
+// commonInitEarlyBoot - set /SMBUS/ACPI/IDE/LPC/PCIB. This settings should be done during S3 resume also
+void commonInitEarlyBoot(AMDSBCFG* pConfig) {
+ UINT16 dwTempVar;
+ CPUID_DATA CpuId;
+ CPUID_DATA CpuId_Brand;
+ UINT8 dbValue;
+ UINT32 ddValue;
+ UINT8 Family, Model, Stepping;
+
+ TRACE((DMSG_SB_TRACE, "CIMx - Entering commonInitEarlyBoot \n"));
+ CpuidRead (0x01, &CpuId);
+ CpuidRead (0x80000001, &CpuId_Brand); //BrandID
+
+ //Early post initialization of pci config space
+ programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbEarlyPostByteInitTable[0]), sizeof(sbEarlyPostByteInitTable)/sizeof(REG8MASK) );
+
+ // RPR 5.5 Clear PM_IO 0x65[4] UsbResetByPciRstEnable, Set this bit so that usb gets reset whenever there is PCIRST.
+ RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT4, BIT4);
+
+
+ #if 0 //KZ [083011]-It's used wrong BIOS SIZE for Coreboot.
+ //For being compatible with earlier revision, check whether ROM decoding is changed already outside CIMx before
+ //changing it.
+ ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG68, AccWidthUint16 | S3_SAVE, &dwTempVar);
+ if ( (dwTempVar == 0x08) || (dwTempVar == 0x00))
+ RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG68, AccWidthUint8 | S3_SAVE, 0, 0x0E);// Change the 1Mb below ROM decoding range to 0xE0000 to 0xFFFFF
+ #endif
+
+ if (pConfig->AzaliaController == 1)
+ RWPMIO(SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 0);
+ else
+ RWPMIO(SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, 0xFF, BIT3);
+
+ //Disable or Enable PCI Clks based on input
+ RWPCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG42, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT5+BIT4+BIT3+BIT2), ((pConfig->PciClks) & 0x0F) << 2 );
+ RWPCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG4A, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT1+BIT0), ((pConfig->PciClks) >> 4) | ((pConfig->PciClk5) << 1) );
+ ReadPMIO(SB_PMIO_REG2C, AccWidthUint16, &dwTempVar); // Read Arbiter address, Arbiter address is in PMIO 2Ch
+ RWIO(dwTempVar, AccWidthUint8, 0, 0); // Write 0 to enable the arbiter
+
+ abLinkInitBeforePciEnum(pConfig); // Set ABCFG registers
+ // Set LDTSTP# duration to 10us for HydraD CPU model 8, 9 or A; or when HT link is 200MHz; or Family15 Orochi CPU C32/G34 package
+ ddValue = CpuId.REG_EAX & 0x00FF00F0;
+ dbValue = 1;
+
+ if((CpuId.REG_EAX & 0x00F00F00) == 0x00600F00) {
+ if(((CpuId_Brand.REG_EBX & 0xF0000000) == 0x30000000) || ((CpuId_Brand.REG_EBX & 0xF0000000) == 0x50000000)) {
+ //Orochi processor G34/C32, set to 10us
+ dbValue = 10;
+ }
+ else {
+ // Orochi processor AM3, set to 5us
+ dbValue = 5;
+ }
+ }
+
+ if ((pConfig->AnyHT200MhzLink) || (ddValue == 0x100080) || (ddValue == 0x100090) || (ddValue == 0x1000A0)) {
+ //any kind of CPU run HT at 200Mhz , or HydraD CPU model 8, 9 or A, set to 10us
+ dbValue = 10;
+ }
+
+
+ RWPMIO(SB_PMIO_REG8B, AccWidthUint8 | S3_SAVE, 0x00, dbValue);
+
+ // Enable/Disable watchdog timer
+ RWPMIO(SB_PMIO_REG69, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, (UINT8)(!pConfig->WatchDogTimerEnable));
+
+ // Per SB700/SP5100 RPR 2.5
+ //
+ // Enable C1e stutter timer for any system with chip revision >= A14
+ // Set SMBUS:0x5c[22:16] = 16 -- Set amount of idle time to 16ms
+ //
+
+ if (getRevisionID() >= SB700_A14) {
+ dwTempVar = 0x0010;
+
+ // Set PMIO:0xcb[5] = 1 -- AutoStutterTimerEn, set 1 to enable
+ // Set PMIO:0xcb[6] = 1 -- AutoStutterTimeSel, 1=1ms timer tick increment; 0=2us increment
+ RWPMIO(SB_PMIO_REGCB, AccWidthUint8 | S3_SAVE, 0xff, BIT6 + BIT5);
+
+ Family = (UINT8)((CpuId.REG_EAX & 0x00ff0000)>> 16);
+ Model = (UINT8)((CpuId.REG_EAX & 0x000000f0)>> 4);
+ Stepping = (UINT8) (CpuId.REG_EAX & 0x0000000f);
+
+ // For Server system (SP5100) with CPU type = Family 10h with LS2 mode enabled:
+ // Model=6 && Stepping=2 || Model=(4I5|6) && Stepping >=3 || Model=(8|9) && Stepping >= 1 || Model Ah
+ // Set SMBUS:0x5c[22:16] = 20 -- Set amount of idle time to 20ms
+ if (IsLs2Mode() && (Family == 0x10)) {
+ switch( Model ){
+ case 0x4:
+ case 0x5:
+ if( Stepping >= 3 ) dwTempVar = 0x14;
+ break;
+ case 0x6:
+ if( Stepping >= 2 ) dwTempVar = 0x14;
+ break;
+ case 0x8:
+ if( Stepping >= 1 ) dwTempVar = 0x14;
+ break;
+ case 0x9:
+ if( Stepping >= 1 ) dwTempVar = 0x14;
+ break;
+ case 0xA:
+ dwTempVar = 0x14;
+ break;
+ }
+ }
+ // Set SMBUS:0x5c[7] = 1 -- CheckC3, set 1 to check for C3 state
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG5C, AccWidthUint32 | S3_SAVE, ~(0x7F << 16), (dwTempVar << 16) + BIT7);
+ }
+
+ //Message-Triggered C1E is not supported in Family 10h G34r1 HY-D0 (0x00100F90) and Family 10h C32 HY-D0 (0x00100F80) processor.
+ ddValue = CpuId.REG_EAX;
+ if ((getRevisionID() == SB700_A15) && (pConfig->MTC1e == CIMX_OPTION_ENABLED) && (ddValue != 0x00100F90) && (ddValue != 0x00100F80)) {
+ //
+ // MTC1e: For A15 (server only) - The settings here borrow the existing legacy ACPI BM_STS and BM_RLD bits as a
+ // mechanism to break out from C1e under a non-OS controlled C3 state. Under this scheme, the logic will automatically
+ // clear the BM_STS bit whenever it enters C1e state. Whenever BM_REQ#/IDLE_EXIT# is detected, it will cause the
+ // BM_STS bit to be set and therefore causing the C state logic to exit.
+ //
+ // Set BMReqEnable (SMBUS:0x64[5]=1) to enable the pin as BM_REQ#/IDLE_EXIT# to the C state logic
+ // Set CheckOwnReq (SMBUS:0x64[4]=0) to force IDLE_EXIT# to set BM_STS and wake from C3
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64, AccWidthUint8 | S3_SAVE, 0xEF, BIT5);
+
+ // Set PCI_Active_enable (PMIO:0x61[2]=1), the secondary enable bit for SB to monitor BM_REQ#/IDLE_EXIT#
+ RWPMIO(SB_PMIO_REG61, AccWidthUint8 | S3_SAVE, 0xff, BIT2);
+
+ // Set auto_bm_rld (PMIO:0x9a[4]=1) so that assertion on BM_REQ#/IDLE_EXIT# pin will cause C state logic to break out from C1e
+ // Set auto_clr_bm_sts (PMIO:0x9a[5]=1) will cause the C state logic to automatically clear the BM_STS bit whenever it sees a C1e entry
+ RWPMIO(SB_PMIO_REG9A, AccWidthUint8 | S3_SAVE, 0xff, BIT5 + BIT4);
+
+
+ // MTC1e: The logic basically counts the number of HALT_ENTER messages. When it has received the number of HALT_ENTER
+ // messages equal to NumOfCpu (PMIO:0xc9[3:0]), it will generate an internal C1e command to the C state logic.
+ // The count increments when it sees HALT_ENTER message after it has generated the C1e command, and it treats the
+ // HALT_EXIT message as a break event.
+ //
+ // Set ServerCEn
+ RWPMIO(SB_PMIO_REGBB, AccWidthUint8 | S3_SAVE, 0xFF, BIT7);
+
+ // Enable counting HALT
+ // PMIO:0xc9[4] = CountHaltMsgEn
+ // PMIO:0xc9[3:0] = NumOfCpu, set to 1 since CPU logic will coordinate among cores and only generate one HALT message
+ RWPMIO(SB_PMIO_REGC9, AccWidthUint8 | S3_SAVE, 0xE0, BIT4 + 1);
+ }
+
+ c3PopupSetting(pConfig);
+
+ TRACE((DMSG_SB_TRACE, "CIMx - Exiting commonInitEarlyBoot \n"));
+}
+
+
+void commonInitEarlyPost(AMDSBCFG* pConfig){
+ //early post initialization of pmio space
+ programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sbEarlyPostPmioInitTbl[0]), (sizeof(sbEarlyPostPmioInitTbl)/sizeof(REG8MASK)) );
+ CallBackToOEM(PULL_UP_PULL_DOWN_SETTINGS, NULL, pConfig);
+}
+
+
+// AB-Link Configuration Table
+ABTBLENTRY abTblEntry600[]={
+ // Enabling Downstream Posted Transactions to Pass Non-Posted Transactions for the K8 Platform ABCFG 0x10090[8] = 1
+ // ABCFG 0x10090 [16] = 1, ensures the SMI# message to be sent before the IO command is completed. The ordering of
+ // SMI# and IO is important for the IO trap to work properly.
+ {ABCFG,SB_AB_REG10090 ,BIT16+BIT8 ,BIT16+BIT8 },
+ // Enabling UpStream DMA Access AXCFG: 0x04[2]=1
+ {AXCFG,SB_AB_REG04 ,BIT2 ,BIT2 },
+ // Setting B-Link Prefetch Mode ABCFG 0x80 [17] = 1 ABCFG 0x80 [18] = 1
+ {ABCFG,SB_AB_REG80 ,BIT17+BIT18 ,BIT17+BIT18 },
+ // Disable B-Link client's credit variable in downstream arbitration equation (for All Revisions)
+ // ABCFG 0x9C[0] = 1 Disable credit variable in downstream arbitration equation
+ // Enabling Additional Address Bits Checking in Downstream Register Programming
+ // ABCFG 0x9C[1] = 1
+ {ABCFG,SB_AB_REG9C ,BIT8+BIT1+BIT0 ,BIT8+BIT1+BIT0 },
+ // Enabling IDE/PCIB Prefetch for Performance Enhancement
+ // IDE prefetch ABCFG 0x10060 [17] = 1 ABCFG 0x10064 [17] = 1
+ // PCIB prefetch ABCFG 0x10060 [20] = 1 ABCFG 0x10064 [20] = 1
+ {ABCFG,SB_AB_REG10060 ,BIT17+BIT20 ,BIT17+BIT20 }, // IDE+PCIB prefetch enable
+ {ABCFG,SB_AB_REG10064 ,BIT17+BIT20 ,BIT17+BIT20 }, // IDE+PCIB prefetch enable
+ // Enabling Detection of Upstream Interrupts ABCFG 0x94 [20] = 1
+ // ABCFG 0x94 [19:0] = cpu interrupt delivery address [39:20]
+ {ABCFG,SB_AB_REG94 ,BIT20 ,BIT20+0x00FEE },
+ // Programming cycle delay for AB and BIF clock gating
+ // Enabling AB and BIF Clock Gating
+ // Enabling AB Int_Arbiter Enhancement
+ // Enabling Requester ID
+ {ABCFG,SB_AB_REG10054, 0x00FFFFFF , 0x010407FF },
+ {ABCFG,SB_AB_REG98 , 0xFFFF00FF , 0x00014700 }, // Enable the requestor ID for upstream traffic ABCFG 0x98[16]=1
+// {ABCFG,SB_AB_REG54 , 0x00FF0000 , 0x01040000 },
+ {ABCFG,SB_AB_REG54 , 0x00FF0000 , 0x00040000 },
+
+ {ABCFG,0,0,-1}, // This dummy entry is to clear ab index
+ {-1, -1, -1, -1 },
+};
+
+
+// AB-Link Configuration Table
+ABTBLENTRY abTblForA15[]={
+
+ //SMI Reordering fix
+ {ABCFG, SB_AB_REG90 ,BIT21 , BIT21 },
+ {ABCFG, SB_AB_REG9C ,BIT15+BIT9+BIT5 ,BIT15+BIT9+BIT5},
+
+ //Posted pass NP Downstream feature
+ {AX_INDXC, SB_AB_REG02, BIT9 ,BIT9 },
+ {ABCFG, SB_AB_REG9C, BIT14+BIT13+BIT12+BIT11+BIT10+BIT7+BIT6 , BIT14+BIT13+BIT12+BIT11+BIT10+BIT7+BIT6},
+ {ABCFG, SB_AB_REG1009C, BIT5+BIT4 , BIT5+BIT4},
+
+ //Posted pass NP upstream feature
+ {ABCFG, SB_AB_REG58, BIT15+BIT14+BIT13+BIT12+BIT11, BIT15+BIT14+BIT13+BIT11},
+
+ //64 bit Non-posted memory write support
+ {AX_INDXC, SB_AB_REG02, BIT10 ,BIT10 },
+
+ {ABCFG, SB_AB_REG10090, BIT12+BIT11+BIT10+BIT9 , BIT12+BIT11+BIT10+BIT9},
+
+ {ABCFG,0,0,-1}, // This dummy entry is to clear ab index
+ {-1, -1, -1, -1 },
+};
+
+
+// abLinkInitBeforePciEnum - Set ABCFG registers
+void abLinkInitBeforePciEnum(AMDSBCFG* pConfig){
+ ABTBLENTRY *pAbTblPtr;
+
+ // disable PMIO decoding when AB is set
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT2, 0);
+
+ pAbTblPtr = (ABTBLENTRY *)FIXUP_PTR(&abTblEntry600[0]);
+ abcfgTbl(pAbTblPtr);
+
+ if (getRevisionID() > SB700_A11){
+ //Enable OHCI Prefetch
+ writeAlink( (SB_AB_REG80 | (ABCFG << 30)), (readAlink((SB_AB_REG80 | (ABCFG << 30)))) | BIT0);
+ //Register bit to maintain correct ordering of SMI and IO write completion
+ writeAlink( (SB_AB_REG8C | (ABCFG << 30)), (readAlink((SB_AB_REG8C | (ABCFG << 30)))) | BIT8);
+ }
+
+ if (getRevisionID() >= SB700_A14){
+ //Enable fix for TT SB01345
+ writeAlink( (SB_AB_REG90 | (ABCFG << 30)), (readAlink((SB_AB_REG90 | (ABCFG << 30)))) | BIT17);
+ //Disable IO Write and SMI ordering enhancement
+ writeAlink( (SB_AB_REG9C | (ABCFG << 30)), (readAlink((SB_AB_REG9C | (ABCFG << 30)))) & (0xFFFFFEFF));
+ }
+
+ if (getRevisionID() >= SB700_A15) {
+ pAbTblPtr = (ABTBLENTRY *)FIXUP_PTR(&abTblForA15[0]);
+ abcfgTbl(pAbTblPtr);
+ }
+
+
+ // enable pmio decoding after ab is configured
+ // or BYTE PTR es:[ebp+SMBUS_BUS_DEV_FUN shl 12 + SB_SMBUS_REG64], BIT2
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT2, BIT2);
+}
+
+
+void abcfgTbl(ABTBLENTRY* pABTbl){
+ UINT32 ddValue;
+
+ while ((pABTbl->regType) != 0xFF){
+ TRACE((DMSG_SB_TRACE, "RegType: %X, RegNumber:%X, AndMask=%X, OrMask=%X \n",pABTbl->regType , pABTbl->regIndex, pABTbl->regMask, pABTbl->regData));
+ if (pABTbl->regType > AX_INDXP){
+ ddValue = pABTbl->regIndex | (pABTbl->regType << 30);
+ writeAlink(ddValue, ((readAlink(ddValue)) & (0xFFFFFFFF^(pABTbl->regMask)))|pABTbl->regData);
+ }
+ else{
+ ddValue = 0x30 | (pABTbl->regType << 30);
+ writeAlink(ddValue, pABTbl->regIndex);
+ ddValue = 0x34 | (pABTbl->regType << 30);
+ writeAlink(ddValue, ((readAlink(ddValue)) & (0xFFFFFFFF^(pABTbl->regMask)))|pABTbl->regData);
+ }
+ ++pABTbl;
+ }
+
+ //Clear ALink Access Index
+ ddValue = 0;
+ WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &ddValue);
+ TRACE((DMSG_SB_TRACE, "Exiting abcfgTbl\n"));
+}
+
+
+// programSubSystemIDs - Config Subsystem ID for all SB devices.
+void programSubSystemIDs(AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions){
+ UINT32 ddTempVar;
+ UINT16 dwDeviceId;
+
+ RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci0Ssid);
+ RWPCI((USB1_OHCI1_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci1Ssid);
+ RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci2Ssid);
+ RWPCI((USB2_OHCI1_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci3Ssid);
+ RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci4Ssid);
+
+ RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ehci0Ssid);
+ RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ehci1Ssid);
+
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->SmbusSsid);
+ RWPCI((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->IdeSsid);
+ RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->LpcSsid);
+ RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->AzaliaSsid);
+
+ ddTempVar = pStaticOptions->SataIDESsid;
+ if ( ((pConfig->SataClass) == AHCI_MODE) || ((pConfig->SataClass)== IDE_TO_AHCI_MODE) )
+ ddTempVar = pStaticOptions->SataAHCISsid;
+
+ ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, &dwDeviceId);
+ if ((pConfig->SataClass) == RAID_MODE){
+ ddTempVar = pStaticOptions->SataRAIDSsid;
+ if (dwDeviceId==SB750_SATA_DEFAULT_DEVICE_ID)
+ ddTempVar = pStaticOptions->SataRAID5Ssid;
+ }
+
+ if ( ((pConfig->SataClass) == AMD_AHCI_MODE) || ((pConfig->SataClass) == IDE_TO_AMD_AHCI_MODE) ) {
+ ddTempVar = pStaticOptions->SataAHCISsid;
+ }
+ RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG2C, AccWidthUint32 | S3_SAVE, 0x00, ddTempVar);
+}
+
+void commonInitLateBoot(AMDSBCFG* pConfig){
+ UINT8 dbValue;
+ UINT32 ddVar;
+
+ // We need to do the following setting in late post also because some bios core pci enumeration changes these values
+ // programmed during early post.
+ // RPR 4.5 Master Latency Timer
+ // Master Latency Timer PCIB_PCI_config 0x0D/0x1B = 0x40
+ // Enables the PCIB to retain ownership of the bus on the
+ // Primary side and on the Secondary side when GNT# is deasserted.
+ //mov BYTE PTR es:[ebp+SBP2P_BUS_DEV_FUN shl 12 + SB_P2P_REG0D], 40h
+ //mov BYTE PTR es:[ebp+SBP2P_BUS_DEV_FUN shl 12 + SB_P2P_REG1B], 40h
+ dbValue = 0x40;
+ WritePCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG0D, AccWidthUint8, &dbValue);
+ WritePCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG1B, AccWidthUint8, &dbValue);
+
+ //SB P2P AutoClock control settings.
+ ddVar = (pConfig->PcibAutoClkCtrlLow) | (pConfig->PcibAutoClkCtrlLow);
+ WritePCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG4C, AccWidthUint32, &ddVar);
+ ddVar = (pConfig->PcibClkStopOverride);
+ RWPCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG50, AccWidthUint16, 0x3F, (UINT16) (ddVar << 6));
+
+ if (pConfig->MobilePowerSavings){
+ //If RTC clock is not driven to any chip, it should be shut-off. If system uses external RTC, then SB needs to
+ //drive out RTC clk to external RTC chip. If system uses internal RTC, then this clk can be shut off.
+ RWPMIO(SB_PMIO_REG68, AccWidthUint8, ~(UINT32)BIT4, (pConfig->ExternalRTCClock)<<4);
+ if (!getClockMode()){
+ if (!(pConfig->UsbIntClock) ){
+ //If the external clock is used, the second PLL should be shut down
+ RWPMIO(SB_PMIO_REGD0, AccWidthUint8, 0xFF, BIT0);
+ // If external clock mode is used, the 25Mhz oscillator buffer can be turned-off by setting PMIO 0xD4[7]=1
+ RWPMIO(SB_PMIO_REGD4, AccWidthUint8, 0xFF, BIT7);
+ //Disable unused clocks
+ RWPMIO(SB_PMIO_REGCA, AccWidthUint8, 0xFF, 0x7E);
+ }
+ }
+ writeAlink(0x30, SB_AB_REG40);
+ writeAlink(0x34, ((readAlink(0x34)) & 0xFFFF0000) | 0x008A);
+
+ }
+ else{
+ //Don't shutoff RTC clock
+ RWPMIO(SB_PMIO_REG68, AccWidthUint8, ~(UINT32)BIT4, 0);
+ //Dont disable second PLL
+ RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)BIT0, 0);
+ //Enable the 25Mhz oscillator
+ RWPMIO(SB_PMIO_REGD4, AccWidthUint8, ~(UINT32)BIT7, 0);
+ RWPMIO(SB_PMIO_REGCA, AccWidthUint8, 0xFF, 0x00);
+ }
+}
+
+
+void
+hpetInit (AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions)
+{
+ DESCRIPTION_HEADER* pHpetTable;
+
+ if (pConfig->HpetTimer == 1) {
+ UINT8 dbTemp;
+
+ RWPMIO(SB_PMIO_REG9A, AccWidthUint8, 0xFF, BIT7);
+ // Program the HPET BAR address
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGB4, AccWidthUint32 | S3_SAVE, 0, pStaticOptions->HpetBase);
+
+ // Enable HPET MMIO decoding: SMBUS:0x43[4] = 1
+ // Enable HPET MSI support only when HpetMsiDis == 0
+ dbTemp = (pConfig->HpetMsiDis)? BIT4 : BIT7 + BIT6 + BIT5 + BIT4;
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, dbTemp);
+ // Program HPET default clock period
+ if (getRevisionID() >= SB700_A13) {
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG34, AccWidthUint32 | S3_SAVE, 0x00, 0x429B17E);
+ }
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT3);
+ // Enable High Precision Event Timer (also called Multimedia Timer) interrupt
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + (SB_SMBUS_REG64+1), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT2, BIT2);
+ }
+ else {
+ if (!(pConfig->S3Resume)) {
+// pHpetTable = (DESCRIPTION_HEADER*)ACPI_LocateTable('TEPH');
+ pHpetTable = (DESCRIPTION_HEADER*)ACPI_LocateTable(Int32FromChar ('T', 'E', 'P', 'H'));
+ if (pHpetTable != NULL) {
+// pHpetTable->Signature = 'HPET';
+ pHpetTable->Signature = Int32FromChar ('T', 'E', 'P', 'H');
+ }
+ }
+ }
+}
+
+
+void c3PopupSetting(AMDSBCFG* pConfig){
+ UINT8 dbTemp;
+ CPUID_DATA CpuId;
+
+ CpuidRead (0x01, &CpuId);
+ //RPR 2.3 C-State and VID/FID Change
+ dbTemp = GetNumberOfCpuCores();
+ if (dbTemp > 1){
+ //PM_IO 0x9A[5]=1, For system with dual core CPU, set this bit to 1 to automatically clear BM_STS when the C3 state is being initiated.
+ //PM_IO 0x9A[4]=1, For system with dual core CPU, set this bit to 1 and BM_STS will cause C3 to wakeup regardless of BM_RLD
+ //PM_IO 0x9A[2]=1, Enable pop-up for C3. For internal bus mastering or BmReq# from the NB, the SB will de-assert
+ //LDTSTP# (pop-up) to allow DMA traffic, then assert LDTSTP# again after some idle time.
+ RWPMIO(SB_PMIO_REG9A, AccWidthUint8, 0xFF, BIT5+BIT4+BIT2);
+ }
+
+ //SB700 needs to changed for RD790 support
+ //PM_IO 0x8F [4] = 0 for system with RS690
+ //Note: RS690 north bridge has AllowLdtStop built for both display and PCIE traffic to wake up the HT link.
+ //BmReq# needs to be ignored otherwise may cause LDTSTP# not to toggle.
+ //PM_IO 0x8F[5]=1, Ignore BM_STS_SET message from NB
+ RWPMIO(SB_PMIO_REG8F, AccWidthUint8, ~(UINT32)(BIT5+BIT4), BIT5);
+
+ //LdtStartTime = 10h for minimum LDTSTP# de-assertion duration of 16us in StutterMode. This is to guarantee that
+ //the HT link has been safely reconnected before it can be disconnected again. If C3 pop-up is enabled, the 16us also
+ //serves as the minimum idle time before LDTSTP# can be asserted again. This allows DMA to finish before the HT
+ //link is disconnected.
+ //Increase LDTSTOP Deassertion time for SP5100 to 20us, SB700 remains the same
+ dbTemp = (IsServer())? 0x14 : 0x10;
+ RWPMIO(SB_PMIO_REG88, AccWidthUint8, 0x00, dbTemp);
+
+ //This setting provides 16us delay before the assertion of LDTSTOP# when C3 is entered. The
+ //delay will allow USB DMA to go on in a continous manner
+ RWPMIO(SB_PMIO_REG89, AccWidthUint8, 0x00, 0x10);
+
+ //Set this bit to allow pop-up request being latched during the minimum LDTSTP# assertion time
+ RWPMIO(SB_PMIO_REG52, AccWidthUint8, 0xFF, BIT7);
+
+}
+
diff --git a/src/vendorcode/amd/cimx/sb700/SbCmnLib.c b/src/vendorcode/amd/cimx/sb700/SbCmnLib.c
new file mode 100644
index 0000000..130dbc4
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/SbCmnLib.c
@@ -0,0 +1,108 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+UINT8 isEcPresent(){
+ UINT8 dbFlag;
+ UINT16 dwVar0;
+
+ //Read the EC configuration register base address from LPCCfg_A4[15:1]
+ //Write 0x5A to the EC config index register to unlock the access
+ //Write 0x20 to the EC config index register to select the device ID register
+ //Read the value of device ID register from the EC config data register
+ //If the value read is 0xB7, then EC is enabled.
+ //Write 0xA5 to re-lock the EC config index register if EC is enabled.
+
+ ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwVar0);
+ dwVar0 &= 0xFFFE;
+ RWIO(dwVar0, AccWidthUint8, 0, 0x5A);
+ RWIO(dwVar0, AccWidthUint8, 0, 0x20);
+ ReadIO(dwVar0+1, AccWidthUint8, &dbFlag);
+ RWIO(dwVar0, AccWidthUint8, 0, 0xA5);
+
+ return ( dbFlag == 0xB7);
+}
+
+void
+getSbInformation (
+SB_INFORMATION *sbInfo){
+ UINT16 dwDevId;
+ UINT8 dbRev;
+
+ ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG02, AccWidthUint16 | S3_SAVE, &dwDevId);
+ ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08, AccWidthUint8 | S3_SAVE, &dbRev);
+ sbInfo->sbModelMask = SB_MODEL_UNKNOWN;
+ if ( (dwDevId == SB7XX_DEVICE_ID) && (dbRev <= SB_Rev_Sb7xx_A14) ){
+ sbInfo->sbModelMask |= SB_MODEL_SB700;
+ sbInfo->sbModelMask |= SB_MODEL_SR5690;
+ sbInfo->sbRev = dbRev;
+ ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint8 | S3_SAVE, &dbRev);
+ if (dbRev & 01)
+ sbInfo->sbModelMask |= SB_MODEL_SB750;
+ if (isEcPresent())
+ sbInfo->sbModelMask |= SB_MODEL_SB710;
+ return;
+ }
+}
+
+
+SB_CAPABILITY_SETTING
+getSbCapability (
+SB_CAPABILITY_ITEM sbCapabilityItem
+)
+{
+ SB_CAPABILITY_SETTING sbCapSetting=SB_UNKNOWN;
+ UINT32 ddTemp0;
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 00);
+ ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG10, AccWidthUint32, &ddTemp0);
+
+ if (sbCapabilityItem < Sb_Unknown_Capability)
+ sbCapSetting = ((ddTemp0 >> (sbCapabilityItem << 1) ) & 0x03);
+
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT3);
+ return sbCapSetting;
+}
+
+
+void
+setSbCapability (
+SB_CAPABILITY_ITEM sbCapabilityItem, SB_CAPABILITY_SETTING sbCapSetting
+)
+{
+ UINT32 ddTemp0;
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 00);
+ ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG10, AccWidthUint32, &ddTemp0);
+ if ( (sbCapabilityItem < Sb_Unknown_Capability) & (sbCapSetting < Sb_Cap_Setting_Unknown) )
+ ddTemp0 = (ddTemp0 & ~(0x03 << (sbCapabilityItem << 1))) | ( (sbCapSetting & 0x03) << (sbCapabilityItem << 1));
+ WritePCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG10, AccWidthUint32, &ddTemp0);
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT3);
+}
diff --git a/src/vendorcode/amd/cimx/sb700/SbCmnLib.h b/src/vendorcode/amd/cimx/sb700/SbCmnLib.h
new file mode 100644
index 0000000..e737bc9
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/SbCmnLib.h
@@ -0,0 +1,89 @@
+/*;********************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; * Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; * Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; * Neither the name of Advanced Micro Devices, Inc. nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*********************************************************************************/
+
+#ifndef _AMD_SBLIB_H_
+#define _AMD_SBLIB_H_
+
+//SB7xx Family
+#define SB7xx_DEVICE_ID 0x4385
+#define SB700 0x00
+#define SB750 0x01
+#define SB710 0x02
+
+//SB800 Family
+#define SB800 0x10
+
+#define SB_UNKNOWN 0xFF
+
+//SB700 Revision IDs
+#define SB700_A11 0x39
+#define SB700_A12 0x3A
+#define SB700_A13 0x3B
+#define SB700_A14 0x3C
+
+#define SB_Rev_Sb7xx_A11 0x39
+#define SB_Rev_Sb7xx_A12 0x3A
+#define SB_Rev_Sb7xx_A13 0x3B
+#define SB_Rev_Sb7xx_A14 0x3C
+
+
+typedef enum {
+ Sb_Raid0_1_Capability, ///
+ Sb_Raid5_Capability, ///
+ Sb_Ahci_Capability, ///
+ Sb_Unknown_Capability
+} SB_CAPABILITY_ITEM;
+
+
+typedef enum {
+ Sb_Cap_Setting_Auto,
+ Sb_Cap_Setting_Enabled,
+ Sb_Cap_Setting_Disabled,
+ Sb_Cap_Setting_Unknown
+} SB_CAPABILITY_SETTING;
+
+
+#define SB_MODEL_SB700 BIT0
+#define SB_MODEL_SB750 BIT1
+#define SB_MODEL_SB710 BIT2
+#define SB_MODEL_SR5690 BIT3
+#define SB_MODEL_UNKNOWN BIT31
+
+typedef struct
+{
+ UINT32 sbModelMask;
+ UINT8 sbRev;
+}SB_INFORMATION;
+
+
+void getSbInformation (SB_INFORMATION *sbInfo);
+SB_CAPABILITY_SETTING getSbCapability (SB_CAPABILITY_ITEM sbCapabilityItem);
+void setSbCapability (SB_CAPABILITY_ITEM sbCapabilityItem, SB_CAPABILITY_SETTING sbCapSetting);
+
+#endif //#ifndef _AMD_SBLIB_H_
diff --git a/src/vendorcode/amd/cimx/sb700/SbDef.h b/src/vendorcode/amd/cimx/sb700/SbDef.h
new file mode 100644
index 0000000..01fc1b5
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/SbDef.h
@@ -0,0 +1,166 @@
+/*;********************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; * Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; * Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; * Neither the name of Advanced Micro Devices, Inc. nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*********************************************************************************/
+
+#ifndef _AMD_SBDEF_H_
+#define _AMD_SBDEF_H_
+
+//AMD Library Routines
+
+UINT64
+MsrRead (
+ IN UINT32 MsrAddress
+ );
+
+VOID
+MsrWrite (
+ IN UINT32 MsrAddress,
+ IN UINT64 Value
+ );
+
+void ReadIO(UINT16 Address, UINT8 OpFlag, void *Value);
+void WriteIO(UINT16 Address, UINT8 OpFlag, void *Value);
+void ReadPCI(UINT32 Address, UINT8 OpFlag, void *Value);
+void WritePCI(UINT32 Address,UINT8 OpFlag, void *Value);
+void RWPCI(UINT32 Address,UINT8 OpFlag,UINT32 Mask,UINT32 Data);
+void ReadIndexPCI32(UINT32 PciAddress,UINT32 IndexAddress,void* Value);
+void WriteIndexPCI32(UINT32 PciAddress,UINT32 IndexAddress,UINT8 OpFlag,void* Value);
+void RWIndexPCI32(UINT32 PciAddress,UINT32 IndexAddress,UINT8 OpFlag,UINT32 Mask,UINT32 Data);
+void RWIO (UINT16 Address, UINT8 OpFlag, UINT32 Mask, UINT32 Data);
+void ReadMEM(UINT32 Address,UINT8 OpFlag, void* Value);
+void WriteMEM(UINT32 Address,UINT8 OpFlag, void* Value);
+void RWMEM(UINT32 Address,UINT8 OpFlag,UINT32 Mask,UINT32 Data);
+UINT32 IsFamily10(void);
+UINT64 ReadMSR(UINT32 Address);
+void WriteMSR(UINT32 Address,UINT64 Value);
+void RWMSR(UINT32 Address, UINT64 Mask, UINT64 Value);
+void* LocateImage(UINT32 Signature);
+void* CheckImage( UINT32 Signature, void* ImagePtr);
+void Stall(UINT32 uSec);
+void Reset(void);
+CIM_STATUS RWSMBUSBlock(UINT8 Controller, UINT8 Address, UINT8 Offset, UINT8 BufferSize, UINT8* BufferPrt);
+void InitSerialOut(void);
+void ReadPMIO(UINT8 Address, UINT8 OpFlag, void* Value);
+void WritePMIO(UINT8 Address, UINT8 OpFlag, void* Value);
+void RWPMIO(UINT8 Address, UINT8 OpFlag, UINT32 AndMask, UINT32 OrMask);
+void ReadPMIO2(UINT8 Address, UINT8 OpFlag, void* Value);
+void WritePMIO2(UINT8 Address, UINT8 OpFlag, void* Value);
+void RWPMIO2(UINT8 Address, UINT8 OpFlag, UINT32 AndMask, UINT32 OrMask);
+void outPort80(UINT32 pcode);
+UINT8 GetNumberOfCpuCores(void);
+UINT8 ReadNumberOfCpuCores(void);
+UINT8 GetByteSum(void* pData, UINT32 Length);
+UINT32 readAlink(UINT32 Index);
+void writeAlink(UINT32 Index,UINT32 Data);
+
+//----------------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------------
+void azaliaInitAfterPciEnum (AMDSBCFG* pConfig);
+
+void SendBytePort(UINT8 Data);
+void SendStringPort(char* pstr);
+void ItoA(UINT32 Value,int Radix,char* pstr);
+AMDSBCFG* getConfigPointer(void);
+void saveConfigPointer(AMDSBCFG* pConfig);
+
+
+UINT32 GetFixUp(void);
+
+void sataInitAfterPciEnum(AMDSBCFG* pConfig);
+void sataInitBeforePciEnum(AMDSBCFG* pConfig);
+void sataInitLatePost(AMDSBCFG* pConfig);
+void sataDriveDetection(AMDSBCFG* pConfig, UINT32 ddBar5);
+void sataPhyWorkaround(AMDSBCFG* pConfig, UINT32 ddBar5);
+void forceOOB(UINT32 ddBar5);
+void shutdownUnconnectedSataPortClock(AMDSBCFG* pConfig, UINT32 ddBar5);
+void restrictSataCapabilities(AMDSBCFG* pConfig);
+
+
+void commonInitEarlyBoot(AMDSBCFG* pConfig);
+void commonInitEarlyPost(AMDSBCFG* pConfig);
+void setRevisionID(void);
+UINT8 getRevisionID(void);
+UINT8 IsServer (void);
+UINT8 IsLs2Mode (void);
+void abLinkInitBeforePciEnum(AMDSBCFG* pConfig);
+void abcfgTbl(ABTBLENTRY* pABTbl);
+void programSubSystemIDs(AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions);
+void commonInitLateBoot(AMDSBCFG* pConfig);
+void hpetInit(AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions);
+void c3PopupSetting(AMDSBCFG* pConfig);
+
+void sbBeforePciInit (AMDSBCFG* pConfig);
+void sbAfterPciInit(AMDSBCFG* pConfig);
+void sbLatePost(AMDSBCFG* pConfig);
+void sbBeforePciRestoreInit(AMDSBCFG* pConfig);
+void sbAfterPciRestoreInit(AMDSBCFG* pConfig);
+void sbSmmAcpiOn(AMDSBCFG* pConfig);
+UINT32 GetPciebase(void);
+UINT32 CallBackToOEM(UINT32 Func, UINTN Data,AMDSBCFG* pConfig);
+void sbSmmService(AMDSBCFG* pConfig);
+void softwareSMIservice(void);
+
+void sbPowerOnInit (AMDSBCFG *pConfig);
+void programPciByteTable(REG8MASK* pPciByteTable, UINT16 dwTableSize);
+void programPmioByteTable(REG8MASK* pPmioByteTable, UINT16 dwTableSize);
+UINT8 getClockMode(void);
+UINT16 readStrapStatus (void);
+
+void usbInitBeforePciEnum(AMDSBCFG* pConfig);
+void usbInitAfterPciInit(AMDSBCFG* pConfig);
+void usbInitMidPost(AMDSBCFG* pConfig);
+void programOhciMmioForEmulation(void);
+
+void fcInitBeforePciEnum(AMDSBCFG* pConfig);
+
+unsigned char ReadIo8 (IN unsigned short Address);
+unsigned short ReadIo16 (IN unsigned short Address);
+unsigned int ReadIo32 (IN unsigned short Address);
+void WriteIo8 (IN unsigned short Address, IN unsigned char Data);
+void WriteIo16 (IN unsigned short Address, IN unsigned short Data);
+void WriteIo32 (IN unsigned short Address, IN unsigned int Data);
+unsigned long long ReadTSC (void);
+void CpuidRead (IN unsigned int Func, IN OUT CPUID_DATA* Data);
+
+#ifndef NO_EC_SUPPORT
+void EnterEcConfig(void);
+void ExitEcConfig(void);
+void ReadEC8(UINT8 Address, UINT8* Value);
+void WriteEC8(UINT8 Address, UINT8* Value);
+void RWEC8(UINT8 Address, UINT8 AndMask, UINT8 OrMask);
+void ecPowerOnInit(BUILDPARAM *pBuildOptPtr, AMDSBCFG *pConfig);
+void ecInitBeforePciEnum(AMDSBCFG* pConfig);
+void ecInitLatePost(AMDSBCFG* pConfig);
+#endif
+UINT8 isEcPresent(void);
+
+void DispatcherEntry(void *pConfig);
+AGESA_STATUS AmdSbDispatcher(void *pConfig);
+void AMDFamily15CpuLdtStopReq(void);
+
+#endif //#ifndef _AMD_SBDEF_H_
diff --git a/src/vendorcode/amd/cimx/sb700/SbMain.c b/src/vendorcode/amd/cimx/sb700/SbMain.c
new file mode 100644
index 0000000..7468eb2
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/SbMain.c
@@ -0,0 +1,289 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+#ifndef B1_IMAGE
+
+BUILDPARAM DfltStaticOptions={
+ BIOS_SIZE, // BIOS Size
+ LEGACY_FREE, // Legacy Free Option
+ 0x00, // Dummy space holder
+
+ 0x00, // ECKbd disable/enable
+ 0x00, // EcChannel0 disable/enable
+ 0x00, // Dummy space holder1
+
+ SMBUS0_BASE_ADDRESS, // Smbus Base Address;
+ SMBUS1_BASE_ADDRESS, // Smbus Base Address;
+ SIO_PME_BASE_ADDRESS, // SIO PME Base Address
+ WATCHDOG_TIMER_BASE_ADDRESS, // Watchdog Timer Base Address
+ SPI_BASE_ADDRESS,
+
+ PM1_EVT_BLK_ADDRESS, // AcpiPm1EvtBlkAddr;
+ PM1_CNT_BLK_ADDRESS, // AcpiPm1CntBlkAddr;
+ PM1_TMR_BLK_ADDRESS, // AcpiPmTmrBlkAddr;
+ CPU_CNT_BLK_ADDRESS, // CpuControlBlkAddr;
+ GPE0_BLK_ADDRESS, // AcpiGpe0BlkAddr;
+ SMI_CMD_PORT, // SmiCmdPortAddr;
+ ACPI_PMA_CNT_BLK_ADDRESS, // AcpiPmaCntBlkAddr;
+
+ EC_LDN5_MAILBOX_ADDRESS,
+ EC_LDN5_IRQ,
+ EC_LDN9_MAILBOX_ADDRESS, // EC LDN9 Mailbox address
+ RESERVED_VALUE,
+ RESERVED_VALUE,
+ RESERVED_VALUE,
+ RESERVED_VALUE,
+
+ HPET_BASE_ADDRESS, // HPET Base address
+
+ SATA_IDE_MODE_SSID,
+ SATA_RAID_MODE_SSID,
+ SATA_RAID5_MODE_SSID,
+ SATA_AHCI_SSID,
+
+ OHCI0_SSID,
+ OHCI1_SSID,
+ EHCI0_SSID,
+ OHCI2_SSID,
+ OHCI3_SSID,
+ EHCI1_SSID,
+ OHCI4_SSID,
+ SMBUS_SSID,
+ IDE_SSID,
+ AZALIA_SSID,
+ LPC_SSID,
+ P2P_SSID,
+};
+
+
+/*********************************************************************************
+*
+* Routine Description: Config SB Before PCI INIT
+*
+* Arguments:
+*
+* pConfig - SBconfiguration
+*
+* Returns:
+*
+* void
+*
+**********************************************************************************/
+void sbBeforePciInit (AMDSBCFG* pConfig){
+ BUILDPARAM *pStaticOptions;
+
+ pStaticOptions = &pConfig->BuildParameters;
+ TRACE((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciInit \n"));
+ commonInitEarlyBoot(pConfig);
+ commonInitEarlyPost(pConfig);
+#ifndef NO_EC_SUPPORT
+ ecInitBeforePciEnum(pConfig);
+#endif
+ usbInitBeforePciEnum(pConfig); // USB POST TIME Only
+ fcInitBeforePciEnum(pConfig); // Preinit flash controller
+ sataInitBeforePciEnum(pConfig); // Init SATA class code and PHY
+ programSubSystemIDs(pConfig, pStaticOptions); // Set subsystem/vendor ID
+
+ TRACE((DMSG_SB_TRACE, "CIMx - Exiting sbBeforePciInit \n"));
+}
+
+
+/*********************************************************************************
+*
+* Routine Description: Config SB After PCI INIT
+*
+* Arguments:
+*
+* pConfig - SBconfiguration
+*
+* Returns: void
+*
+* Reference: atiSbAfterPciInit
+*
+**********************************************************************************/
+void sbAfterPciInit(AMDSBCFG* pConfig){
+ BUILDPARAM *pStaticOptions;
+
+ TRACE((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciInit \n"));
+
+ pStaticOptions = &pConfig->BuildParameters;
+ usbInitMidPost(pConfig); //usb initialization which is required only during post
+ usbInitAfterPciInit(pConfig); // Init USB MMIO
+ sataInitAfterPciEnum(pConfig); // SATA port enumeration
+ azaliaInitAfterPciEnum(pConfig); // Detect and configure High Definition Audio
+
+ TRACE((DMSG_SB_TRACE, "CIMx - Exiting sbAfterPciInit \n"));
+}
+
+
+/*********************************************************************************
+*
+* Routine Description: Config SB during late POST
+*
+* Arguments:
+*
+* pConfig - SBconfiguration
+*
+* Returns: void
+*
+* Reference: atiSbLatePost
+*
+**********************************************************************************/
+void sbLatePost(AMDSBCFG* pConfig){
+ UINT16 dwVar;
+ BUILDPARAM *pStaticOptions;
+ pStaticOptions = &pConfig->BuildParameters;
+ TRACE((DMSG_SB_TRACE, "CIMx - Entering sbLatePost \n"));
+ ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG02, AccWidthUint16, &dwVar);
+ if (dwVar != SB7XX_DEVICE_ID){
+ // Display message that the SB is wrong and stop the system
+ TRACE((DMSG_SB_TRACE, "Current system does not have SB700 chipset. Stopping\n"));
+ for(;;);
+ }
+ commonInitLateBoot(pConfig);
+ sataInitLatePost(pConfig);
+ hpetInit(pConfig, pStaticOptions); // SB Configure HPET base and enable bit
+#ifndef NO_EC_SUPPORT
+ ecInitLatePost(pConfig);
+#endif
+}
+
+/*********************************************************************************
+*
+* Routine Description: Config SB before ACPI S3 resume PCI config device restore
+*
+* Arguments:
+*
+* pConfig - SBconfiguration
+*
+* Returns: void
+*
+* Reference: AtiSbBfPciRestore
+*
+**********************************************************************************/
+void sbBeforePciRestoreInit(AMDSBCFG* pConfig){
+ BUILDPARAM *pStaticOptions;
+
+ TRACE((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciRestoreInit \n"));
+
+ pConfig->S3Resume = 1;
+
+ pStaticOptions = &pConfig->BuildParameters;
+ commonInitEarlyBoot(pConfig); // set /SMBUS/ACPI/IDE/LPC/PCIB
+ abLinkInitBeforePciEnum(pConfig); // Set ABCFG registers
+ usbInitBeforePciEnum(pConfig); // USB POST TIME Only
+ fcInitBeforePciEnum(pConfig); // Preinit flash controller
+ sataInitBeforePciEnum(pConfig);
+ programSubSystemIDs(pConfig, pStaticOptions); // Set subsystem/vendor ID
+}
+
+
+/*********************************************************************************
+*
+* Routine Description: Config SB after ACPI S3 resume PCI config device restore
+*
+* Arguments:
+*
+* pConfig - SBconfiguration
+*
+* Returns: void
+*
+* Reference: AtiSbAfPciRestore
+*
+**********************************************************************************/
+void sbAfterPciRestoreInit(AMDSBCFG* pConfig){
+ BUILDPARAM *pStaticOptions;
+
+ pConfig->S3Resume = 1;
+
+ pStaticOptions = &pConfig->BuildParameters;
+ TRACE((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciRestoreInit \n"));
+
+ commonInitLateBoot(pConfig);
+ sataInitAfterPciEnum(pConfig);
+ azaliaInitAfterPciEnum(pConfig); // Detect and configure High Definition Audio
+ hpetInit(pConfig, pStaticOptions); // SB Configure HPET base and enable bit
+ sataInitLatePost(pConfig);
+ sbSmmAcpiOn(pConfig);
+}
+
+
+/*++
+
+Routine Description:
+
+ SB config hook during ACPI_ON
+
+Arguments:
+
+ pConfig - SBconfiguration
+
+Returns:
+
+ void
+
+--*/
+
+void sbSmmAcpiOn(AMDSBCFG* pConfig){
+ UINT32 ddBar5;
+ UINT8 dbPort;
+
+ //RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+2, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT1+BIT0), 0);
+ if (getRevisionID() >= SB700_A13)
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); //Enable Legacy DMA prefetch enhancement
+
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+2, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT1+BIT0), 0);
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64+3, AccWidthUint8| S3_SAVE, ~(UINT32)BIT7, 0);
+ programOhciMmioForEmulation();
+
+ // For IDE_TO_AHCI_MODE and IDE_TO_AMD_AHCI_MODE, clear Interrupt Status register for all ports
+ ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5);
+ if ((pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE)){
+ for (dbPort = 0; dbPort <= 5; dbPort++) {
+ RWMEM(ddBar5 + SB_SATA_BAR5_REG110 + dbPort * 0x80, AccWidthUint32, 0x00, 0xFFFFFFFF);
+ }
+ }
+}
+
+
+UINT32 CallBackToOEM(UINT32 Func, UINTN Data,AMDSBCFG* pConfig){
+ UINT32 Result=0;
+ TRACE((DMSG_SB_TRACE,"OEM Call Back Func [%x] Data [%x]\n",Func,Data));
+ if (pConfig->StdHeader.pCallBack==NULL)
+ return Result;
+ Result = (*(pConfig->StdHeader.pCallBack))(Func,Data,pConfig);
+ TRACE((DMSG_SB_TRACE,"SB Hook Status [%x]\n",Result));
+ return Result;
+}
+
+#endif
diff --git a/src/vendorcode/amd/cimx/sb700/SbPort.c b/src/vendorcode/amd/cimx/sb700/SbPort.c
new file mode 100644
index 0000000..6c5740b
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/SbPort.c
@@ -0,0 +1,441 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+REG8MASK sbPorInitPciTable[] = {
+ // SMBUS Device(Bus 0, Dev 20, Func 0)
+ {0x00, SMBUS_BUS_DEV_FUN, 0},
+ {SB_SMBUS_REGD0+2, 0x00, 0x01},
+ {SB_SMBUS_REG40, 0x00, 0x44},
+ {SB_SMBUS_REG40+1, 0xFF, 0xE9}, //Set smbus pci config 0x40[14]=1, This bit is used for internal bus flow control.
+ {SB_SMBUS_REG64, 0x00, 0xBF}, //SB_SMBUS_REG64[13]=1, delays back to back interrupts to the CPU
+ {SB_SMBUS_REG64+1, 0x00, 0x78},
+ {SB_SMBUS_REG64+2, ~(UINT8)BIT6, 0x9E},
+ {SB_SMBUS_REG64+3, 0x0F, 0x02},
+ {SB_SMBUS_REG68+1, 0x00, 0x90},
+ {SB_SMBUS_REG6C, 0x00, 0x20},
+ {SB_SMBUS_REG78, 0x00, 0xFF},
+ {SB_SMBUS_REG04, 0x00, 0x07},
+ {SB_SMBUS_REG04+1, 0x00, 0x04},
+ {SB_SMBUS_REGE1, 0x00, 0x99}, //RPR recommended setting, Sections "SMBUS Pci Config" & "IMC Access Control"
+ {SB_SMBUS_REGAC, ~(UINT8)BIT4, BIT1},
+ {SB_SMBUS_REG60+2, ~(UINT8)(BIT1+BIT0) , 0x24}, // Disabling Legacy USB Fast SMI# Smbus_PCI_config 0x62 [5] = 1. Legacy USB
+ // can request SMI# to be sent out early before IO completion.
+ // Some applications may have problems with this feature. The BIOS should set this bit
+ // to 1 to disable the feature. Enabling Legacy Interrupt Smbus_PCI_Config 0x62[2]=1.
+ {0xFF, 0xFF, 0xFF},
+
+ // LPC Device(Bus 0, Dev 20, Func 3)
+ {0x00, LPC_BUS_DEV_FUN, 0},
+ {SB_LPC_REG40, 0x00, 0x04},
+ {SB_LPC_REG48, 0x00, 0x07},
+ {SB_LPC_REG4A, 0x00, 0x20}, // Port Enable for IO Port 80h.
+ {SB_LPC_REG78, ~(UINT8)BIT0, 0x00},
+ {SB_LPC_REG7C, 0x00, 0x05},
+ {SB_LPC_REGB8+3, ~(UINT8)BIT0, BIT7+BIT6+BIT5+BIT3+BIT0}, //RPR recommended setting,Section "IO / Mem Decoding" & "SPI bus"
+ {0xFF, 0xFF, 0xFF},
+
+ // P2P Bridge(Bus 0, Dev 20, Func 4)
+ {0x00, SBP2P_BUS_DEV_FUN, 0},
+ {SB_P2P_REG40, 0x00, 0x26}, // Enabling PCI-bridge subtractive decoding & PCI Bus 64-byte DMA Read Access
+ {SB_P2P_REG4B, 0xFF, BIT6+BIT7+BIT4},
+ {SB_P2P_REG1C, 0x00, 0x11},
+ {SB_P2P_REG1D, 0x00, 0x11},
+ {SB_P2P_REG04, 0x00, 0x21},
+ {SB_P2P_REG50, 0x02, 0x01}, // PCI Bridge upstream dual address window
+ {0xFF, 0xFF, 0xFF},
+};
+
+
+REG8MASK sbA13PorInitPciTable[] = {
+ // SMBUS Device(Bus 0, Dev 20, Func 0)
+ {0x00, SMBUS_BUS_DEV_FUN, 0},
+ {SB_SMBUS_REG43, ~(UINT8)BIT3, 0x00}, //Make some hidden registers of smbus visible.
+ {SB_SMBUS_REG38, (UINT8)~BIT7, 00},
+ {SB_SMBUS_REGAC+1, ~(UINT8)BIT5, 0}, //Enable SATA test/enhancement mode
+ {SB_SMBUS_REG43, 0xFF, BIT3}, //Make some hidden registers of smbus invisible.
+ {0xFF, 0xFF, 0xFF},
+};
+
+
+REG8MASK sbA14PorInitPciTable[] = {
+ // LPC Device(Bus 0, Dev 20, Func 3)
+ {0x00, LPC_BUS_DEV_FUN, 0},
+ {SB_LPC_REG8C+2, ~(UINT8)BIT1, 00},
+ {0xFF, 0xFF, 0xFF},
+};
+
+REG8MASK sbPorPmioInitTbl[] = {
+ // index andmask ormask
+ {SB_PMIO_REG67, 0xFF, 0x02},
+ {SB_PMIO_REG37, 0xFF, 0x04}, // Configure pciepme as rising edge
+ {SB_PMIO_REG50, 0x00, 0xE0}, // Enable CPU_STP (except S5) & PCI_STP
+ {SB_PMIO_REG60, 0xFF, 0x20}, // Enable Speaker
+ {SB_PMIO_REG65, (UINT8)~(BIT4+BIT7), 0x00},// Clear PM_IO 0x65[4] UsbResetByPciRstEnable to avoid S3 reset to reset USB
+ {SB_PMIO_REG55, ~(UINT8)BIT6, 0x07}, // Select CIR wake event to ACPI.GEVENT[23] & Clear BIT6 SoftPciRst for safety
+ {SB_PMIO_REG66, 0xFF, BIT5}, // Configure keyboard reset to generate pci reset
+ {SB_PMIO_REGB2, 0xFF, BIT7},
+ {SB_PMIO_REG0E, 0xFF, BIT3}, // Enable ACPI IO decoding
+ {SB_PMIO_REGD7, 0xF6, 0x80},
+ {SB_PMIO_REG7C, 0xFF, BIT4}, // enable RTC AltCentury register
+
+ {SB_PMIO_REG75, 0xC0, 0x05}, // PME_TURN_OFF_MSG during ASF shutdown
+ {SB_PMIO_REG52, 0xC0, 0x08},
+
+ {SB_PMIO_REG8B, 0x00, 0x10},
+ {SB_PMIO_REG69, 0xF9, 0x01 << 1}, // [Updated RPR] Set default WDT resolution to 10ms
+};
+
+REG8MASK sbA13PorPmioInitTbl[]={
+ // index andmask ormask
+ {SB_PMIO_REGD7, 0xFF, BIT5+BIT0}, //Fixes for TT SB00068 & SB01054 (BIT5 & BIT0 correspondingly)
+ {SB_PMIO_REGBB, (UINT8)~BIT7, BIT6+BIT5}, //Fixes for TT SB00866 & SB00696 (BIT6 & BIT5 correspondingly)
+ // Always clear [7] to begin with SP5100 C1e disabled
+
+// {SB_PMIO_REG65, 0xFF, BIT7},
+// {SB_PMIO_REG75, 0xC0, 0x01}, // PME_TURN_OFF_MSG during ASF shutdown
+// {SB_PMIO_REG52, 0xC0, 0x02},
+
+};
+
+
+void sbPowerOnInit (AMDSBCFG *pConfig){
+ UINT8 dbVar0, dbVar1, dbValue;
+ UINT16 dwTempVar;
+ BUILDPARAM *pBuildOptPtr;
+
+ TRACE((DMSG_SB_TRACE, "CIMx - Entering sbPowerOnInit \n"));
+
+ setRevisionID();
+ ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, &dwTempVar);
+ if (dwTempVar == SB750_SATA_DEFAULT_DEVICE_ID)
+ RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint8 | S3_SAVE, 0xFF, 0x01);
+
+ // Set A-Link bridge access address. This address is set at device 14h, function 0,
+ // register 0f0h. This is an I/O address. The I/O address must be on 16-byte boundry.
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGF0, AccWidthUint32, 00, ALINK_ACCESS_INDEX);
+
+ writeAlink(0x80000004, 0x04); // RPR 3.3 Enabling upstream DMA Access
+ writeAlink(0x30, 0x10); //AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform.
+ writeAlink(0x34, readAlink(0x34) | BIT9);
+
+ if (!(pConfig->ResetCpuOnSyncFlood)){
+ //Enable reset on sync flood
+ writeAlink( (UINT32)( ((UINT32)SB_AB_REG10050) | ((UINT32)ABCFG << 30)),
+ (UINT32)( readAlink((((UINT32)SB_AB_REG10050) | ((UINT32)ABCFG << 30))) | ((UINT32)BIT2) ));
+ }
+
+ pBuildOptPtr = &(pConfig->BuildParameters);
+
+ WritePCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG90, AccWidthUint32 | S3_SAVE, &(pBuildOptPtr->Smbus0BaseAddress) );
+
+ dwTempVar = pBuildOptPtr->Smbus1BaseAddress & (UINT16)~BIT0;
+ if( dwTempVar != 0 ){
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG58, AccWidthUint16 | S3_SAVE, 00, (dwTempVar|BIT0));
+ // Disable ASF Slave controller on SB700 rev A15.
+ if (getRevisionID() == SB700_A15) {
+ RWIO((dwTempVar+0x0D), AccWidthUint8, (UINT8)~BIT6, BIT6);
+ }
+ }
+
+ WritePCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pBuildOptPtr->SioPmeBaseAddress));
+ RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F,(pBuildOptPtr->SpiRomBaseAddress));
+
+ WritePMIO(SB_PMIO_REG20, AccWidthUint16, &(pBuildOptPtr->AcpiPm1EvtBlkAddr));
+ WritePMIO(SB_PMIO_REG22, AccWidthUint16, &(pBuildOptPtr->AcpiPm1CntBlkAddr));
+ WritePMIO(SB_PMIO_REG24, AccWidthUint16, &(pBuildOptPtr->AcpiPmTmrBlkAddr));
+ WritePMIO(SB_PMIO_REG26, AccWidthUint16, &(pBuildOptPtr->CpuControlBlkAddr));
+ WritePMIO(SB_PMIO_REG28, AccWidthUint16, &(pBuildOptPtr->AcpiGpe0BlkAddr));
+ WritePMIO(SB_PMIO_REG2A, AccWidthUint16, &(pBuildOptPtr->SmiCmdPortAddr));
+ WritePMIO(SB_PMIO_REG2C, AccWidthUint16, &(pBuildOptPtr->AcpiPmaCntBlkAddr));
+ RWPMIO(SB_PMIO_REG2E, AccWidthUint16, 0x00,(pBuildOptPtr->SmiCmdPortAddr)+8);
+ WritePMIO(SB_PMIO_REG6C, AccWidthUint32, &(pBuildOptPtr->WatchDogTimerBase));
+
+ //Program power on pci init table
+ programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbPorInitPciTable[0]), sizeof(sbPorInitPciTable)/sizeof(REG8MASK) );
+ //Program power on pmio init table
+ programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sbPorPmioInitTbl[0]), (sizeof(sbPorPmioInitTbl)/sizeof(REG8MASK)) );
+
+ dbValue = 0x00;
+ ReadIO (SB_IOMAP_REGC14, AccWidthUint8, &dbValue);
+ dbValue &= 0xF3;
+ WriteIO (SB_IOMAP_REGC14, AccWidthUint8, &dbValue);
+
+ dbValue = 0x0A;
+ WriteIO (SB_IOMAP_REG70, AccWidthUint8, &dbValue);
+ ReadIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
+ dbValue &= 0xEF;
+ WriteIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
+
+
+ if (getRevisionID() >= SB700_A13){
+ programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbA13PorInitPciTable[0]), sizeof(sbA13PorInitPciTable)/sizeof(REG8MASK) );
+ programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sbA13PorPmioInitTbl[0]), (sizeof(sbA13PorPmioInitTbl)/sizeof(REG8MASK)) );
+ }
+
+ if ((getRevisionID() >= SB700_A14) )
+ programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbA14PorInitPciTable[0]), sizeof(sbA14PorInitPciTable)/sizeof(REG8MASK) );
+
+ if ( (getRevisionID() >= SB700_A14) && ( (pConfig->TimerClockSource == 1) || (pConfig->TimerClockSource == 2) )){
+ ReadPMIO(SB_PMIO_REGD4, AccWidthUint8, &dbVar1);
+ if (!(dbVar1 & BIT6)){
+ RWPMIO(SB_PMIO_REGD4, AccWidthUint8, 0xFF, BIT6);
+ pConfig->RebootRequired=1;
+ }
+ }
+
+ if (getRevisionID() > SB700_A11) {
+ if (pConfig->PciClk5 == 1)
+ RWPMIO(SB_PMIO_REG41, AccWidthUint8, ~(UINT32)BIT1, BIT1); // Enabled PCICLK5 for A12
+ }
+
+ dbVar0 = (pBuildOptPtr->BiosSize + 1) & 7;
+ if (dbVar0 > 4) {
+ dbVar0 = 0;
+ }
+ //KZ [061811]-It's used wrong BIOS SIZE for Coreboot. RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint8 | S3_SAVE, 0x00, 0xF8 << dbVar0);
+
+ if (pConfig->Spi33Mhz)
+ //spi reg0c[13:12] to 01h to run spi 33Mhz in system bios
+ RWMEM((pBuildOptPtr->SpiRomBaseAddress)+SB_SPI_MMIO_REG0C,AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT13+BIT12), BIT12);
+
+ //SB internal spread spectrum settings. A reboot is required if the spread spectrum settings have to be changed
+ //from the existing value.
+ ReadPMIO(SB_PMIO_REG42, AccWidthUint8, &dbVar0);
+ if (pConfig->SpreadSpectrum != (dbVar0 >> 7) )
+ pConfig->RebootRequired = 1;
+ if (pConfig->SpreadSpectrum)
+ RWPMIO(SB_PMIO_REG42, AccWidthUint8, ~(UINT32)BIT7, BIT7);
+ else
+ RWPMIO(SB_PMIO_REG42, AccWidthUint8, ~(UINT32)BIT7, 0);
+
+ if ( !(pConfig->S3Resume) ){
+ //To detect whether internal clock chip is used, do the following procedure
+ //set PMIO_B2[7]=1, then read PMIO_B0[4]; if it is 1, we are strapped to CLKGEN mode.
+ //if it is 0, we are using clock chip on board.
+ RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT7);
+
+ //Do the following programming only for SB700-A11.
+ //1. Set PMIO_B2 [7]=1 and read B0 and B1 and save those values.
+ //2. Set PMIO_B2 [7]=0
+ //3. Write the saved values from step 1, back to B0 and B1.
+ //4. Set PMIO_B2 [6]=1.
+ ReadPMIO(SB_PMIO_REGB0, AccWidthUint16, &dwTempVar);
+ if (getRevisionID() == SB700_A11){
+ RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)BIT7, 00);
+ WritePMIO(SB_PMIO_REGB0, AccWidthUint16, &dwTempVar);
+ RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT6);
+ }
+
+ if (!(dwTempVar & BIT4)){
+ RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)BIT0, 0); //Enable PLL2
+
+ //we are in external clock chip on the board
+ if (pConfig->UsbIntClock == CIMX_OPTION_ENABLED){
+ //Configure usb clock to come from internal PLL
+ RWPMIO(SB_PMIO_REGD2, AccWidthUint8, 0xFF, BIT3); //Enable 48Mhz clock from PLL2
+ RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, BIT4); //Tell USB PHY to use internal 48Mhz clock from PLL2
+ }
+ else{
+ //Configure usb clock to come from external clock
+ RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, 0); //Tell USB PHY to use external 48Mhz clock from PLL2
+ RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, 00); //Disable 48Mhz clock from PLL2
+ }
+ }
+ else{
+ //we are using internal clock chip on this board
+ if (pConfig->UsbIntClock == CIMX_OPTION_ENABLED){
+ //Configure usb clock to come from internal PLL
+ RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, 0); //Enable 48Mhz clock from PLL2
+ RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, BIT4); //Tell USB PHY to use internal 48Mhz clock from PLL2
+ }
+ else{
+ //Configure usb clock to come from external clock
+ RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, 0); //Tell USB PHY to use external 48Mhz clock from PLL2
+ RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, BIT3); //Disable 48Mhz clock from PLL2
+ }
+ }
+
+ ReadPMIO(SB_PMIO_REG43, AccWidthUint8, &dbVar0);
+ RWPMIO(SB_PMIO_REG43, AccWidthUint8, ~(UINT32)(BIT6+BIT5+BIT0), (pConfig->UsbIntClock << 5));
+ //Check whether our usb clock settings changed compared to previous boot, if yes then we need to reboot.
+ if ( (dbVar0 & BIT0) || ( (pConfig->UsbIntClock) != ((dbVar0 & (BIT6+BIT5)) >> 5)) ) pConfig->RebootRequired = 1;
+ }
+
+ if (pBuildOptPtr->LegacyFree) //if LEGACY FREE system
+ RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000);
+ else
+ RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5);
+
+ if ( (getRevisionID() == SB700_A14) || (getRevisionID() == SB700_A13)){
+ RWPMIO(SB_PMIO_REG65, AccWidthUint8, 0xFF, BIT7);
+ RWPMIO(SB_PMIO_REG75, AccWidthUint8, 0xC0, BIT0);
+ RWPMIO(SB_PMIO_REG52, AccWidthUint8, 0xC0, BIT1);
+ }
+
+ if (getRevisionID() >= SB700_A15) {
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40+3, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT3), 0);
+ //Enable unconditional shutdown fix in A15
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG38+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT4);
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40+3, AccWidthUint8 | S3_SAVE, 0xFF, BIT3);
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG06+1, AccWidthUint8 | S3_SAVE, 0xFF, 0xD0);
+ }
+
+ // [Updated RPR] Set ImcHostSmArbEn(SMBUS:0xE1[5]) only when IMC is enabled
+ if (isEcPresent()) {
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGE1, AccWidthUint8 | S3_SAVE, 0xFF, BIT5);
+ }
+
+ //According to AMD Family 15h Models 00h-0fh processor BKDG section 2.12.8 LDTSTOP requirement
+ // to program VID/FID LDTSTP# duration selection register
+ AMDFamily15CpuLdtStopReq();
+
+#ifndef NO_EC_SUPPORT
+ ecPowerOnInit(pBuildOptPtr, pConfig);
+#endif
+}
+
+
+void setRevisionID(void){
+ UINT8 dbVar0, dbVar1;
+
+ ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0);
+ ReadPMIO(SB_PMIO_REG53, AccWidthUint8, &dbVar1);
+ if ( (dbVar0 == 0x39) && (dbVar1 & BIT6) && !(dbVar1 & BIT7)){
+ RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40), AccWidthUint8, ~(UINT32)BIT0, BIT0);
+ RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, 00, SB700_A12);
+ RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40), AccWidthUint8, ~(UINT32)BIT0, 00);
+ }
+ ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0);
+}
+
+
+UINT8 getRevisionID(void){
+ UINT8 dbVar0;
+
+ ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0);
+ return dbVar0;
+}
+
+
+void AMDFamily15CpuLdtStopReq(void) {
+ CPUID_DATA CpuId;
+ CPUID_DATA CpuId_Brand;
+ UINT8 dbVar0, dbVar1, dbVar2;
+
+ //According to AMD Family 15h Models 00h-0fh processor BKDG section 2.12.8 LDTSTOP requirement
+ //to program VID/FID LDTSTP# duration selection register
+ //If any of the following system configuration properties are true LDTSTP# assertion time required by the processor is 10us:
+ // 1. Any link in the system operating at a Gen 1 Frequency.
+ // 2. Also for server platform (G34/C32) set PM_REG8A[6:4]=100b (16us)
+
+ CpuidRead (0x01, &CpuId);
+ CpuidRead (0x80000001, &CpuId_Brand); //BrandID, to read socket type
+ if ((CpuId.REG_EAX & 0xFFFFFF00) == 0x00600F00) {
+
+ //Program to Gen 3 default value - 001b
+ RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x10); //set [6:4]=001b
+
+ //Any link in the system operating at a Gen 1 Frequency.
+ //Check Link 0 - Link connected regsister
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG98), AccWidthUint8, &dbVar2);
+ dbVar2 = dbVar2 & 0x01;
+
+ if(dbVar2 == 0x01) {
+ //Check Link 0 - Link Frequency Freq[4:0]
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG89), AccWidthUint8, &dbVar0);
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG9C), AccWidthUint8, &dbVar1);
+ dbVar0 = dbVar0 & 0x0F; //Freq[3:0]
+ dbVar1 = dbVar1 & 0x01; //Freq[4]
+ dbVar0 = (dbVar1 << 4) | dbVar0; //Freq[4:0]
+ //Value 6 or less indicate Gen1
+ if(dbVar0 <= 0x6) {
+ RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b
+ }
+ }
+
+ //Check Link 1 - Link connected regsister
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGB8), AccWidthUint8, &dbVar2);
+ dbVar2 = dbVar2 & 0x01;
+ if(dbVar2 == 0x01) {
+ //Check Link 1 - Link Frequency Freq[4:0]
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGA9), AccWidthUint8, &dbVar0);
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGBC), AccWidthUint8, &dbVar1);
+ dbVar0 = dbVar0 & 0x0F; //Freq[3:0]
+ dbVar1 = dbVar1 & 0x01; //Freq[4]
+ dbVar0 = (dbVar1 << 4) | dbVar0; //Freq[4:0]
+ //Value 6 or less indicate Gen1
+ if(dbVar0 <= 0x6) {
+ RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b
+ }
+ }
+
+ //Check Link 2 - Link connected regsister
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGD8), AccWidthUint8, &dbVar2);
+ dbVar2 = dbVar2 & 0x01;
+ if(dbVar2 == 0x01) {
+ //Check Link 2 - Link Frequency Freq[4:0]
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGC9), AccWidthUint8, &dbVar0);
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGDC), AccWidthUint8, &dbVar1);
+ dbVar0 = dbVar0 & 0x0F; //Freq[3:0]
+ dbVar1 = dbVar1 & 0x01; //Freq[4]
+ dbVar0 = (dbVar1 << 4) | dbVar0; //Freq[4:0]
+ //Value 6 or less indicate Gen1
+ if(dbVar0 <= 0x6) {
+ RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b
+ }
+ }
+
+ //Check Link 3 - Link connected regsister
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGF8), AccWidthUint8, &dbVar2);
+ dbVar2 = dbVar2 & 0x01;
+ if(dbVar2 == 0x01) {
+ //Check Link 3 - Link Frequency Freq[4:0]
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGE9), AccWidthUint8, &dbVar0);
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGFC), AccWidthUint8, &dbVar1);
+ dbVar0 = dbVar0 & 0x0F; //Freq[3:0]
+ dbVar1 = dbVar1 & 0x01; //Freq[4]
+ dbVar0 = ((dbVar1 << 4) | dbVar0); //Freq[4:0]
+ //Value 6 or less indicate Gen1
+ if(dbVar0 <= 0x6) {
+ RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b
+ }
+ }
+
+ // Server platform (G34/C32) set PM_REG8A[6:4]=100b (16us)
+ if(((CpuId_Brand.REG_EBX & 0xF0000000) == 0x30000000) || ((CpuId_Brand.REG_EBX & 0xF0000000) == 0x50000000)) {
+ RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b
+ }
+ }
+
+}
+
diff --git a/src/vendorcode/amd/cimx/sb700/SbType.h b/src/vendorcode/amd/cimx/sb700/SbType.h
new file mode 100644
index 0000000..faeae5d
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/SbType.h
@@ -0,0 +1,249 @@
+/*;********************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; * Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; * Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; * Neither the name of Advanced Micro Devices, Inc. nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*********************************************************************************/
+
+#ifndef _AMD_SBTYPE_H_
+#define _AMD_SBTYPE_H_
+
+#pragma pack(push,1)
+
+typedef UINT32 (*CIM_HOOK_ENTRY)(UINT32 Param1, UINTN Param2, void* pConfig);
+typedef void (*SMM_SERVICE_ROUTINE) (void);
+
+typedef struct _STDCFG{
+ UINT32 pImageBase;
+ UINT32 pPcieBase;
+ UINT8 Func;
+ CIM_HOOK_ENTRY pCallBack;
+ UINT32 pB2ImageBase;
+}STDCFG; //Size of stdcfg is 17 bytes
+
+typedef struct _BUILDPARAM
+{
+ UINT16 BiosSize:3; //0-1MB, 1-2MB, 2-4MB, 3-8MB, 7-512KB, all other values reserved
+ UINT16 LegacyFree:1;
+ UINT16 Dummy0:12;
+
+ UINT16 EcKbd:1;
+ UINT16 EcChannel0:1;
+ UINT16 Dummy1:14;
+
+ UINT32 Smbus0BaseAddress;
+ UINT16 Smbus1BaseAddress;
+ UINT32 SioPmeBaseAddress;
+ UINT32 WatchDogTimerBase;
+ UINT32 SpiRomBaseAddress;
+
+ UINT16 AcpiPm1EvtBlkAddr;
+ UINT16 AcpiPm1CntBlkAddr;
+ UINT16 AcpiPmTmrBlkAddr;
+ UINT16 CpuControlBlkAddr;
+ UINT16 AcpiGpe0BlkAddr;
+ UINT16 SmiCmdPortAddr;
+ UINT16 AcpiPmaCntBlkAddr;
+
+ UINT16 EcLdn5MailBoxAddr;
+ UINT8 EcLdn5Irq;
+ UINT16 EcLdn9MailBoxAddr;
+ UINT32 ReservedDword0;
+ UINT32 ReservedDword1;
+ UINT32 ReservedDword2;
+ UINT32 ReservedDword3;
+
+ UINT32 HpetBase; //HPET Base address
+
+ UINT32 SataIDESsid;
+ UINT32 SataRAIDSsid;
+ UINT32 SataRAID5Ssid;
+ UINT32 SataAHCISsid;
+
+ UINT32 Ohci0Ssid;
+ UINT32 Ohci1Ssid;
+ UINT32 Ehci0Ssid;
+ UINT32 Ohci2Ssid;
+ UINT32 Ohci3Ssid;
+ UINT32 Ehci1Ssid;
+ UINT32 Ohci4Ssid;
+ UINT32 SmbusSsid;
+ UINT32 IdeSsid;
+ UINT32 AzaliaSsid;
+ UINT32 LpcSsid;
+ UINT32 P2PSsid;
+}BUILDPARAM;
+
+typedef struct _CODECENTRY{
+ UINT8 Nid;
+ UINT32 Byte40;
+}CODECENTRY;
+
+typedef struct _CODECTBLLIST{
+ UINT32 CodecID;
+ CODECENTRY* CodecTablePtr;
+}CODECTBLLIST;
+
+typedef struct _AMDSBCFG
+{
+ STDCFG StdHeader; //offset 0:16 - 17 bytes
+ //UINT32 MsgXchgBiosCimx; //offset 17:20 - 4 bytes
+ UINT32 S3Resume:1;
+ UINT32 RebootRequired:1;
+ UINT32 Spi33Mhz:1;
+ UINT32 SpreadSpectrum:1;
+ UINT32 UsbIntClock:1; //0:Use external clock, 1:Use internal clock
+ UINT32 PciClk5:1; //0:disable, 1:enable
+ UINT32 TimerClockSource:2; //0:100Mhz PCIE Reference clock (same as SB700-A12,
+ //1: 14Mhz using 25M_48M_66M_OSC pin, 2: Auto (100Mhz for SB700-A12, 14Mhz
+ //using 25M_48m_66m_0SC pin for SB700-A14, SB710, SP5100
+ UINT32 ResetCpuOnSyncFlood:1; //0:Reset CPU on Sync Flood, 1:Do not reset CPU on sync flood
+ UINT32 MsgXchgBiosCimxDummyBB:23;
+
+ /** BuildParameters - The STATIC platform information for CIMx Module. */
+ BUILDPARAM BuildParameters;
+
+ //SATA Configuration
+ UINT32 SataController :1; //0, 0:disable 1:enable* //offset 25:28 - 4 bytes
+ UINT32 SataClass :3; //1, 0:IDE* 1:RAID 2:AHCI 3:Legacy IDE 4:IDE->AHCI 5:AMD_AHCI, 6:IDE->AMD_AHCI
+ UINT32 SataSmbus :1; //4, 0:disable 1:enable*
+ UINT32 SataAggrLinkPmCap:1; //5, 0:OFF 1:ON
+ UINT32 SataPortMultCap :1; //6, 0:OFF 1:ON
+ UINT32 SataReserved :2; //8:7, Reserved
+ UINT32 SataClkAutoOff :1; //9, AutoClockOff for IDE modes 0:Disabled, 1:Enabled
+ UINT32 SataIdeCombinedMode :1; //10, SataIDECombinedMode 0:Disabled, 1:Enabled
+ UINT32 SataIdeCombMdPriSecOpt:1; //11, Combined Mode, SATA as primary or secondary 0:primary 1:secondary
+ UINT32 SataReserved1 :6; //17:12, Not used currently
+ UINT32 SataEspPort :6; //23:18 SATA port is external accessiable on a signal only connector (eSATA:)
+ UINT32 SataClkAutoOffAhciMode:1; //24: Sata Auto clock off for AHCI mode
+ UINT32 SataHpcpButNonESP:6; //25:30 Hotplug capable but not e-sata port
+ UINT32 SataHideUnusedPort:1; //31, 0:Disabled 1:Enabled
+
+ //Flash Configuration //offset 29:30 - 2 bytes
+ UINT16 FlashController :1; //0, 0:disable FC & enable IDE 1:enable FC & disable IDE
+ UINT16 FlashControllerMode:1; //1, 0:Flash behind SATA 1:Flash as standalone
+ UINT16 FlashHcCrc:1; //2,
+ UINT16 FlashErrorMode:1; //3
+ UINT16 FlashNumOfBankMode:1; //4
+ UINT16 FlashDummy:11; //5:15
+
+ //USB Configuration //offset 31:32 - 2 bytes
+ UINT16 Usb1Ohci0 :1; //0, 0:disable 1:enable* Bus 0 Dev 18 Func0
+ UINT16 Usb1Ohci1 :1; //1, 0:disable 1:enable* Bus 0 Dev 18 Func1
+ UINT16 Usb1Ehci :1; //2, 0:disable 1:enable* Bus 0 Dev 18 Func2
+ UINT16 Usb2Ohci0 :1; //3, 0:disable 1:enable* Bus 0 Dev 19 Func0
+ UINT16 Usb2Ohci1 :1; //4, 0:disable 1:enable* Bus 0 Dev 19 Func1
+ UINT16 Usb2Ehci :1; //5, 0:disable 1:enable* Bus 0 Dev 19 Func2
+ UINT16 Usb3Ohci :1; //6, 0:disable 1:enable* Bus 0 Dev 20 Func5
+ UINT16 UsbOhciLegacyEmulation:1; //7, 0:Enabled, 1:Disabled
+ UINT16 UsbDummy :8; //8:15
+
+ //Azalia Configuration //offset 33:36 - 4 bytes
+ UINT32 AzaliaController:2; //0, 0:AUTO, 1:disable, 2:enable
+ UINT32 AzaliaPinCfg :1; //2, 0:disable, 1:enable
+ UINT32 AzaliaFrontPanel:2; //3, 0:AUTO, 1:disable, 2:enable
+ UINT32 FrontPanelDetected:1; //5, 0:Not detected, 1:detected
+ UINT32 AzaliaSdin0 :2; //6
+ UINT32 AzaliaSdin1 :2; //8
+ UINT32 AzaliaSdin2 :2; //10
+ UINT32 AzaliaSdin3 :2; //12
+ UINT32 AzaliaDummy :18; //14:31
+
+ CODECTBLLIST* pAzaliaOemCodecTablePtr; //offset 37:40 - 4 bytes
+ UINT32 pAzaliaOemFpCodecTableptr; //offset 41:44 - 4 bytes
+
+ //Miscellaneous Configuration //offset 45:48 - 4 bytes
+ UINT32 MiscReserved0:1; //0
+ UINT32 HpetTimer:1; //1, 0:disable 1:enable
+ UINT32 PciClks:5; //2:6, 0:disable, 1:enable
+ UINT32 MiscReserved1:3; //9:7, Reserved
+ UINT32 IdeController:1; //10, 0:Enable, 1:Disabled
+ UINT32 MobilePowerSavings:1; //11, 0:Disable, 1:Enable Power saving features especially for Mobile platform
+ UINT32 ExternalRTCClock:1; //12, 0:Don't Shut Off, 1:Shut Off, external RTC clock
+ UINT32 AcpiS1Supported:1; //13, 0:S1 not supported, 1:S1 supported
+ UINT32 AnyHT200MhzLink:1; //14, 0:No HT 200Mhz Link in platform, 1; There is 200MHz HT Link in platform
+ UINT32 WatchDogTimerEnable:1; //15, [0]: WDT disabled; 1: WDT enabled
+ UINT32 MTC1e:1; //16, Message Triggered C1e - 0:Disabled*, 1:Enabled
+ UINT32 HpetMsiDis:1; //17, HPET MSI - 0:Enable HPET MSI, 1:Disable
+ UINT32 EhciDataCacheDis:1; //18, 0:Date Cache Enabled, 1:Date Cache Disabled /** EHCI Async Data Cache Disable */
+ UINT32 MiscDummy:13;
+
+ UINT32 AsmAslInfoExchange0; //offset 49:52 - 4 bytes
+ UINT32 AsmAslInfoExchange1; //offset 53:56
+
+ //DebugOptions_1 //offset 57:60
+ UINT32 FlashPinConfig :1; //0, 0:desktop mode 1:mobile mode
+ UINT32 UsbPhyPowerDown :1; //1
+ UINT32 PcibClkStopOverride :10; //11:2
+ UINT32 Debug1Reserved0:4; //15:11
+ UINT32 AzaliaSnoop:1; //16 0:Disable, 1:Enable
+ UINT32 SataSscPscCap:1; //17, 0:Enable SSC/PSC capability, 1:Disable SSC/PSC capability
+ UINT32 SataPortMode:6; //23:18, 0: AUTO, 1:Force SATA port(6/5/4/3/2/1) to GEN1
+ UINT32 SataPhyWorkaround:2; //25:24, 0:AUTO, 1:Enable, 2:Disable
+ UINT32 Gen1DeviceShutdownDuringPhyWrknd:2; //27:26, 0:AUTO, 1:YES, 2:NO
+ UINT32 OhciIsoOutPrefetchDis:1; //28, 0:Enable OHCI ISO OUT prefetch, 1:Disable
+ UINT32 Debug1Dummy:3; //
+
+ //DebugOptions_2
+ UINT32 PcibAutoClkCtrlLow:16;
+ UINT32 PcibAutoClkCtrlHigh:16;
+
+ //TempMMIO
+ UINT32 TempMMIO:32;
+
+}AMDSBCFG;
+
+typedef struct _SMMSERVICESTRUC
+{
+ UINT8 enableRegNum;
+ UINT8 enableBit;
+ UINT8 statusRegNum;
+ UINT8 statusBit;
+ CHAR8 *debugMessage;
+ SMM_SERVICE_ROUTINE serviceRoutine;
+}SMMSERVICESTRUC;
+
+typedef struct _ABTblEntry
+{
+ UINT8 regType;
+ UINT32 regIndex;
+ UINT32 regMask;
+ UINT32 regData;
+}ABTBLENTRY;
+
+#define PCI_ADDRESS(bus,dev,func,reg) \
+(UINT32) ( (((UINT32)bus) << 24) + (((UINT32)dev) << 19) + (((UINT32)func) << 16) + ((UINT32)reg) )
+
+typedef UINT32 CIM_STATUS;
+#define CIM_SUCCESS 0x00000000
+#define CIM_ERROR 0x80000000
+#define CIM_UNSUPPORTED 0x80000001
+
+#pragma pack(pop)
+
+#define CIMX_OPTION_DISABLED 0
+#define CIMX_OPTION_ENABLED 1
+
+#endif // _AMD_SBTYPE_H_
diff --git a/src/vendorcode/amd/cimx/sb700/Smm.c b/src/vendorcode/amd/cimx/sb700/Smm.c
new file mode 100644
index 0000000..0d752fb
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/Smm.c
@@ -0,0 +1,91 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+SMMSERVICESTRUC smmItemsTable[]={
+ {SB_PMIO_REG0E, BIT2, SB_PMIO_REG0F, BIT2, (CHAR8 *)"Software SMI through SMI CMD port \n ", softwareSMIservice},
+ {SB_PMIO_REG00, BIT4, SB_PMIO_REG01, BIT4, (CHAR8 *)"Software initiated SMI \n ", NULL},
+ {SB_PMIO_REG02, 0xFF, SB_PMIO_REG05, 0xFF, (CHAR8 *)"SMI on IRQ15-8 \n ", NULL},
+ {SB_PMIO_REG03, 0xFF, SB_PMIO_REG06, 0xFF, (CHAR8 *)"SMI on IRQ7-0 \n ", NULL},
+ {SB_PMIO_REG04, 0xFF, SB_PMIO_REG07, 0xFF, (CHAR8 *)"SMI on legacy devices activity(Serial, FDD etc) \n ", NULL},
+ {SB_PMIO_REG1C, 0xFF, SB_PMIO_REG1D, 0xFF, (CHAR8 *)"SMI on PIO 0123 \n ", NULL},
+ {SB_PMIO_REGA8, 0x0F, SB_PMIO_REGA9, 0xFF, (CHAR8 *)"SMI on PIO 4567 \n ", NULL},
+};
+
+
+/*++
+
+Routine Description:
+
+ SB SMI service
+
+Arguments:
+
+ pConfig - SBconfiguration
+
+Returns:
+
+ void
+
+--*/
+
+void sbSmmService(AMDSBCFG* pConfig){
+ UINT8 i, dbEnableValue, dbStatusValue;
+ SMMSERVICESTRUC *pSmmItems;
+ SMM_SERVICE_ROUTINE serviceRoutine;
+
+ pSmmItems = (SMMSERVICESTRUC *)FIXUP_PTR(&smmItemsTable[0]);
+ TRACE((DMSG_SB_TRACE, "CIMx - Entering SMM services \n"));
+ for (i = 1; i <= (sizeof(smmItemsTable)/sizeof(SMMSERVICESTRUC)); i++){
+ dbEnableValue = pSmmItems->enableRegNum;
+ ReadPMIO(pSmmItems->enableRegNum, AccWidthUint8, &dbEnableValue);
+ ReadPMIO(pSmmItems->statusRegNum, AccWidthUint8, &dbStatusValue);
+ if ( (dbEnableValue & (pSmmItems->enableBit)) && (dbStatusValue & (pSmmItems->statusBit)) ){
+ TRACE((DMSG_SB_TRACE, "\n \nSmi source is: %s \n", pSmmItems->debugMessage));
+ TRACE((DMSG_SB_TRACE, "Enable Reg:%d Value:%d\n", pSmmItems->enableRegNum, dbEnableValue));
+ TRACE((DMSG_SB_TRACE, "Status Reg:%d Value:%d\n\n", pSmmItems->statusRegNum, dbStatusValue));
+ if ( (pSmmItems->serviceRoutine)!= NULL){
+ serviceRoutine = (void *)FIXUP_PTR(pSmmItems->serviceRoutine);
+ serviceRoutine();
+ }
+ }
+ }
+ TRACE((DMSG_SB_TRACE, "CIMx - Exiting SMM services \n"));
+}
+
+
+void softwareSMIservice(void){
+ UINT16 dwSmiCmdPort, dwVar;
+ ReadPMIO(SB_PMIO_REG2A, AccWidthUint16, &dwSmiCmdPort);
+ ReadIO(dwSmiCmdPort, AccWidthUint16, &dwVar);
+ TRACE((DMSG_SB_TRACE, "SMI CMD Port Address: %X SMICMD Port value is %X \n", dwSmiCmdPort, dwVar));
+}
diff --git a/src/vendorcode/amd/cimx/sb700/USB.c b/src/vendorcode/amd/cimx/sb700/USB.c
deleted file mode 100644
index 9c5e7b3..0000000
--- a/src/vendorcode/amd/cimx/sb700/USB.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/*****************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *
- ***************************************************************************/
-
-
-#include "Platform.h"
-
-
-void usbInitBeforePciEnum(AMDSBCFG* pConfig){
- UINT8 dbVar=0;
-
- TRACE((DMSG_SB_TRACE, "Entering PreInit Usb \n"));
- if (pConfig->Usb1Ohci0){
- dbVar = (pConfig->Usb1Ehci << 2);
- dbVar |= ((pConfig->Usb1Ohci0) << 0);
- dbVar |= ((pConfig->Usb1Ohci1) << 1);
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG68, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT0+BIT1+BIT2), dbVar );
- }
- if (pConfig->Usb2Ohci0){
- dbVar = (pConfig->Usb2Ehci << 6) ;
- dbVar |= ((pConfig->Usb2Ohci0) << 4);
- dbVar |= ((pConfig->Usb2Ohci1) << 5);
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG68, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT6+BIT4+BIT5), dbVar );
- }
- if (pConfig->Usb3Ohci)
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG68, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT7), ((pConfig->Usb3Ohci) << 7) );
-
- RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50+1, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT4), BIT4);
-}
-
-
-void usbInitAfterPciInit(AMDSBCFG* pConfig){
- UINT32 ddBarAddress, ddVar;
-
- ReadPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address
- if ( (ddBarAddress != -1) && (ddBarAddress != 0) ){
- //Enable Memory access
- RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG04, AccWidthUint8, 0, BIT1);
- //USB Common PHY CAL & Control Register setting
- ddVar = 0x00020F00;
- WriteMEM(ddBarAddress+SB_EHCI_BAR_REGC0, AccWidthUint32, &ddVar);
- //RPR - IN AND OUT DATA PACKET FIFO THRESHOLD
- //EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40 //OUT threshold bits[23:16]=0x40
- RWMEM(ddBarAddress+SB_EHCI_BAR_REGA4, AccWidthUint32, 0xFF00FF00, 0x00400040);
- //RPR - EHCI dynamic clock gating feature
- //EHCI_BAR 0xBC Bit[12] = 0, For normal operation, the clock gating feature must be disabled.
- // Disables HS uFrame babble detection for erratum: EHCI_EOR + 9Ch [11] = 1
- RWMEM(ddBarAddress+SB_EHCI_BAR_REGBC, AccWidthUint16, ~(UINT32)(BIT12+BIT11), BIT11);
- }
-
- ReadPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address
- if ( (ddBarAddress != -1) && (ddBarAddress != 0) ){
- //Enable Memory access
- RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG04, AccWidthUint8, 0, BIT1);
- //USB Common PHY CAL & Control Register setting
- ddVar = 0x00020F00;
- WriteMEM(ddBarAddress+SB_EHCI_BAR_REGC0, AccWidthUint32, &ddVar);
- //RPR - IN AND OUT DATA PACKET FIFO THRESHOLD
- //EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40 //OUT threshold bits[23:16]=0x40
- RWMEM(ddBarAddress+SB_EHCI_BAR_REGA4, AccWidthUint32, 0xFF00FF00, 0x00400040);
- //RPR - EHCI dynamic clock gating feature
- //EHCI_BAR 0xBC Bit[12] = 0, For normal operation, the clock gating feature must be disabled.
- // Disables HS uFrame babble detection for erratum: EHCI_EOR + 9Ch [11] = 1
- RWMEM(ddBarAddress+SB_EHCI_BAR_REGBC, AccWidthUint16, ~(UINT32)(BIT12+BIT11), BIT11);
- }
-
- if (pConfig->UsbPhyPowerDown)
- RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, BIT0);
- else
- RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0);
-
- // Disable the MSI capability of USB host controllers
- RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG40+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0);
- RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG40+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0);
- RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG40+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
-
- //RPR recommended setting "EHCI Advance Asynchronous Enhancement DISABLE"
- //Set EHCI_pci_configx50[28]='1' to disable the advance async enhancement feature to avoid the bug found in Linux.
- //Set EHCI_pci_configx50[6]='1' to disable EHCI MSI support
- //RPR recommended setting "EHCI Async Park Mode"
- //Set EHCI_pci_configx50[23]='1' to disable "EHCI Async Park Mode support"
- // RPR recommended setting "EHCI Advance PHY Power Savings"
- // Set EHCI_pci_configx50[31]='1' if SB700 A12 & above
- // Fix for EHCI controller driver yellow sign issue under device manager
- // when used in conjunction with HSET tool driver. EHCI PCI config 0x50[20]=1
- RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT31+BIT28+BIT23+BIT20+BIT6);
- RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT31+BIT28+BIT23+BIT20+BIT6);
-
- //RPR recommended setting to, enable fix to cover the corner case S3 wake up issue from some USB 1.1 devices
- //OHCI 0_PCI_Config 0x50[16] = 1
- RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
- RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
- RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
-
- if (getRevisionID() >= SB700_A14){
- RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT28), BIT8+BIT7+BIT4+BIT3);
- RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT28), BIT8+BIT7+BIT4+BIT3);
-
- RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT26+BIT25+BIT17);
- RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT26+BIT25+BIT17);
- RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT26+BIT25);
- }
-
- if (getRevisionID() >= SB700_A15) {
- //USB PID Error checking
- RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1);
- RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1);
- }
-
- // RPR 6.25 - Optionally disable OHCI isochronous out prefetch
- if (pConfig->OhciIsoOutPrefetchDis) {
- RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT9 + BIT8), 0);
- RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT9 + BIT8), 0);
- RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT9 + BIT8), 0);
- }
-
- if ( pConfig->EhciDataCacheDis ) {
- // Disable Async Data Cache, EHCI_pci_configx50[26]='1'
- RWPCI ((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)BIT26, BIT26);
- RWPCI ((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)BIT26, BIT26);
- }
-}
-
-
-void usbInitMidPost(AMDSBCFG* pConfig){
- if (pConfig->UsbOhciLegacyEmulation == 0){
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0);
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64+3, AccWidthUint8 | S3_SAVE, 0xFF, BIT7);
- }
- else{
- programOhciMmioForEmulation();
- }
-}
-
-
-void programOhciMmioForEmulation(void){
- UINT32 ddBarAddress;
-
- ReadPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address
- ddBarAddress &= 0xFFFFF000;
- if ( (ddBarAddress != 0xFFFFF000) && (ddBarAddress != 0) ){
- //Enable Memory access
- RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG04, AccWidthUint8, 0, BIT1);
- RWMEM(ddBarAddress+SB_OHCI_BAR_REG160, AccWidthUint32, 0, 0);
- }
-
- ReadPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address
- ddBarAddress &= 0xFFFFF000;
- if ( (ddBarAddress != 0xFFFFF000) && (ddBarAddress != 0) ){
- //Enable Memory access
- RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG04, AccWidthUint8, 0, BIT1);
- RWMEM(ddBarAddress+SB_OHCI_BAR_REG160, AccWidthUint32, 0, 0);
- }
-
- ReadPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address
- if ( (ddBarAddress != 0xFFFFF000) && (ddBarAddress != 0) ){
- //Enable Memory access
- RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG04, AccWidthUint8, 0, BIT1);
- RWMEM(ddBarAddress+SB_OHCI_BAR_REG160, AccWidthUint32, 0, 0);
- }
-}
diff --git a/src/vendorcode/amd/cimx/sb700/Usb.c b/src/vendorcode/amd/cimx/sb700/Usb.c
new file mode 100644
index 0000000..9c5e7b3
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/Usb.c
@@ -0,0 +1,187 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+
+void usbInitBeforePciEnum(AMDSBCFG* pConfig){
+ UINT8 dbVar=0;
+
+ TRACE((DMSG_SB_TRACE, "Entering PreInit Usb \n"));
+ if (pConfig->Usb1Ohci0){
+ dbVar = (pConfig->Usb1Ehci << 2);
+ dbVar |= ((pConfig->Usb1Ohci0) << 0);
+ dbVar |= ((pConfig->Usb1Ohci1) << 1);
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG68, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT0+BIT1+BIT2), dbVar );
+ }
+ if (pConfig->Usb2Ohci0){
+ dbVar = (pConfig->Usb2Ehci << 6) ;
+ dbVar |= ((pConfig->Usb2Ohci0) << 4);
+ dbVar |= ((pConfig->Usb2Ohci1) << 5);
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG68, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT6+BIT4+BIT5), dbVar );
+ }
+ if (pConfig->Usb3Ohci)
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG68, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT7), ((pConfig->Usb3Ohci) << 7) );
+
+ RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50+1, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT4), BIT4);
+}
+
+
+void usbInitAfterPciInit(AMDSBCFG* pConfig){
+ UINT32 ddBarAddress, ddVar;
+
+ ReadPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address
+ if ( (ddBarAddress != -1) && (ddBarAddress != 0) ){
+ //Enable Memory access
+ RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG04, AccWidthUint8, 0, BIT1);
+ //USB Common PHY CAL & Control Register setting
+ ddVar = 0x00020F00;
+ WriteMEM(ddBarAddress+SB_EHCI_BAR_REGC0, AccWidthUint32, &ddVar);
+ //RPR - IN AND OUT DATA PACKET FIFO THRESHOLD
+ //EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40 //OUT threshold bits[23:16]=0x40
+ RWMEM(ddBarAddress+SB_EHCI_BAR_REGA4, AccWidthUint32, 0xFF00FF00, 0x00400040);
+ //RPR - EHCI dynamic clock gating feature
+ //EHCI_BAR 0xBC Bit[12] = 0, For normal operation, the clock gating feature must be disabled.
+ // Disables HS uFrame babble detection for erratum: EHCI_EOR + 9Ch [11] = 1
+ RWMEM(ddBarAddress+SB_EHCI_BAR_REGBC, AccWidthUint16, ~(UINT32)(BIT12+BIT11), BIT11);
+ }
+
+ ReadPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address
+ if ( (ddBarAddress != -1) && (ddBarAddress != 0) ){
+ //Enable Memory access
+ RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG04, AccWidthUint8, 0, BIT1);
+ //USB Common PHY CAL & Control Register setting
+ ddVar = 0x00020F00;
+ WriteMEM(ddBarAddress+SB_EHCI_BAR_REGC0, AccWidthUint32, &ddVar);
+ //RPR - IN AND OUT DATA PACKET FIFO THRESHOLD
+ //EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40 //OUT threshold bits[23:16]=0x40
+ RWMEM(ddBarAddress+SB_EHCI_BAR_REGA4, AccWidthUint32, 0xFF00FF00, 0x00400040);
+ //RPR - EHCI dynamic clock gating feature
+ //EHCI_BAR 0xBC Bit[12] = 0, For normal operation, the clock gating feature must be disabled.
+ // Disables HS uFrame babble detection for erratum: EHCI_EOR + 9Ch [11] = 1
+ RWMEM(ddBarAddress+SB_EHCI_BAR_REGBC, AccWidthUint16, ~(UINT32)(BIT12+BIT11), BIT11);
+ }
+
+ if (pConfig->UsbPhyPowerDown)
+ RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, BIT0);
+ else
+ RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0);
+
+ // Disable the MSI capability of USB host controllers
+ RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG40+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0);
+ RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG40+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0);
+ RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG40+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
+
+ //RPR recommended setting "EHCI Advance Asynchronous Enhancement DISABLE"
+ //Set EHCI_pci_configx50[28]='1' to disable the advance async enhancement feature to avoid the bug found in Linux.
+ //Set EHCI_pci_configx50[6]='1' to disable EHCI MSI support
+ //RPR recommended setting "EHCI Async Park Mode"
+ //Set EHCI_pci_configx50[23]='1' to disable "EHCI Async Park Mode support"
+ // RPR recommended setting "EHCI Advance PHY Power Savings"
+ // Set EHCI_pci_configx50[31]='1' if SB700 A12 & above
+ // Fix for EHCI controller driver yellow sign issue under device manager
+ // when used in conjunction with HSET tool driver. EHCI PCI config 0x50[20]=1
+ RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT31+BIT28+BIT23+BIT20+BIT6);
+ RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT31+BIT28+BIT23+BIT20+BIT6);
+
+ //RPR recommended setting to, enable fix to cover the corner case S3 wake up issue from some USB 1.1 devices
+ //OHCI 0_PCI_Config 0x50[16] = 1
+ RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
+ RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
+ RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
+
+ if (getRevisionID() >= SB700_A14){
+ RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT28), BIT8+BIT7+BIT4+BIT3);
+ RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT28), BIT8+BIT7+BIT4+BIT3);
+
+ RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT26+BIT25+BIT17);
+ RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT26+BIT25+BIT17);
+ RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT26+BIT25);
+ }
+
+ if (getRevisionID() >= SB700_A15) {
+ //USB PID Error checking
+ RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1);
+ RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1);
+ }
+
+ // RPR 6.25 - Optionally disable OHCI isochronous out prefetch
+ if (pConfig->OhciIsoOutPrefetchDis) {
+ RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT9 + BIT8), 0);
+ RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT9 + BIT8), 0);
+ RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT9 + BIT8), 0);
+ }
+
+ if ( pConfig->EhciDataCacheDis ) {
+ // Disable Async Data Cache, EHCI_pci_configx50[26]='1'
+ RWPCI ((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)BIT26, BIT26);
+ RWPCI ((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)BIT26, BIT26);
+ }
+}
+
+
+void usbInitMidPost(AMDSBCFG* pConfig){
+ if (pConfig->UsbOhciLegacyEmulation == 0){
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0);
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64+3, AccWidthUint8 | S3_SAVE, 0xFF, BIT7);
+ }
+ else{
+ programOhciMmioForEmulation();
+ }
+}
+
+
+void programOhciMmioForEmulation(void){
+ UINT32 ddBarAddress;
+
+ ReadPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address
+ ddBarAddress &= 0xFFFFF000;
+ if ( (ddBarAddress != 0xFFFFF000) && (ddBarAddress != 0) ){
+ //Enable Memory access
+ RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG04, AccWidthUint8, 0, BIT1);
+ RWMEM(ddBarAddress+SB_OHCI_BAR_REG160, AccWidthUint32, 0, 0);
+ }
+
+ ReadPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address
+ ddBarAddress &= 0xFFFFF000;
+ if ( (ddBarAddress != 0xFFFFF000) && (ddBarAddress != 0) ){
+ //Enable Memory access
+ RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG04, AccWidthUint8, 0, BIT1);
+ RWMEM(ddBarAddress+SB_OHCI_BAR_REG160, AccWidthUint32, 0, 0);
+ }
+
+ ReadPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address
+ if ( (ddBarAddress != 0xFFFFF000) && (ddBarAddress != 0) ){
+ //Enable Memory access
+ RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG04, AccWidthUint8, 0, BIT1);
+ RWMEM(ddBarAddress+SB_OHCI_BAR_REG160, AccWidthUint32, 0, 0);
+ }
+}
diff --git a/src/vendorcode/amd/cimx/sb700/sbAMDLIB.h b/src/vendorcode/amd/cimx/sb700/sbAMDLIB.h
deleted file mode 100644
index e8f6b38..0000000
--- a/src/vendorcode/amd/cimx/sb700/sbAMDLIB.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/*;********************************************************************************
-;
-; Copyright (C) 2012 Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#ifndef _AMD_AMDLIB_H_
-#define _AMD_AMDLIB_H_
-
-typedef CHAR8 *va_list;
-#ifndef _INTSIZEOF
- #define _INTSIZEOF(n)( (sizeof(n) + sizeof(UINTN) - 1) & ~(sizeof(UINTN) - 1) )
-#endif
-
-// Also support coding convention rules for var arg macros
-#ifndef va_start
-#define va_start(ap,v) ( ap = (va_list)&(v) + _INTSIZEOF(v) )
-#endif
-#define va_arg(ap,t) ( *(t *)((ap += _INTSIZEOF(t)) - _INTSIZEOF(t)) )
-#define va_end(ap) ( ap = (va_list)0 )
-
-#ifndef CIMx_DEBUG
- #define CIMx_DEBUG 0
-#endif
-
-
-#pragma pack(push,1)
-
-#define IMAGE_ALIGN 32*1024
-#define NUM_IMAGE_LOCATION 32
-
-//Entry Point Call
-typedef void (*CIM_IMAGE_ENTRY)(void* pConfig);
-
-//Hook Call
-
-typedef struct _Reg8Mask
-{
- UINT8 bRegIndex;
- UINT8 bANDMask;
- UINT8 bORMask;
-}REG8MASK;
-
-
-typedef struct _CIMFILEHEADER{
- UINT32 AtiLogo;
- UINT32 EntryPoint;
- UINT32 ModuleLogo;
- UINT32 ImageSize;
- UINT16 Version;
- UINT8 CheckSum;
- UINT8 Reserved1;
- UINT32 Reserved2;
-}CIMFILEHEADER;
-
-typedef struct _CPUID_DATA{
- UINT32 REG_EAX;
- UINT32 REG_EBX;
- UINT32 REG_ECX;
- UINT32 REG_EDX;
-}CPUID_DATA;
-
-#ifndef BIT0
- #define BIT0 (1 << 0)
-#endif
-#ifndef BIT1
- #define BIT1 (1 << 1)
-#endif
-#ifndef BIT2
- #define BIT2 (1 << 2)
-#endif
-#ifndef BIT3
- #define BIT3 (1 << 3)
-#endif
-#ifndef BIT4
- #define BIT4 (1 << 4)
-#endif
-#ifndef BIT5
- #define BIT5 (1 << 5)
-#endif
-#ifndef BIT6
- #define BIT6 (1 << 6)
-#endif
-#ifndef BIT7
- #define BIT7 (1 << 7)
-#endif
-#ifndef BIT8
- #define BIT8 (1 << 8)
-#endif
-#ifndef BIT9
- #define BIT9 (1 << 9)
-#endif
-#ifndef BIT10
- #define BIT10 (1 << 10)
-#endif
-#ifndef BIT11
- #define BIT11 (1 << 11)
-#endif
-#ifndef BIT12
- #define BIT12 (1 << 12)
-#endif
-#ifndef BIT13
- #define BIT13 (1 << 13)
-#endif
-#ifndef BIT14
- #define BIT14 (1 << 14)
-#endif
-#ifndef BIT15
- #define BIT15 (1 << 15)
-#endif
-#ifndef BIT16
- #define BIT16 (1 << 16)
-#endif
-#ifndef BIT17
- #define BIT17 (1 << 17)
-#endif
-#ifndef BIT18
- #define BIT18 (1 << 18)
-#endif
-#ifndef BIT19
- #define BIT19 (1 << 19)
-#endif
-#ifndef BIT20
- #define BIT20 (1 << 20)
-#endif
-#ifndef BIT21
- #define BIT21 (1 << 21)
-#endif
-#ifndef BIT22
- #define BIT22 (1 << 22)
-#endif
-#ifndef BIT23
- #define BIT23 (1 << 23)
-#endif
-#ifndef BIT24
- #define BIT24 (1 << 24)
-#endif
-#ifndef BIT25
- #define BIT25 (1 << 25)
-#endif
-#ifndef BIT26
- #define BIT26 (1 << 26)
-#endif
-#ifndef BIT27
- #define BIT27 (1 << 27)
-#endif
-#ifndef BIT28
- #define BIT28 (1 << 28)
-#endif
-#ifndef BIT29
- #define BIT29 (1 << 29)
-#endif
-#ifndef BIT30
- #define BIT30 (1 << 30)
-#endif
-#ifndef BIT31
- #define BIT31 (1 << 31)
-#endif
-
-#define PCI_ADDRESS(bus,dev,func,reg) \
-(UINT32) ( (((UINT32)bus) << 24) + (((UINT32)dev) << 19) + (((UINT32)func) << 16) + ((UINT32)reg) )
-
-#pragma pack(pop)
-
-typedef enum {
- AccWidthUint8 = 0,
- AccWidthUint16,
- AccWidthUint32,
-} ACC_WIDTH;
-
-#define S3_SAVE 0x80
-
-#endif //#ifndef _AMD_AMDLIB_H_
diff --git a/src/vendorcode/amd/cimx/sb800/ACPILIB.c b/src/vendorcode/amd/cimx/sb800/ACPILIB.c
deleted file mode 100644
index bc11209..0000000
--- a/src/vendorcode/amd/cimx/sb800/ACPILIB.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "SBPLATFORM.h"
-#include "cbtypes.h"
-
-//
-//
-// Routine Description:
-//
-// Locate ACPI table
-//
-// Arguments:
-//
-// Signature - table signature
-//
-//Returns:
-//
-// pointer to ACPI table
-//
-//
-VOID*
-ACPI_LocateTable (
- IN UINT32 Signature
- )
-{
- UINT32 i;
- UINT32* RsdPtr;
- UINT32* Rsdt;
- UINTN tableOffset;
- DESCRIPTION_HEADER* CurrentTable;
-
- RsdPtr = (UINT32*) (UINTN)0xe0000;
- Rsdt = NULL;
- do {
- if ( *RsdPtr == Int32FromChar('R', 'S', 'D', ' ') && *(RsdPtr + 1) == Int32FromChar('P', 'T', 'R', ' ')) {
- Rsdt = (UINT32*) (UINTN) ((RSDP*)RsdPtr)->RsdtAddress;
- break;
- }
- RsdPtr += 4;
- } while ( RsdPtr <= (UINT32*) (UINTN)0xffff0 );
- if ( Rsdt != NULL && ACPI_GetTableChecksum (Rsdt) == 0 ) {
- for ( i = 0; i < (((DESCRIPTION_HEADER*)Rsdt)->Length - sizeof (DESCRIPTION_HEADER)) / 4; i++ ) {
- tableOffset = *(UINTN*) ((UINT8*)Rsdt + sizeof (DESCRIPTION_HEADER) + i * 4);
- CurrentTable = (DESCRIPTION_HEADER*)tableOffset;
- if ( CurrentTable->Signature == Signature ) {
- return CurrentTable;
- }
- }
- }
- return NULL;
-}
-
-//
-//
-// Routine Description:
-//
-// Update table checksum
-//
-// Arguments:
-//
-// TablePtr - table pointer
-//
-// Returns:
-//
-// none
-//
-//
-VOID
-ACPI_SetTableChecksum (
- IN VOID* TablePtr
- )
-{
- UINT8 Checksum;
- Checksum = 0;
- ((DESCRIPTION_HEADER*)TablePtr)->Checksum = 0;
- Checksum = ACPI_GetTableChecksum (TablePtr);
- ((DESCRIPTION_HEADER*)TablePtr)->Checksum = (UINT8)(0x100 - Checksum);
-}
-
-//
-//
-// Routine Description:
-//
-// Get table checksum
-//
-// Arguments:
-//
-// TablePtr - table pointer
-//
-// Returns:
-//
-// none
-//
-//
-UINT8
-ACPI_GetTableChecksum (
- IN VOID* TablePtr
- )
-{
- return GetByteSum (TablePtr, ((DESCRIPTION_HEADER*)TablePtr)->Length);
-}
-
-
-UINT8
-GetByteSum (
- IN VOID* pData,
- IN UINT32 Length
- )
-{
- UINT32 i;
- UINT8 Checksum;
- Checksum = 0;
- for ( i = 0; i < Length; i++ ) {
- Checksum = Checksum + (*((UINT8*)pData + i));
- }
- return Checksum;
-}
-VOID
-GetSbAcpiMmioBase (
- OUT UINT32* AcpiMmioBase
- )
-{
- UINT32 Value16;
-
- ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint16, &Value16);
- *AcpiMmioBase = Value16 << 16;
-}
-
-VOID
-GetSbAcpiPmBase (
- OUT UINT16* AcpiPmBase
- )
-{
- ReadPMIO (SB_PMIOA_REG60, AccWidthUint16, AcpiPmBase);
-}
-
diff --git a/src/vendorcode/amd/cimx/sb800/ACPILIB.h b/src/vendorcode/amd/cimx/sb800/ACPILIB.h
deleted file mode 100644
index 73571f4..0000000
--- a/src/vendorcode/amd/cimx/sb800/ACPILIB.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/**
- * RSDP - ACPI 2.0 table RSDP
- */
-typedef struct _RSDP
-{
- unsigned long long Signature; /* RSDP signature "RSD PTR" */
- unsigned char Checksum; /* checksum of the first 20 bytes */
- unsigned char OEMID[6]; /* OEM ID, "LXBIOS" */
- unsigned char Revision; /* 0 for APCI 1.0, 2 for ACPI 2.0 */
- unsigned int RsdtAddress; /* physical address of RSDT */
- unsigned int Length; /* total length of RSDP (including extended part) */
- unsigned long long XsdtAddress; /* physical address of XSDT */
- unsigned char ExtendedChecksum; /* chechsum of whole table */
- unsigned char Reserved[3];
-} RSDP;
-
-
-/**
- * DESCRIPTION_HEADER - ACPI common table header
- */
-typedef struct _DESCRIPTION_HEADER
-{
- unsigned int Signature; /* ACPI signature (4 ASCII characters) */
- unsigned int Length; /* Length of table, in bytes, including header */
- unsigned char Revision; /* ACPI Specification minor version # */
- unsigned char Checksum; /* To make sum of entire table == 0 */
- unsigned char OEMID[6]; /* OEM identification */
- unsigned char OEMTableID[8]; /* OEM table identification */
- unsigned int OEMRevision; /* OEM revision number */
- unsigned int CreatorID; /* ASL compiler vendor ID */
- unsigned int CreatorRevision; /* ASL compiler revision number */
-} DESCRIPTION_HEADER;
-
-void* ACPI_LocateTable (IN unsigned int Signature);
-void ACPI_SetTableChecksum (IN void* TablePtr);
-unsigned char ACPI_GetTableChecksum (IN void* TablePtr);
-unsigned char GetByteSum (IN void* pData, IN unsigned int Length);
diff --git a/src/vendorcode/amd/cimx/sb800/AMDLIB.c b/src/vendorcode/amd/cimx/sb800/AMDLIB.c
deleted file mode 100644
index 90e9e27..0000000
--- a/src/vendorcode/amd/cimx/sb800/AMDLIB.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "SBPLATFORM.h"
-#include "cbtypes.h"
-
-UINT8
-getNumberOfCpuCores (
- OUT VOID
- )
-{
- UINT8 Result;
- Result = 1;
- Result = ReadNumberOfCpuCores ();
- return Result;
-}
-
-UINT32
-readAlink (
- IN UINT32 Index
- )
-{
- UINT32 Data;
- WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32, &Index);
- ReadIO (ALINK_ACCESS_DATA, AccWidthUint32, &Data);
- //Clear Index
- Index = 0;
- WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32, &Index);
- return Data;
-}
-
-VOID
-writeAlink (
- IN UINT32 Index,
- IN UINT32 Data
- )
-{
- WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &Index);
- WriteIO (ALINK_ACCESS_DATA, AccWidthUint32 | S3_SAVE, &Data);
- //Clear Index
- Index = 0;
- WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &Index);
-}
-
-VOID
-rwAlink (
- IN UINT32 Index,
- IN UINT32 AndMask,
- IN UINT32 OrMask
- )
-{
- UINT32 AccesType;
- AccesType = Index & 0xE0000000;
- if (AccesType == (AXINDC << 29)) {
- writeAlink ((SB_AX_INDXC_REG30 | AccesType), Index & 0x1FFFFFFF);
- Index = (SB_AX_DATAC_REG34 | AccesType);
- } else if (AccesType == (AXINDP << 29)) {
- writeAlink ((SB_AX_INDXP_REG38 | AccesType), Index & 0x1FFFFFFF);
- Index = (SB_AX_DATAP_REG3C | AccesType);
- }
- writeAlink (Index, (readAlink (Index) & AndMask) | OrMask );
-}
-
diff --git a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.c b/src/vendorcode/amd/cimx/sb800/AMDSBLIB.c
deleted file mode 100644
index a5d92ad..0000000
--- a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/**
- * @file
- *
- * Southbridge IO access common routine
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: CIMx-SB
- * @e sub-project:
- * @e \$Revision:$ @e \$Date:$
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "SBPLATFORM.h"
-#include "cbtypes.h"
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * SbStall - Delay routine
- *
- *
- *
- * @param[in] uSec
- *
- */
-VOID
-SbStall (
- IN UINT32 uSec
- )
-{
- UINT16 timerAddr;
- UINT32 startTime;
- UINT32 elapsedTime;
-
- ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, &timerAddr);
- if ( timerAddr == 0 ) {
- uSec = uSec / 2;
- while ( uSec != 0 ) {
- ReadIO (0x80, AccWidthUint8, (UINT8 *) (&startTime));
- uSec--;
- }
- } else {
- ReadIO (timerAddr, AccWidthUint32, &startTime);
- for ( ;; ) {
- ReadIO (timerAddr, AccWidthUint32, &elapsedTime);
- if ( elapsedTime < startTime ) {
- elapsedTime = elapsedTime + 0xFFFFFFFF - startTime;
- } else {
- elapsedTime = elapsedTime - startTime;
- }
- if ( (elapsedTime * 28 / 100) > uSec ) {
- break;
- }
- }
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * SbReset - Generate a reset command
- *
- *
- *
- * @param[in] OpFlag - Dummy
- *
- */
-VOID
-SbReset (
- IN UINT8 OpFlag
- )
-{
- UINT8 Temp;
- Temp = OpFlag;
- RWIO (0xcf9, AccWidthUint8, 0x0, 0x06);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * outPort80 - Send data to PORT 80 (debug port)
- *
- *
- *
- * @param[in] pcode - debug code (32 bits)
- *
- */
-VOID
-outPort80 (
- IN UINT32 pcode
- )
-{
- WriteIO (0x80, AccWidthUint8, &pcode);
- return;
-}
-
-/**
- * AmdSbCopyMem - Memory copy
- *
- * @param[in] pDest - Destance address point
- * @param[in] pSource - Source Address point
- * @param[in] Length - Data length
- *
- */
-VOID
-AmdSbCopyMem (
- IN VOID* pDest,
- IN VOID* pSource,
- IN UINTN Length
- )
-{
- UINTN i;
- UINT8 *Ptr;
- UINT8 *Source;
- Ptr = (UINT8*)pDest;
- Source = (UINT8*)pSource;
- for (i = 0; i < Length; i++) {
- *Ptr = *Source;
- Source++;
- Ptr++;
- }
-}
diff --git a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h b/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h
deleted file mode 100644
index 9e50bf9..0000000
--- a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/**
- * @file
- *
- * Southbridge IO access common routine define file
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: CIMx-SB
- * @e sub-project:
- * @e \$Revision:$ @e \$Date:$
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef __VENDORCODE_AMD_CIMX_SB800_AMDSBLIB_H__
-#define __VENDORCODE_AMD_CIMX_SB800_AMDSBLIB_H__
-
-//AMDSBLIB Routines
-
-/**
- * SbStall - Delay routine
- *
- *
- *
- * @param[in] uSec
- *
- */
-void SbStall (IN unsigned int uSec);
-
-/**
- * SbReset - Generate a reset command
- *
- *
- *
- * @param[in] OpFlag - Dummy
- *
- */
-void SbReset (IN unsigned char OpFlag);
-
-/**
- * outPort80 - Send data to PORT 80 (debug port)
- *
- *
- *
- * @param[in] pcode - debug code (32 bits)
- *
- */
-void outPort80 (IN unsigned int pcode);
-
-/**
- * getEfuseStatue - Get Efuse status
- *
- *
- * @param[in] Value - Return Chip strap status
- *
- */
-void getEfuseStatus (IN void* Value);
-
-/**
- * AmdSbDispatcher - Dispatch Southbridge function
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-AGESA_STATUS AmdSbDispatcher (IN void *pConfig);
-
-/**
- * AmdSbCopyMem - Memory copy
- *
- * @param[in] pDest - Destance address point
- * @param[in] pSource - Source Address point
- * @param[in] Length - Data length
- *
- */
-void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN unsigned int Length);
-
-
-/* SB800 CIMx and AGESA V5 can share lib functions */
-unsigned char ReadIo8(IN unsigned short Address);
-unsigned short ReadIo16(IN unsigned short Address);
-unsigned int ReadIo32(IN unsigned short Address);
-void WriteIo8(IN unsigned short Address, IN unsigned char Data);
-void WriteIo16(IN unsigned short Address, IN unsigned short Data);
-void WriteIo32(IN unsigned short Address, IN unsigned int Data);
-//void CpuidRead(IN unsigned int CpuidFcnAddress, OUT CPUID_DATA *Value);
-void CpuidRead(unsigned int CpuidFcnAddress, CPUID_DATA *Value);
-unsigned char ReadNumberOfCpuCores(void);
-
-#endif
diff --git a/src/vendorcode/amd/cimx/sb800/AZALIA.c b/src/vendorcode/amd/cimx/sb800/AZALIA.c
deleted file mode 100644
index ccb4f90..0000000
--- a/src/vendorcode/amd/cimx/sb800/AZALIA.c
+++ /dev/null
@@ -1,512 +0,0 @@
-/**
- * @file
- *
- * Config Southbridge HD Audio Controller
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: CIMx-SB
- * @e sub-project:
- * @e \$Revision:$ @e \$Date:$
- *
- */
-
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-#include "SBPLATFORM.h"
-#include "cbtypes.h"
-
-//
-// Declaration of local functions
-//
-
-VOID configureAzaliaPinCmd (IN AMDSBCFG* pConfig, IN UINT32 ddBAR0, IN UINT8 dbChannelNum);
-VOID configureAzaliaSetConfigD4Dword (IN CODECENTRY* tempAzaliaCodecEntryPtr, IN UINT32 ddChannelNum, IN UINT32 ddBAR0);
-
-/**
- * Pin Config for ALC880, ALC882 and ALC883.
- *
- *
- *
- */
-const static CODECENTRY AzaliaCodecAlc882Table[] =
-{
- {0x14, 0x01014010},
- {0x15, 0x01011012},
- {0x16, 0x01016011},
- {0x17, 0x01012014},
- {0x18, 0x01A19030},
- {0x19, 0x411111F0},
- {0x1a, 0x01813080},
- {0x1b, 0x411111F0},
- {0x1C, 0x411111F0},
- {0x1d, 0x411111F0},
- {0x1e, 0x01441150},
- {0x1f, 0x01C46160},
- {0xff, 0xffffffff}
-};
-
-/**
- * Pin Config for ALC0262.
- *
- *
- *
- */
-const static CODECENTRY AzaliaCodecAlc262Table[] =
-{
- {0x14, 0x01014010},
- {0x15, 0x411111F0},
- {0x16, 0x411111F0},
- {0x18, 0x01A19830},
- {0x19, 0x02A19C40},
- {0x1a, 0x01813031},
- {0x1b, 0x02014C20},
- {0x1c, 0x411111F0},
- {0x1d, 0x411111F0},
- {0x1e, 0x0144111E},
- {0x1f, 0x01C46150},
- {0xff, 0xffffffff}
-};
-
-/**
- * Pin Config for ALC0269.
- *
- *
- *
- */
-const static CODECENTRY AzaliaCodecAlc269Table[] =
-{
- {0x12, 0x99A30960},
- {0x14, 0x99130110},
- {0x15, 0x0221401F},
- {0x16, 0x99130120},
- {0x18, 0x01A19850},
- {0x19, 0x02A15951},
- {0x1a, 0x01813052},
- {0x1b, 0x0181405F},
- {0x1d, 0x40134601},
- {0x1e, 0x01441130},
- {0x11, 0x18567140},
- {0x20, 0x0030FFFF},
- {0xff, 0xffffffff}
-};
-
-/**
- * Pin Config for ALC0861.
- *
- *
- *
- */
-const static CODECENTRY AzaliaCodecAlc861Table[] =
-{
- {0x01, 0x8086C601},
- {0x0B, 0x01014110},
- {0x0C, 0x01813140},
- {0x0D, 0x01A19941},
- {0x0E, 0x411111F0},
- {0x0F, 0x02214420},
- {0x10, 0x02A1994E},
- {0x11, 0x99330142},
- {0x12, 0x01451130},
- {0x1F, 0x411111F0},
- {0x20, 0x411111F0},
- {0x23, 0x411111F0},
- {0xff, 0xffffffff}
-};
-
-/**
- * Pin Config for ALC0889.
- *
- *
- *
- */
-const static CODECENTRY AzaliaCodecAlc889Table[] =
-{
- {0x11, 0x411111F0},
- {0x14, 0x01014010},
- {0x15, 0x01011012},
- {0x16, 0x01016011},
- {0x17, 0x01013014},
- {0x18, 0x01A19030},
- {0x19, 0x411111F0},
- {0x1a, 0x411111F0},
- {0x1b, 0x411111F0},
- {0x1C, 0x411111F0},
- {0x1d, 0x411111F0},
- {0x1e, 0x01442150},
- {0x1f, 0x01C42160},
- {0xff, 0xffffffff}
-};
-
-/**
- * Pin Config for ADI1984.
- *
- *
- *
- */
-const static CODECENTRY AzaliaCodecAd1984Table[] =
-{
- {0x11, 0x0221401F},
- {0x12, 0x90170110},
- {0x13, 0x511301F0},
- {0x14, 0x02A15020},
- {0x15, 0x50A301F0},
- {0x16, 0x593301F0},
- {0x17, 0x55A601F0},
- {0x18, 0x55A601F0},
- {0x1A, 0x91F311F0},
- {0x1B, 0x014511A0},
- {0x1C, 0x599301F0},
- {0xff, 0xffffffff}
-};
-
-/**
- * FrontPanel Config table list
- *
- *
- *
- */
-const static CODECENTRY FrontPanelAzaliaCodecTableList[] =
-{
- {0x19, 0x02A19040},
- {0x1b, 0x02214020},
- {0xff, 0xffffffff}
-};
-
-/**
- * Current HD Audio support codec list
- *
- *
- *
- */
-const static CODECTBLLIST azaliaCodecTableList[] =
-{
- {0x010ec0880, (CODECENTRY*)&AzaliaCodecAlc882Table[0]},
- {0x010ec0882, (CODECENTRY*)&AzaliaCodecAlc882Table[0]},
- {0x010ec0883, (CODECENTRY*)&AzaliaCodecAlc882Table[0]},
- {0x010ec0885, (CODECENTRY*)&AzaliaCodecAlc882Table[0]},
- {0x010ec0889, (CODECENTRY*)&AzaliaCodecAlc889Table[0]},
- {0x010ec0262, (CODECENTRY*)&AzaliaCodecAlc262Table[0]},
- {0x010ec0269, (CODECENTRY*)&AzaliaCodecAlc269Table[0]},
- {0x010ec0861, (CODECENTRY*)&AzaliaCodecAlc861Table[0]},
- {0x011d41984, (CODECENTRY*)&AzaliaCodecAd1984Table[0]},
- { (UINT32) 0x0FFFFFFFF, (CODECENTRY*) (UINTN)0x0FFFFFFFF}
-};
-
-/**
- * azaliaInitBeforePciEnum - Config HD Audio Before PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-azaliaInitBeforePciEnum (
- IN AMDSBCFG* pConfig
- )
-{
- if ( pConfig->AzaliaController == 1 ) {
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0);
- } else {
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, BIT0);
- if ( pConfig->BuildParameters.HdAudioMsi) {
- RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG44, AccWidthUint32 | S3_SAVE, ~BIT8, BIT8);
- RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG60, AccWidthUint32 | S3_SAVE, ~BIT16, BIT16);
- }
- }
-}
-
-/**
- * azaliaInitAfterPciEnum - Config HD Audio after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-azaliaInitAfterPciEnum (
- IN AMDSBCFG* pConfig
- )
-{
- UINT8 Data;
- UINT8 i;
- UINT8 dbEnableAzalia;
- UINT8 dbPinRouting;
- UINT8 dbChannelNum;
- UINT8 dbTempVariable;
- UINT16 dwTempVariable;
- UINT32 ddBAR0;
- UINT32 ddTempVariable;
- dbEnableAzalia = 0;
- dbChannelNum = 0;
- dbTempVariable = 0;
- dwTempVariable = 0;
- ddBAR0 = 0;
- ddTempVariable = 0;
-
- if ( pConfig->AzaliaController == 1 ) {
- return;
- }
-
- if ( pConfig->AzaliaController != 1 ) {
- RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~BIT1, BIT1);
- if ( pConfig->BuildParameters.AzaliaSsid != 0 ) {
- RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.AzaliaSsid);
- }
- ReadPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0);
- if ( ddBAR0 != 0 ) {
- if ( ddBAR0 != 0xFFFFFFFF ) {
- ddBAR0 &= ~(0x03FFF);
- dbEnableAzalia = 1;
- }
- }
- }
-
- if ( dbEnableAzalia ) {
- // Get SDIN Configuration
- if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin0 == 2 ) {
- RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x3E);
- RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x00);
- } else {
- RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x0);
- RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x01);
- }
- if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin1 == 2 ) {
- RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x3E);
- RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x00);
- } else {
- RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x0);
- RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x01);
- }
- if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin2 == 2 ) {
- RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x3E);
- RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x00);
- } else {
- RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x0);
- RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x01);
- }
- if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin3 == 2 ) {
- RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x3E);
- RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x00);
- } else {
- RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x0);
- RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x01);
- }
- // INT#A Azalia resource
- Data = 0x93; // Azalia APIC index
- WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &Data);
- Data = 0x10; // IRQ16 (INTA#)
- WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &Data);
-
- i = 11;
- do {
- ReadMEM ( ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
- dbTempVariable |= BIT0;
- WriteMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
- SbStall (1000);
- ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
- i--;
- } while ((! (dbTempVariable & BIT0)) && (i > 0) );
-
- if ( i == 0 ) {
- return;
- }
-
- SbStall (1000);
- ReadMEM ( ddBAR0 + SB_AZ_BAR_REG0E, AccWidthUint16, &dwTempVariable);
- if ( dwTempVariable & 0x0F ) {
-
- //atleast one azalia codec found
- // ?? E0 is not real register what we expect. we have change to GPIO/and program GPIO Mux
- //ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGE0, AccWidthUint8, &dbPinRouting);
- dbPinRouting = pConfig->AZALIACONFIG.AzaliaSdinPin;
- do {
- if ( ( ! (dbPinRouting & BIT0) ) && (dbPinRouting & BIT1) ) {
-// dbChannelNum = 3;
- configureAzaliaPinCmd (pConfig, ddBAR0, dbChannelNum);
- }
- dbPinRouting >>= 2;
- dbChannelNum++;
- } while ( dbChannelNum != 4 );
- } else {
- //No Azalia codec found
- if ( pConfig->AzaliaController != 2 ) {
- dbEnableAzalia = 0; //set flag to disable Azalia
- }
- }
- }
-
- if ( dbEnableAzalia ) {
- //redo clear reset
- do {
- dwTempVariable = 0;
- WriteMEM ( ddBAR0 + SB_AZ_BAR_REG0C, AccWidthUint16 | S3_SAVE, &dwTempVariable);
- ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
- dbTempVariable &= ~(BIT0);
- WriteMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
- ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
- } while ( dbTempVariable & BIT0 );
-
- if ( pConfig->AzaliaSnoop == 1 ) {
- RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG42, AccWidthUint8 | S3_SAVE, 0xFF, BIT1 + BIT0);
- }
- } else {
- //disable Azalia controller
- RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint16 | S3_SAVE, 0, 0);
- // RWPMIO (SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, ~BIT3, 0);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0);
- // RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8 | S3_SAVE, 0, 0x55);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0);
- }
-}
-
-/**
- * configureAzaliaPinCmd - Configuration HD Audio PIN Command
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- * @param[in] ddBAR0 HD Audio BAR0 base address.
- * @param[in] dbChannelNum Channel Number.
- *
- */
-VOID
-configureAzaliaPinCmd (
- IN AMDSBCFG* pConfig,
- IN UINT32 ddBAR0,
- IN UINT8 dbChannelNum
- )
-{
- UINT32 ddTempVariable;
- UINT32 ddChannelNum;
- CODECTBLLIST* ptempAzaliaOemCodecTablePtr;
- CODECENTRY* tempAzaliaCodecEntryPtr;
-
- if ( (pConfig->AzaliaPinCfg) != 1 ) {
- return;
- }
-
- ddChannelNum = dbChannelNum << 28;
- ddTempVariable = 0xF0000;
- ddTempVariable |= ddChannelNum;
-
- WriteMEM (ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddTempVariable);
- SbStall (600);
- ReadMEM (ddBAR0 + SB_AZ_BAR_REG64, AccWidthUint32 | S3_SAVE, &ddTempVariable);
-
- if ( ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) (UINTN)0xFFFFFFFF))) {
- ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) FIXUP_PTR (&azaliaCodecTableList[0]);
- } else {
- ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr;
- }
-
- while ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF ) {
- if ( ptempAzaliaOemCodecTablePtr->CodecID == ddTempVariable ) {
- break;
- } else {
- ++ptempAzaliaOemCodecTablePtr;
- }
- }
-
- if ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF ) {
- tempAzaliaCodecEntryPtr = (CODECENTRY*) ptempAzaliaOemCodecTablePtr->CodecTablePtr;
-
- if ( ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) (UINTN)0xFFFFFFFF)) ) {
- tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR (tempAzaliaCodecEntryPtr);
- }
- configureAzaliaSetConfigD4Dword (tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0);
- if ( pConfig->AzaliaFrontPanel != 1 ) {
- if ( (pConfig->AzaliaFrontPanel == 2) || (pConfig->FrontPanelDetected == 1) ) {
- if ( ((pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr) == NULL) || ((pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr) == (VOID*) (UINTN)0xFFFFFFFF) ) {
- tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR (&FrontPanelAzaliaCodecTableList[0]);
- } else {
- tempAzaliaCodecEntryPtr = (CODECENTRY*) pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr;
- }
- configureAzaliaSetConfigD4Dword (tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0);
- }
- }
- }
-}
-
-/**
- * configureAzaliaSetConfigD4Dword - Configuration HD Audio Codec table
- *
- *
- * @param[in] tempAzaliaCodecEntryPtr HD Audio Codec table structure pointer.
- * @param[in] ddChannelNum HD Audio Channel Number.
- * @param[in] ddBAR0 HD Audio BAR0 base address.
- *
- */
-VOID
-configureAzaliaSetConfigD4Dword (
- IN CODECENTRY* tempAzaliaCodecEntryPtr,
- IN UINT32 ddChannelNum,
- IN UINT32 ddBAR0
- )
-{
- UINT8 dbtemp1;
- UINT8 dbtemp2;
- UINT8 i;
- UINT32 ddtemp;
- UINT32 ddtemp2;
- ddtemp = 0;
- ddtemp2 = 0;
- while ( (tempAzaliaCodecEntryPtr->Nid) != 0xFF ) {
- dbtemp1 = 0x20;
- if ( (tempAzaliaCodecEntryPtr->Nid) == 0x1 ) {
- dbtemp1 = 0x24;
- }
-
- ddtemp = tempAzaliaCodecEntryPtr->Nid;
- ddtemp &= 0xff;
- ddtemp <<= 20;
- ddtemp |= ddChannelNum;
-
- ddtemp |= (0x700 << 8);
- for ( i = 4; i > 0; i-- ) {
- do {
- ReadMEM (ddBAR0 + SB_AZ_BAR_REG68, AccWidthUint32, &ddtemp2);
- } while ( ddtemp2 & BIT0 );
-
- dbtemp2 = (UINT8) (( (tempAzaliaCodecEntryPtr->Byte40) >> ((4 - i) * 8 ) ) & 0xff);
- ddtemp = (ddtemp & 0xFFFF0000) + ((dbtemp1 - i) << 8) + dbtemp2;
- WriteMEM (ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddtemp);
- SbStall (60);
- }
- ++tempAzaliaCodecEntryPtr;
- }
-}
-
diff --git a/src/vendorcode/amd/cimx/sb800/AcpiLib.c b/src/vendorcode/amd/cimx/sb800/AcpiLib.c
new file mode 100644
index 0000000..bc11209
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/AcpiLib.c
@@ -0,0 +1,166 @@
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "SBPLATFORM.h"
+#include "cbtypes.h"
+
+//
+//
+// Routine Description:
+//
+// Locate ACPI table
+//
+// Arguments:
+//
+// Signature - table signature
+//
+//Returns:
+//
+// pointer to ACPI table
+//
+//
+VOID*
+ACPI_LocateTable (
+ IN UINT32 Signature
+ )
+{
+ UINT32 i;
+ UINT32* RsdPtr;
+ UINT32* Rsdt;
+ UINTN tableOffset;
+ DESCRIPTION_HEADER* CurrentTable;
+
+ RsdPtr = (UINT32*) (UINTN)0xe0000;
+ Rsdt = NULL;
+ do {
+ if ( *RsdPtr == Int32FromChar('R', 'S', 'D', ' ') && *(RsdPtr + 1) == Int32FromChar('P', 'T', 'R', ' ')) {
+ Rsdt = (UINT32*) (UINTN) ((RSDP*)RsdPtr)->RsdtAddress;
+ break;
+ }
+ RsdPtr += 4;
+ } while ( RsdPtr <= (UINT32*) (UINTN)0xffff0 );
+ if ( Rsdt != NULL && ACPI_GetTableChecksum (Rsdt) == 0 ) {
+ for ( i = 0; i < (((DESCRIPTION_HEADER*)Rsdt)->Length - sizeof (DESCRIPTION_HEADER)) / 4; i++ ) {
+ tableOffset = *(UINTN*) ((UINT8*)Rsdt + sizeof (DESCRIPTION_HEADER) + i * 4);
+ CurrentTable = (DESCRIPTION_HEADER*)tableOffset;
+ if ( CurrentTable->Signature == Signature ) {
+ return CurrentTable;
+ }
+ }
+ }
+ return NULL;
+}
+
+//
+//
+// Routine Description:
+//
+// Update table checksum
+//
+// Arguments:
+//
+// TablePtr - table pointer
+//
+// Returns:
+//
+// none
+//
+//
+VOID
+ACPI_SetTableChecksum (
+ IN VOID* TablePtr
+ )
+{
+ UINT8 Checksum;
+ Checksum = 0;
+ ((DESCRIPTION_HEADER*)TablePtr)->Checksum = 0;
+ Checksum = ACPI_GetTableChecksum (TablePtr);
+ ((DESCRIPTION_HEADER*)TablePtr)->Checksum = (UINT8)(0x100 - Checksum);
+}
+
+//
+//
+// Routine Description:
+//
+// Get table checksum
+//
+// Arguments:
+//
+// TablePtr - table pointer
+//
+// Returns:
+//
+// none
+//
+//
+UINT8
+ACPI_GetTableChecksum (
+ IN VOID* TablePtr
+ )
+{
+ return GetByteSum (TablePtr, ((DESCRIPTION_HEADER*)TablePtr)->Length);
+}
+
+
+UINT8
+GetByteSum (
+ IN VOID* pData,
+ IN UINT32 Length
+ )
+{
+ UINT32 i;
+ UINT8 Checksum;
+ Checksum = 0;
+ for ( i = 0; i < Length; i++ ) {
+ Checksum = Checksum + (*((UINT8*)pData + i));
+ }
+ return Checksum;
+}
+VOID
+GetSbAcpiMmioBase (
+ OUT UINT32* AcpiMmioBase
+ )
+{
+ UINT32 Value16;
+
+ ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint16, &Value16);
+ *AcpiMmioBase = Value16 << 16;
+}
+
+VOID
+GetSbAcpiPmBase (
+ OUT UINT16* AcpiPmBase
+ )
+{
+ ReadPMIO (SB_PMIOA_REG60, AccWidthUint16, AcpiPmBase);
+}
+
diff --git a/src/vendorcode/amd/cimx/sb800/AcpiLib.h b/src/vendorcode/amd/cimx/sb800/AcpiLib.h
new file mode 100644
index 0000000..73571f4
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/AcpiLib.h
@@ -0,0 +1,69 @@
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+/**
+ * RSDP - ACPI 2.0 table RSDP
+ */
+typedef struct _RSDP
+{
+ unsigned long long Signature; /* RSDP signature "RSD PTR" */
+ unsigned char Checksum; /* checksum of the first 20 bytes */
+ unsigned char OEMID[6]; /* OEM ID, "LXBIOS" */
+ unsigned char Revision; /* 0 for APCI 1.0, 2 for ACPI 2.0 */
+ unsigned int RsdtAddress; /* physical address of RSDT */
+ unsigned int Length; /* total length of RSDP (including extended part) */
+ unsigned long long XsdtAddress; /* physical address of XSDT */
+ unsigned char ExtendedChecksum; /* chechsum of whole table */
+ unsigned char Reserved[3];
+} RSDP;
+
+
+/**
+ * DESCRIPTION_HEADER - ACPI common table header
+ */
+typedef struct _DESCRIPTION_HEADER
+{
+ unsigned int Signature; /* ACPI signature (4 ASCII characters) */
+ unsigned int Length; /* Length of table, in bytes, including header */
+ unsigned char Revision; /* ACPI Specification minor version # */
+ unsigned char Checksum; /* To make sum of entire table == 0 */
+ unsigned char OEMID[6]; /* OEM identification */
+ unsigned char OEMTableID[8]; /* OEM table identification */
+ unsigned int OEMRevision; /* OEM revision number */
+ unsigned int CreatorID; /* ASL compiler vendor ID */
+ unsigned int CreatorRevision; /* ASL compiler revision number */
+} DESCRIPTION_HEADER;
+
+void* ACPI_LocateTable (IN unsigned int Signature);
+void ACPI_SetTableChecksum (IN void* TablePtr);
+unsigned char ACPI_GetTableChecksum (IN void* TablePtr);
+unsigned char GetByteSum (IN void* pData, IN unsigned int Length);
diff --git a/src/vendorcode/amd/cimx/sb800/AmdLib.c b/src/vendorcode/amd/cimx/sb800/AmdLib.c
new file mode 100644
index 0000000..90e9e27
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/AmdLib.c
@@ -0,0 +1,92 @@
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "SBPLATFORM.h"
+#include "cbtypes.h"
+
+UINT8
+getNumberOfCpuCores (
+ OUT VOID
+ )
+{
+ UINT8 Result;
+ Result = 1;
+ Result = ReadNumberOfCpuCores ();
+ return Result;
+}
+
+UINT32
+readAlink (
+ IN UINT32 Index
+ )
+{
+ UINT32 Data;
+ WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32, &Index);
+ ReadIO (ALINK_ACCESS_DATA, AccWidthUint32, &Data);
+ //Clear Index
+ Index = 0;
+ WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32, &Index);
+ return Data;
+}
+
+VOID
+writeAlink (
+ IN UINT32 Index,
+ IN UINT32 Data
+ )
+{
+ WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &Index);
+ WriteIO (ALINK_ACCESS_DATA, AccWidthUint32 | S3_SAVE, &Data);
+ //Clear Index
+ Index = 0;
+ WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &Index);
+}
+
+VOID
+rwAlink (
+ IN UINT32 Index,
+ IN UINT32 AndMask,
+ IN UINT32 OrMask
+ )
+{
+ UINT32 AccesType;
+ AccesType = Index & 0xE0000000;
+ if (AccesType == (AXINDC << 29)) {
+ writeAlink ((SB_AX_INDXC_REG30 | AccesType), Index & 0x1FFFFFFF);
+ Index = (SB_AX_DATAC_REG34 | AccesType);
+ } else if (AccesType == (AXINDP << 29)) {
+ writeAlink ((SB_AX_INDXP_REG38 | AccesType), Index & 0x1FFFFFFF);
+ Index = (SB_AX_DATAP_REG3C | AccesType);
+ }
+ writeAlink (Index, (readAlink (Index) & AndMask) | OrMask );
+}
+
diff --git a/src/vendorcode/amd/cimx/sb800/AmdSbLib.c b/src/vendorcode/amd/cimx/sb800/AmdSbLib.c
new file mode 100644
index 0000000..a5d92ad
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/AmdSbLib.c
@@ -0,0 +1,152 @@
+/**
+ * @file
+ *
+ * Southbridge IO access common routine
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$ @e \$Date:$
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "SBPLATFORM.h"
+#include "cbtypes.h"
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * SbStall - Delay routine
+ *
+ *
+ *
+ * @param[in] uSec
+ *
+ */
+VOID
+SbStall (
+ IN UINT32 uSec
+ )
+{
+ UINT16 timerAddr;
+ UINT32 startTime;
+ UINT32 elapsedTime;
+
+ ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, &timerAddr);
+ if ( timerAddr == 0 ) {
+ uSec = uSec / 2;
+ while ( uSec != 0 ) {
+ ReadIO (0x80, AccWidthUint8, (UINT8 *) (&startTime));
+ uSec--;
+ }
+ } else {
+ ReadIO (timerAddr, AccWidthUint32, &startTime);
+ for ( ;; ) {
+ ReadIO (timerAddr, AccWidthUint32, &elapsedTime);
+ if ( elapsedTime < startTime ) {
+ elapsedTime = elapsedTime + 0xFFFFFFFF - startTime;
+ } else {
+ elapsedTime = elapsedTime - startTime;
+ }
+ if ( (elapsedTime * 28 / 100) > uSec ) {
+ break;
+ }
+ }
+ }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * SbReset - Generate a reset command
+ *
+ *
+ *
+ * @param[in] OpFlag - Dummy
+ *
+ */
+VOID
+SbReset (
+ IN UINT8 OpFlag
+ )
+{
+ UINT8 Temp;
+ Temp = OpFlag;
+ RWIO (0xcf9, AccWidthUint8, 0x0, 0x06);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * outPort80 - Send data to PORT 80 (debug port)
+ *
+ *
+ *
+ * @param[in] pcode - debug code (32 bits)
+ *
+ */
+VOID
+outPort80 (
+ IN UINT32 pcode
+ )
+{
+ WriteIO (0x80, AccWidthUint8, &pcode);
+ return;
+}
+
+/**
+ * AmdSbCopyMem - Memory copy
+ *
+ * @param[in] pDest - Destance address point
+ * @param[in] pSource - Source Address point
+ * @param[in] Length - Data length
+ *
+ */
+VOID
+AmdSbCopyMem (
+ IN VOID* pDest,
+ IN VOID* pSource,
+ IN UINTN Length
+ )
+{
+ UINTN i;
+ UINT8 *Ptr;
+ UINT8 *Source;
+ Ptr = (UINT8*)pDest;
+ Source = (UINT8*)pSource;
+ for (i = 0; i < Length; i++) {
+ *Ptr = *Source;
+ Source++;
+ Ptr++;
+ }
+}
diff --git a/src/vendorcode/amd/cimx/sb800/AmdSbLib.h b/src/vendorcode/amd/cimx/sb800/AmdSbLib.h
new file mode 100644
index 0000000..9e50bf9
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/AmdSbLib.h
@@ -0,0 +1,122 @@
+/**
+ * @file
+ *
+ * Southbridge IO access common routine define file
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$ @e \$Date:$
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#ifndef __VENDORCODE_AMD_CIMX_SB800_AMDSBLIB_H__
+#define __VENDORCODE_AMD_CIMX_SB800_AMDSBLIB_H__
+
+//AMDSBLIB Routines
+
+/**
+ * SbStall - Delay routine
+ *
+ *
+ *
+ * @param[in] uSec
+ *
+ */
+void SbStall (IN unsigned int uSec);
+
+/**
+ * SbReset - Generate a reset command
+ *
+ *
+ *
+ * @param[in] OpFlag - Dummy
+ *
+ */
+void SbReset (IN unsigned char OpFlag);
+
+/**
+ * outPort80 - Send data to PORT 80 (debug port)
+ *
+ *
+ *
+ * @param[in] pcode - debug code (32 bits)
+ *
+ */
+void outPort80 (IN unsigned int pcode);
+
+/**
+ * getEfuseStatue - Get Efuse status
+ *
+ *
+ * @param[in] Value - Return Chip strap status
+ *
+ */
+void getEfuseStatus (IN void* Value);
+
+/**
+ * AmdSbDispatcher - Dispatch Southbridge function
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+AGESA_STATUS AmdSbDispatcher (IN void *pConfig);
+
+/**
+ * AmdSbCopyMem - Memory copy
+ *
+ * @param[in] pDest - Destance address point
+ * @param[in] pSource - Source Address point
+ * @param[in] Length - Data length
+ *
+ */
+void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN unsigned int Length);
+
+
+/* SB800 CIMx and AGESA V5 can share lib functions */
+unsigned char ReadIo8(IN unsigned short Address);
+unsigned short ReadIo16(IN unsigned short Address);
+unsigned int ReadIo32(IN unsigned short Address);
+void WriteIo8(IN unsigned short Address, IN unsigned char Data);
+void WriteIo16(IN unsigned short Address, IN unsigned short Data);
+void WriteIo32(IN unsigned short Address, IN unsigned int Data);
+//void CpuidRead(IN unsigned int CpuidFcnAddress, OUT CPUID_DATA *Value);
+void CpuidRead(unsigned int CpuidFcnAddress, CPUID_DATA *Value);
+unsigned char ReadNumberOfCpuCores(void);
+
+#endif
diff --git a/src/vendorcode/amd/cimx/sb800/Azalia.c b/src/vendorcode/amd/cimx/sb800/Azalia.c
new file mode 100644
index 0000000..ccb4f90
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/Azalia.c
@@ -0,0 +1,512 @@
+/**
+ * @file
+ *
+ * Config Southbridge HD Audio Controller
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$ @e \$Date:$
+ *
+ */
+
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+
+#include "SBPLATFORM.h"
+#include "cbtypes.h"
+
+//
+// Declaration of local functions
+//
+
+VOID configureAzaliaPinCmd (IN AMDSBCFG* pConfig, IN UINT32 ddBAR0, IN UINT8 dbChannelNum);
+VOID configureAzaliaSetConfigD4Dword (IN CODECENTRY* tempAzaliaCodecEntryPtr, IN UINT32 ddChannelNum, IN UINT32 ddBAR0);
+
+/**
+ * Pin Config for ALC880, ALC882 and ALC883.
+ *
+ *
+ *
+ */
+const static CODECENTRY AzaliaCodecAlc882Table[] =
+{
+ {0x14, 0x01014010},
+ {0x15, 0x01011012},
+ {0x16, 0x01016011},
+ {0x17, 0x01012014},
+ {0x18, 0x01A19030},
+ {0x19, 0x411111F0},
+ {0x1a, 0x01813080},
+ {0x1b, 0x411111F0},
+ {0x1C, 0x411111F0},
+ {0x1d, 0x411111F0},
+ {0x1e, 0x01441150},
+ {0x1f, 0x01C46160},
+ {0xff, 0xffffffff}
+};
+
+/**
+ * Pin Config for ALC0262.
+ *
+ *
+ *
+ */
+const static CODECENTRY AzaliaCodecAlc262Table[] =
+{
+ {0x14, 0x01014010},
+ {0x15, 0x411111F0},
+ {0x16, 0x411111F0},
+ {0x18, 0x01A19830},
+ {0x19, 0x02A19C40},
+ {0x1a, 0x01813031},
+ {0x1b, 0x02014C20},
+ {0x1c, 0x411111F0},
+ {0x1d, 0x411111F0},
+ {0x1e, 0x0144111E},
+ {0x1f, 0x01C46150},
+ {0xff, 0xffffffff}
+};
+
+/**
+ * Pin Config for ALC0269.
+ *
+ *
+ *
+ */
+const static CODECENTRY AzaliaCodecAlc269Table[] =
+{
+ {0x12, 0x99A30960},
+ {0x14, 0x99130110},
+ {0x15, 0x0221401F},
+ {0x16, 0x99130120},
+ {0x18, 0x01A19850},
+ {0x19, 0x02A15951},
+ {0x1a, 0x01813052},
+ {0x1b, 0x0181405F},
+ {0x1d, 0x40134601},
+ {0x1e, 0x01441130},
+ {0x11, 0x18567140},
+ {0x20, 0x0030FFFF},
+ {0xff, 0xffffffff}
+};
+
+/**
+ * Pin Config for ALC0861.
+ *
+ *
+ *
+ */
+const static CODECENTRY AzaliaCodecAlc861Table[] =
+{
+ {0x01, 0x8086C601},
+ {0x0B, 0x01014110},
+ {0x0C, 0x01813140},
+ {0x0D, 0x01A19941},
+ {0x0E, 0x411111F0},
+ {0x0F, 0x02214420},
+ {0x10, 0x02A1994E},
+ {0x11, 0x99330142},
+ {0x12, 0x01451130},
+ {0x1F, 0x411111F0},
+ {0x20, 0x411111F0},
+ {0x23, 0x411111F0},
+ {0xff, 0xffffffff}
+};
+
+/**
+ * Pin Config for ALC0889.
+ *
+ *
+ *
+ */
+const static CODECENTRY AzaliaCodecAlc889Table[] =
+{
+ {0x11, 0x411111F0},
+ {0x14, 0x01014010},
+ {0x15, 0x01011012},
+ {0x16, 0x01016011},
+ {0x17, 0x01013014},
+ {0x18, 0x01A19030},
+ {0x19, 0x411111F0},
+ {0x1a, 0x411111F0},
+ {0x1b, 0x411111F0},
+ {0x1C, 0x411111F0},
+ {0x1d, 0x411111F0},
+ {0x1e, 0x01442150},
+ {0x1f, 0x01C42160},
+ {0xff, 0xffffffff}
+};
+
+/**
+ * Pin Config for ADI1984.
+ *
+ *
+ *
+ */
+const static CODECENTRY AzaliaCodecAd1984Table[] =
+{
+ {0x11, 0x0221401F},
+ {0x12, 0x90170110},
+ {0x13, 0x511301F0},
+ {0x14, 0x02A15020},
+ {0x15, 0x50A301F0},
+ {0x16, 0x593301F0},
+ {0x17, 0x55A601F0},
+ {0x18, 0x55A601F0},
+ {0x1A, 0x91F311F0},
+ {0x1B, 0x014511A0},
+ {0x1C, 0x599301F0},
+ {0xff, 0xffffffff}
+};
+
+/**
+ * FrontPanel Config table list
+ *
+ *
+ *
+ */
+const static CODECENTRY FrontPanelAzaliaCodecTableList[] =
+{
+ {0x19, 0x02A19040},
+ {0x1b, 0x02214020},
+ {0xff, 0xffffffff}
+};
+
+/**
+ * Current HD Audio support codec list
+ *
+ *
+ *
+ */
+const static CODECTBLLIST azaliaCodecTableList[] =
+{
+ {0x010ec0880, (CODECENTRY*)&AzaliaCodecAlc882Table[0]},
+ {0x010ec0882, (CODECENTRY*)&AzaliaCodecAlc882Table[0]},
+ {0x010ec0883, (CODECENTRY*)&AzaliaCodecAlc882Table[0]},
+ {0x010ec0885, (CODECENTRY*)&AzaliaCodecAlc882Table[0]},
+ {0x010ec0889, (CODECENTRY*)&AzaliaCodecAlc889Table[0]},
+ {0x010ec0262, (CODECENTRY*)&AzaliaCodecAlc262Table[0]},
+ {0x010ec0269, (CODECENTRY*)&AzaliaCodecAlc269Table[0]},
+ {0x010ec0861, (CODECENTRY*)&AzaliaCodecAlc861Table[0]},
+ {0x011d41984, (CODECENTRY*)&AzaliaCodecAd1984Table[0]},
+ { (UINT32) 0x0FFFFFFFF, (CODECENTRY*) (UINTN)0x0FFFFFFFF}
+};
+
+/**
+ * azaliaInitBeforePciEnum - Config HD Audio Before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+azaliaInitBeforePciEnum (
+ IN AMDSBCFG* pConfig
+ )
+{
+ if ( pConfig->AzaliaController == 1 ) {
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0);
+ } else {
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, BIT0);
+ if ( pConfig->BuildParameters.HdAudioMsi) {
+ RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG44, AccWidthUint32 | S3_SAVE, ~BIT8, BIT8);
+ RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG60, AccWidthUint32 | S3_SAVE, ~BIT16, BIT16);
+ }
+ }
+}
+
+/**
+ * azaliaInitAfterPciEnum - Config HD Audio after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+azaliaInitAfterPciEnum (
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT8 Data;
+ UINT8 i;
+ UINT8 dbEnableAzalia;
+ UINT8 dbPinRouting;
+ UINT8 dbChannelNum;
+ UINT8 dbTempVariable;
+ UINT16 dwTempVariable;
+ UINT32 ddBAR0;
+ UINT32 ddTempVariable;
+ dbEnableAzalia = 0;
+ dbChannelNum = 0;
+ dbTempVariable = 0;
+ dwTempVariable = 0;
+ ddBAR0 = 0;
+ ddTempVariable = 0;
+
+ if ( pConfig->AzaliaController == 1 ) {
+ return;
+ }
+
+ if ( pConfig->AzaliaController != 1 ) {
+ RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~BIT1, BIT1);
+ if ( pConfig->BuildParameters.AzaliaSsid != 0 ) {
+ RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.AzaliaSsid);
+ }
+ ReadPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0);
+ if ( ddBAR0 != 0 ) {
+ if ( ddBAR0 != 0xFFFFFFFF ) {
+ ddBAR0 &= ~(0x03FFF);
+ dbEnableAzalia = 1;
+ }
+ }
+ }
+
+ if ( dbEnableAzalia ) {
+ // Get SDIN Configuration
+ if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin0 == 2 ) {
+ RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x3E);
+ RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x00);
+ } else {
+ RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x0);
+ RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x01);
+ }
+ if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin1 == 2 ) {
+ RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x3E);
+ RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x00);
+ } else {
+ RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x0);
+ RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x01);
+ }
+ if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin2 == 2 ) {
+ RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x3E);
+ RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x00);
+ } else {
+ RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x0);
+ RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x01);
+ }
+ if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin3 == 2 ) {
+ RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x3E);
+ RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x00);
+ } else {
+ RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x0);
+ RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x01);
+ }
+ // INT#A Azalia resource
+ Data = 0x93; // Azalia APIC index
+ WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &Data);
+ Data = 0x10; // IRQ16 (INTA#)
+ WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &Data);
+
+ i = 11;
+ do {
+ ReadMEM ( ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+ dbTempVariable |= BIT0;
+ WriteMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+ SbStall (1000);
+ ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+ i--;
+ } while ((! (dbTempVariable & BIT0)) && (i > 0) );
+
+ if ( i == 0 ) {
+ return;
+ }
+
+ SbStall (1000);
+ ReadMEM ( ddBAR0 + SB_AZ_BAR_REG0E, AccWidthUint16, &dwTempVariable);
+ if ( dwTempVariable & 0x0F ) {
+
+ //atleast one azalia codec found
+ // ?? E0 is not real register what we expect. we have change to GPIO/and program GPIO Mux
+ //ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGE0, AccWidthUint8, &dbPinRouting);
+ dbPinRouting = pConfig->AZALIACONFIG.AzaliaSdinPin;
+ do {
+ if ( ( ! (dbPinRouting & BIT0) ) && (dbPinRouting & BIT1) ) {
+// dbChannelNum = 3;
+ configureAzaliaPinCmd (pConfig, ddBAR0, dbChannelNum);
+ }
+ dbPinRouting >>= 2;
+ dbChannelNum++;
+ } while ( dbChannelNum != 4 );
+ } else {
+ //No Azalia codec found
+ if ( pConfig->AzaliaController != 2 ) {
+ dbEnableAzalia = 0; //set flag to disable Azalia
+ }
+ }
+ }
+
+ if ( dbEnableAzalia ) {
+ //redo clear reset
+ do {
+ dwTempVariable = 0;
+ WriteMEM ( ddBAR0 + SB_AZ_BAR_REG0C, AccWidthUint16 | S3_SAVE, &dwTempVariable);
+ ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+ dbTempVariable &= ~(BIT0);
+ WriteMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+ ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+ } while ( dbTempVariable & BIT0 );
+
+ if ( pConfig->AzaliaSnoop == 1 ) {
+ RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG42, AccWidthUint8 | S3_SAVE, 0xFF, BIT1 + BIT0);
+ }
+ } else {
+ //disable Azalia controller
+ RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint16 | S3_SAVE, 0, 0);
+ // RWPMIO (SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, ~BIT3, 0);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0);
+ // RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8 | S3_SAVE, 0, 0x55);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0);
+ }
+}
+
+/**
+ * configureAzaliaPinCmd - Configuration HD Audio PIN Command
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ * @param[in] ddBAR0 HD Audio BAR0 base address.
+ * @param[in] dbChannelNum Channel Number.
+ *
+ */
+VOID
+configureAzaliaPinCmd (
+ IN AMDSBCFG* pConfig,
+ IN UINT32 ddBAR0,
+ IN UINT8 dbChannelNum
+ )
+{
+ UINT32 ddTempVariable;
+ UINT32 ddChannelNum;
+ CODECTBLLIST* ptempAzaliaOemCodecTablePtr;
+ CODECENTRY* tempAzaliaCodecEntryPtr;
+
+ if ( (pConfig->AzaliaPinCfg) != 1 ) {
+ return;
+ }
+
+ ddChannelNum = dbChannelNum << 28;
+ ddTempVariable = 0xF0000;
+ ddTempVariable |= ddChannelNum;
+
+ WriteMEM (ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddTempVariable);
+ SbStall (600);
+ ReadMEM (ddBAR0 + SB_AZ_BAR_REG64, AccWidthUint32 | S3_SAVE, &ddTempVariable);
+
+ if ( ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) (UINTN)0xFFFFFFFF))) {
+ ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) FIXUP_PTR (&azaliaCodecTableList[0]);
+ } else {
+ ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr;
+ }
+
+ while ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF ) {
+ if ( ptempAzaliaOemCodecTablePtr->CodecID == ddTempVariable ) {
+ break;
+ } else {
+ ++ptempAzaliaOemCodecTablePtr;
+ }
+ }
+
+ if ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF ) {
+ tempAzaliaCodecEntryPtr = (CODECENTRY*) ptempAzaliaOemCodecTablePtr->CodecTablePtr;
+
+ if ( ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) (UINTN)0xFFFFFFFF)) ) {
+ tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR (tempAzaliaCodecEntryPtr);
+ }
+ configureAzaliaSetConfigD4Dword (tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0);
+ if ( pConfig->AzaliaFrontPanel != 1 ) {
+ if ( (pConfig->AzaliaFrontPanel == 2) || (pConfig->FrontPanelDetected == 1) ) {
+ if ( ((pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr) == NULL) || ((pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr) == (VOID*) (UINTN)0xFFFFFFFF) ) {
+ tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR (&FrontPanelAzaliaCodecTableList[0]);
+ } else {
+ tempAzaliaCodecEntryPtr = (CODECENTRY*) pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr;
+ }
+ configureAzaliaSetConfigD4Dword (tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0);
+ }
+ }
+ }
+}
+
+/**
+ * configureAzaliaSetConfigD4Dword - Configuration HD Audio Codec table
+ *
+ *
+ * @param[in] tempAzaliaCodecEntryPtr HD Audio Codec table structure pointer.
+ * @param[in] ddChannelNum HD Audio Channel Number.
+ * @param[in] ddBAR0 HD Audio BAR0 base address.
+ *
+ */
+VOID
+configureAzaliaSetConfigD4Dword (
+ IN CODECENTRY* tempAzaliaCodecEntryPtr,
+ IN UINT32 ddChannelNum,
+ IN UINT32 ddBAR0
+ )
+{
+ UINT8 dbtemp1;
+ UINT8 dbtemp2;
+ UINT8 i;
+ UINT32 ddtemp;
+ UINT32 ddtemp2;
+ ddtemp = 0;
+ ddtemp2 = 0;
+ while ( (tempAzaliaCodecEntryPtr->Nid) != 0xFF ) {
+ dbtemp1 = 0x20;
+ if ( (tempAzaliaCodecEntryPtr->Nid) == 0x1 ) {
+ dbtemp1 = 0x24;
+ }
+
+ ddtemp = tempAzaliaCodecEntryPtr->Nid;
+ ddtemp &= 0xff;
+ ddtemp <<= 20;
+ ddtemp |= ddChannelNum;
+
+ ddtemp |= (0x700 << 8);
+ for ( i = 4; i > 0; i-- ) {
+ do {
+ ReadMEM (ddBAR0 + SB_AZ_BAR_REG68, AccWidthUint32, &ddtemp2);
+ } while ( ddtemp2 & BIT0 );
+
+ dbtemp2 = (UINT8) (( (tempAzaliaCodecEntryPtr->Byte40) >> ((4 - i) * 8 ) ) & 0xff);
+ ddtemp = (ddtemp & 0xFFFF0000) + ((dbtemp1 - i) << 8) + dbtemp2;
+ WriteMEM (ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddtemp);
+ SbStall (60);
+ }
+ ++tempAzaliaCodecEntryPtr;
+ }
+}
+
diff --git a/src/vendorcode/amd/cimx/sb800/DISPATCHER.c b/src/vendorcode/amd/cimx/sb800/DISPATCHER.c
deleted file mode 100644
index 8b35047..0000000
--- a/src/vendorcode/amd/cimx/sb800/DISPATCHER.c
+++ /dev/null
@@ -1,252 +0,0 @@
-/**
- * @file
- *
- * Function dispatcher.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: CIMx-SB
- * @e sub-project:
- * @e \$Revision:$ @e \$Date:$
- *
- */
-
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "SBPLATFORM.h"
-#include "cbtypes.h"
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
-*/
-
-
-//
-// Declaration of local functions
-//
-
-VOID saveConfigPointer (IN AMDSBCFG* pConfig);
-VOID* VerifyImage (IN UINT64 Signature, IN VOID* ImagePtr);
-VOID* LocateImage (IN UINT64 Signature);
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/**
- * AmdSbDispatcher - Dispatch Southbridge function
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-AGESA_STATUS
-AmdSbDispatcher (
- IN VOID *pConfig
- )
-{
- AGESA_STATUS Status;
-
-#ifdef B1_IMAGE
- VOID *pAltImagePtr;
- CIM_IMAGE_ENTRY AltImageEntry;
-#endif
-
- UINT64 tdValue;
- tdValue = 0x32314130384253ULL;
-
-#ifdef B1_IMAGE
- pAltImagePtr = NULL;
-#endif
- Status = AGESA_UNSUPPORTED;
-
-#ifdef B1_IMAGE
- if ((UINT32) (UINTN) (((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr) != 0xffffffff ) {
- if ( ((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr ) {
- pAltImagePtr = VerifyImage ( tdValue, (VOID*) (UINTN) ((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr);
- }
- if ( pAltImagePtr == NULL ) {
- pAltImagePtr = LocateImage ( tdValue );
- }
- if ( pAltImagePtr != NULL ) {
- ((AMD_CONFIG_PARAMS*)pConfig)->ImageBasePtr = (UINT32) (UINTN) pAltImagePtr;
- AltImageEntry = (CIM_IMAGE_ENTRY) (UINTN) ((UINT32) (UINTN) pAltImagePtr + (UINT32) (((AMD_IMAGE_HEADER*) (UINTN) pAltImagePtr)->EntryPointAddress));
- (*AltImageEntry) (pConfig);
- return Status;
- }
- }
-#endif
- saveConfigPointer (pConfig);
-
- if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_POWERON_INIT ) {
- sbPowerOnInit ((AMDSBCFG*) pConfig);
- }
-
-#ifndef B1_IMAGE
- if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_INIT ) {
- sbBeforePciInit ((AMDSBCFG*)pConfig);
- }
-
- if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_INIT ) {
- sbAfterPciInit ((AMDSBCFG*)pConfig);
- }
-
- if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_MID_POST_INIT ) {
- sbMidPostInit ((AMDSBCFG*)pConfig);
- }
-
- if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_LATE_POST_INIT ) {
- sbLatePost ((AMDSBCFG*)pConfig);
- }
-
- if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_RESTORE_INIT ) {
- sbBeforePciRestoreInit ((AMDSBCFG*)pConfig);
- }
-
- if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_RESTORE_INIT ) {
- sbAfterPciRestoreInit ((AMDSBCFG*)pConfig);
- }
-
- if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_SERVICE ) {
- sbSmmService ((AMDSBCFG*)pConfig);
- }
-
- if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_ACPION ) {
- sbSmmAcpiOn ((AMDSBCFG*)pConfig);
- }
-
- if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_EC_FANCONTROL ) {
- sbECfancontrolservice((AMDSBCFG*)pConfig);
- }
-#endif
- return Status;
-}
-
-/**
- * LocateImage - Locate Southbridge CIMx module
- *
- *
- *
- * @param[in] Signature Southbridge CIMx image signature.
- *
- */
-VOID*
-LocateImage (
- IN UINT64 Signature
- )
-{
- VOID *Result;
- UINT32 ImagePtr;
- ImagePtr = 0xffffffff - (IMAGE_ALIGN - 1);
-
- while ( ImagePtr >= (0xfffffff - (NUM_IMAGE_LOCATION * IMAGE_ALIGN - 1)) ) {
- Result = VerifyImage (Signature, (VOID*)(UINTN)ImagePtr);
- if ( Result != NULL ) {
- return Result;
- }
- ImagePtr -= IMAGE_ALIGN;
- }
- return NULL;
-}
-
-/**
- * VerifyImage - Verify Southbridge CIMx module
- *
- *
- * @param[in] Signature Southbridge CIMx image signature.
- * @param[in] ImagePtr Southbridge CIMx image address.
- *
- */
-VOID*
-VerifyImage (
- IN UINT64 Signature,
- IN VOID* ImagePtr
- )
-{
- UINT16 *TempImagePtr;
- UINT16 Sum;
- UINT32 i;
- Sum = 0;
- if ( (*((UINT32*)ImagePtr) == Int32FromChar('$', 'A', 'M', 'D') && ((CIMFILEHEADER*)ImagePtr)->CreatorID == Signature) ) {
- //GetImage Image size
- TempImagePtr = (UINT16*)ImagePtr;
- for ( i = 0; i < (((CIMFILEHEADER*)ImagePtr)->ImageSize); i += 2 ) {
- Sum = Sum + *TempImagePtr;
- TempImagePtr++;
- }
- if ( Sum == 0 ) {
- return ImagePtr;
- }
- }
- return NULL;
-}
-
-/**
- * saveConfigPointer - Verify Southbridge CIMx module
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-saveConfigPointer (
- IN AMDSBCFG* pConfig
- )
-{
- UINT8 dbReg;
- UINT8 i;
- UINT32 ddValue;
-
- ddValue = (UINT32) (UINTN)pConfig; // Needs to live below 4G
- dbReg = SB_ECMOS_REG08;
-
- for ( i = 0; i <= 3; i++ ) {
- WriteIO (SB_IOMAP_REG72, AccWidthUint8, &dbReg);
- WriteIO (SB_IOMAP_REG73, AccWidthUint8, (UINT8*)&ddValue);
- ddValue = (ddValue >> 8);
- dbReg++;
- }
-}
diff --git a/src/vendorcode/amd/cimx/sb800/Dispatcher.c b/src/vendorcode/amd/cimx/sb800/Dispatcher.c
new file mode 100644
index 0000000..8b35047
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/Dispatcher.c
@@ -0,0 +1,252 @@
+/**
+ * @file
+ *
+ * Function dispatcher.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$ @e \$Date:$
+ *
+ */
+
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "SBPLATFORM.h"
+#include "cbtypes.h"
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+*/
+
+
+//
+// Declaration of local functions
+//
+
+VOID saveConfigPointer (IN AMDSBCFG* pConfig);
+VOID* VerifyImage (IN UINT64 Signature, IN VOID* ImagePtr);
+VOID* LocateImage (IN UINT64 Signature);
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * E X P O R T E D F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * AmdSbDispatcher - Dispatch Southbridge function
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+AGESA_STATUS
+AmdSbDispatcher (
+ IN VOID *pConfig
+ )
+{
+ AGESA_STATUS Status;
+
+#ifdef B1_IMAGE
+ VOID *pAltImagePtr;
+ CIM_IMAGE_ENTRY AltImageEntry;
+#endif
+
+ UINT64 tdValue;
+ tdValue = 0x32314130384253ULL;
+
+#ifdef B1_IMAGE
+ pAltImagePtr = NULL;
+#endif
+ Status = AGESA_UNSUPPORTED;
+
+#ifdef B1_IMAGE
+ if ((UINT32) (UINTN) (((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr) != 0xffffffff ) {
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr ) {
+ pAltImagePtr = VerifyImage ( tdValue, (VOID*) (UINTN) ((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr);
+ }
+ if ( pAltImagePtr == NULL ) {
+ pAltImagePtr = LocateImage ( tdValue );
+ }
+ if ( pAltImagePtr != NULL ) {
+ ((AMD_CONFIG_PARAMS*)pConfig)->ImageBasePtr = (UINT32) (UINTN) pAltImagePtr;
+ AltImageEntry = (CIM_IMAGE_ENTRY) (UINTN) ((UINT32) (UINTN) pAltImagePtr + (UINT32) (((AMD_IMAGE_HEADER*) (UINTN) pAltImagePtr)->EntryPointAddress));
+ (*AltImageEntry) (pConfig);
+ return Status;
+ }
+ }
+#endif
+ saveConfigPointer (pConfig);
+
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_POWERON_INIT ) {
+ sbPowerOnInit ((AMDSBCFG*) pConfig);
+ }
+
+#ifndef B1_IMAGE
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_INIT ) {
+ sbBeforePciInit ((AMDSBCFG*)pConfig);
+ }
+
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_INIT ) {
+ sbAfterPciInit ((AMDSBCFG*)pConfig);
+ }
+
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_MID_POST_INIT ) {
+ sbMidPostInit ((AMDSBCFG*)pConfig);
+ }
+
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_LATE_POST_INIT ) {
+ sbLatePost ((AMDSBCFG*)pConfig);
+ }
+
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_RESTORE_INIT ) {
+ sbBeforePciRestoreInit ((AMDSBCFG*)pConfig);
+ }
+
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_RESTORE_INIT ) {
+ sbAfterPciRestoreInit ((AMDSBCFG*)pConfig);
+ }
+
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_SERVICE ) {
+ sbSmmService ((AMDSBCFG*)pConfig);
+ }
+
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_ACPION ) {
+ sbSmmAcpiOn ((AMDSBCFG*)pConfig);
+ }
+
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_EC_FANCONTROL ) {
+ sbECfancontrolservice((AMDSBCFG*)pConfig);
+ }
+#endif
+ return Status;
+}
+
+/**
+ * LocateImage - Locate Southbridge CIMx module
+ *
+ *
+ *
+ * @param[in] Signature Southbridge CIMx image signature.
+ *
+ */
+VOID*
+LocateImage (
+ IN UINT64 Signature
+ )
+{
+ VOID *Result;
+ UINT32 ImagePtr;
+ ImagePtr = 0xffffffff - (IMAGE_ALIGN - 1);
+
+ while ( ImagePtr >= (0xfffffff - (NUM_IMAGE_LOCATION * IMAGE_ALIGN - 1)) ) {
+ Result = VerifyImage (Signature, (VOID*)(UINTN)ImagePtr);
+ if ( Result != NULL ) {
+ return Result;
+ }
+ ImagePtr -= IMAGE_ALIGN;
+ }
+ return NULL;
+}
+
+/**
+ * VerifyImage - Verify Southbridge CIMx module
+ *
+ *
+ * @param[in] Signature Southbridge CIMx image signature.
+ * @param[in] ImagePtr Southbridge CIMx image address.
+ *
+ */
+VOID*
+VerifyImage (
+ IN UINT64 Signature,
+ IN VOID* ImagePtr
+ )
+{
+ UINT16 *TempImagePtr;
+ UINT16 Sum;
+ UINT32 i;
+ Sum = 0;
+ if ( (*((UINT32*)ImagePtr) == Int32FromChar('$', 'A', 'M', 'D') && ((CIMFILEHEADER*)ImagePtr)->CreatorID == Signature) ) {
+ //GetImage Image size
+ TempImagePtr = (UINT16*)ImagePtr;
+ for ( i = 0; i < (((CIMFILEHEADER*)ImagePtr)->ImageSize); i += 2 ) {
+ Sum = Sum + *TempImagePtr;
+ TempImagePtr++;
+ }
+ if ( Sum == 0 ) {
+ return ImagePtr;
+ }
+ }
+ return NULL;
+}
+
+/**
+ * saveConfigPointer - Verify Southbridge CIMx module
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+saveConfigPointer (
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT8 dbReg;
+ UINT8 i;
+ UINT32 ddValue;
+
+ ddValue = (UINT32) (UINTN)pConfig; // Needs to live below 4G
+ dbReg = SB_ECMOS_REG08;
+
+ for ( i = 0; i <= 3; i++ ) {
+ WriteIO (SB_IOMAP_REG72, AccWidthUint8, &dbReg);
+ WriteIO (SB_IOMAP_REG73, AccWidthUint8, (UINT8*)&ddValue);
+ ddValue = (ddValue >> 8);
+ dbReg++;
+ }
+}
diff --git a/src/vendorcode/amd/cimx/sb800/EC.c b/src/vendorcode/amd/cimx/sb800/EC.c
deleted file mode 100644
index 9e70e8b..0000000
--- a/src/vendorcode/amd/cimx/sb800/EC.c
+++ /dev/null
@@ -1,131 +0,0 @@
-
-/**
- * @file
- *
- * Config Southbridge EC Controller
- *
- * Init EC features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: CIMx-SB
- * @e sub-project:
- * @e \$Revision:$ @e \$Date:$
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "SBPLATFORM.h"
-#include "cbtypes.h"
-
-#ifndef NO_EC_SUPPORT
-
-/**
- * Config EC controller during power-on
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-ecPowerOnInit (
- IN AMDSBCFG* pConfig
- )
-{
- //Enable config mode
- EnterEcConfig ();
-
- //Do settings for mailbox - logical device 0x09
- RWEC8 (0x07, 0x00, 0x09); //switch to device 9 (Mailbox)
- RWEC8 (0x60, 0x00, (MailBoxPort >> 8)); //set MSB of Mailbox port
- RWEC8 (0x61, 0x00, (MailBoxPort & 0xFF)); //set LSB of Mailbox port
- RWEC8 (0x30, 0x00, 0x01); //;Enable Mailbox Registers Interface, bit0=1
-
- if ( pConfig->BuildParameters.EcKbd == CIMX_OPTION_ENABLED) {
- //Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD6, AccWidthUint8, ~BIT8, BIT0 + BIT1 + BIT2 + BIT3);
-
- //Disable LPC Decoding of port 60/64
- RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG47), AccWidthUint8 | S3_SAVE, ~BIT5, 0);
-
- //Enable logical device 0x07 (Keyboard controller)
- RWEC8 (0x07, 0x00, 0x07);
- RWEC8 (0x30, 0x00, 0x01);
- }
-
- if ( pConfig->BuildParameters.EcChannel0 == CIMX_OPTION_ENABLED) {
- //Logical device 0x03
- RWEC8 (0x07, 0x00, 0x03);
- RWEC8 (0x60, 0x00, 0x00);
- RWEC8 (0x61, 0x00, 0x62);
- RWEC8 (0x30, 0x00, 0x01); //;Enable Device 8
- }
-
- //Enable EC (IMC) to generate SMI to BIOS
- RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB3, AccWidthUint8, ~BIT6, BIT6);
- ExitEcConfig ();
-}
-
-/**
- * Config EC controller before PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-ecInitBeforePciEnum (
- IN AMDSBCFG* pConfig
- )
-{
- AMDSBCFG* pTmp; // dummy code
- pTmp = pConfig;
-}
-
-/**
- * Prepare EC controller to boot to OS.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-ecInitLatePost (
- IN AMDSBCFG* pConfig
- )
-{
- AMDSBCFG* pTmp; // dummy code
- pTmp = pConfig;
-}
-#endif
diff --git a/src/vendorcode/amd/cimx/sb800/ECLIB.c b/src/vendorcode/amd/cimx/sb800/ECLIB.c
deleted file mode 100644
index 54d87e7..0000000
--- a/src/vendorcode/amd/cimx/sb800/ECLIB.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/**
- * @file
- *
- * Southbridge EC IO access common routine
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "SBPLATFORM.h"
-#include "cbtypes.h"
-
-// #ifndef NO_EC_SUPPORT
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * EnterEcConfig - Force EC into Config mode
- *
- *
- *
- *
- */
-VOID
-EnterEcConfig (
- )
-{
- UINT16 dwEcIndexPort;
-
- ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
- dwEcIndexPort &= ~(BIT0);
- RWIO (dwEcIndexPort, AccWidthUint8, 0x00, 0x5A);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * ExitEcConfig - Force EC exit Config mode
- *
- *
- *
- *
- */
-VOID
-ExitEcConfig (
- )
-{
- UINT16 dwEcIndexPort;
-
- ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
- dwEcIndexPort &= ~(BIT0);
- RWIO (dwEcIndexPort, AccWidthUint8, 0x00, 0xA5);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * ReadEC8 - Read EC register data
- *
- *
- *
- * @param[in] Address - EC Register Offset Value
- * @param[in] Value - Read Data Buffer
- *
- */
-VOID
-ReadEC8 (
- IN UINT8 Address,
- IN UINT8* Value
- )
-{
- UINT16 dwEcIndexPort;
-
- ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
- dwEcIndexPort &= ~(BIT0);
- WriteIO (dwEcIndexPort, AccWidthUint8, &Address);
- ReadIO (dwEcIndexPort + 1, AccWidthUint8, Value);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * WriteEC8 - Write date into EC register
- *
- *
- *
- * @param[in] Address - EC Register Offset Value
- * @param[in] Value - Write Data Buffer
- *
- */
-VOID
-WriteEC8 (
- IN UINT8 Address,
- IN UINT8* Value
- )
-{
- UINT16 dwEcIndexPort;
-
- ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
- dwEcIndexPort &= ~(BIT0);
-
- WriteIO (dwEcIndexPort, AccWidthUint8, &Address);
- WriteIO (dwEcIndexPort + 1, AccWidthUint8, Value);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * RWEC8 - Read/Write EC register
- *
- *
- *
- * @param[in] Address - EC Register Offset Value
- * @param[in] AndMask - Data And Mask 8 bits
- * @param[in] OrMask - Data OR Mask 8 bits
- *
- */
-VOID
-RWEC8 (
- IN UINT8 Address,
- IN UINT8 AndMask,
- IN UINT8 OrMask
- )
-{
- UINT8 Result;
- ReadEC8 (Address, &Result);
- Result = (Result & AndMask) | OrMask;
- WriteEC8 (Address, &Result);
-}
-
-// #endif
-
diff --git a/src/vendorcode/amd/cimx/sb800/ECfan.h b/src/vendorcode/amd/cimx/sb800/ECfan.h
deleted file mode 100644
index 3fd5fea..0000000
--- a/src/vendorcode/amd/cimx/sb800/ECfan.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "cbtypes.h"
-
-VOID WriteECmsg (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value);
-VOID WaitForEcLDN9MailboxCmdAck (VOID);
-VOID ReadECmsg (IN UINT8 Address, IN UINT8 OpFlag, OUT VOID* Value);
-
-// IMC Message Register Software Interface
-#define CPU_MISC_BUS_DEV_FUN ((0x18 << 3) + 3)
-
-#define MSG_SYS_TO_IMC 0x80
-#define Fun_80 0x80
-#define Fun_81 0x81
-#define Fun_82 0x82
-#define Fun_83 0x83
-#define Fun_84 0x84
-#define Fun_85 0x85
-#define Fun_86 0x86
-#define Fun_87 0x87
-#define Fun_88 0x88
-#define Fun_89 0x89
-#define Fun_90 0x90
-#define MSG_IMC_TO_SYS 0x81
-#define MSG_REG0 0x82
-#define MSG_REG1 0x83
-#define MSG_REG2 0x84
-#define MSG_REG3 0x85
-#define MSG_REG4 0x86
-#define MSG_REG5 0x87
-#define MSG_REG6 0x88
-#define MSG_REG7 0x89
-#define MSG_REG8 0x8A
-#define MSG_REG9 0x8B
-#define MSG_REGA 0x8C
-#define MSG_REGB 0x8D
-#define MSG_REGC 0x8E
-#define MSG_REGD 0x8F
-
-
diff --git a/src/vendorcode/amd/cimx/sb800/ECfanLIB.c b/src/vendorcode/amd/cimx/sb800/ECfanLIB.c
deleted file mode 100644
index 9ac6c88..0000000
--- a/src/vendorcode/amd/cimx/sb800/ECfanLIB.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/**
- * @file
- *
- * Southbridge EC IO access common routine
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "SBPLATFORM.h"
-#include "ECfan.h"
-
-VOID
-ReadECmsg (
- IN UINT8 Address,
- IN UINT8 OpFlag,
- OUT VOID* Value
- )
-{
- UINT8 i;
-
- OpFlag = OpFlag & 0x7f;
- if (OpFlag == 0x02) OpFlag = 0x03;
- for (i = 0; i <= OpFlag; i++) {
- WriteIO(MailBoxPort, AccWidthUint8, &Address); // EC_LDN9_MAILBOX_BASE_ADDRESS
- Address++;
- ReadIO(MailBoxPort + 1, AccWidthUint8, (UINT8 *)Value+i); // EC_LDN9_MAILBOX_BASE_ADDRESS
- }
-}
-
-
-VOID
-WriteECmsg (
- IN UINT8 Address,
- IN UINT8 OpFlag,
- IN VOID* Value
- )
-{
- UINT8 i;
-
- OpFlag = OpFlag & 0x7f;
- if (OpFlag == 0x02) OpFlag = 0x03;
- for (i = 0; i <= OpFlag; i++) {
- WriteIO(MailBoxPort, AccWidthUint8, &Address); // EC_LDN9_MAILBOX_BASE_ADDRESS
- Address++;
- WriteIO(MailBoxPort + 1, AccWidthUint8, (UINT8 *)Value+i); // EC_LDN9_MAILBOX_BASE_ADDRESS
- }
-}
-
-VOID
-WaitForEcLDN9MailboxCmdAck (
- VOID
- )
-{
- UINT8 Msgdata;
- UINT16 Delaytime;
- Msgdata = 0;
- for (Delaytime = 0; Delaytime <= 500; Delaytime++) {
- ReadECmsg (MSG_REG0, AccWidthUint8, &Msgdata);
- if ( Msgdata == 0xfa) {
- break;
- }
- SbStall (1000); // Wait for 1ms
- }
-}
-
-
diff --git a/src/vendorcode/amd/cimx/sb800/ECfanc.c b/src/vendorcode/amd/cimx/sb800/ECfanc.c
deleted file mode 100644
index 7e679c9..0000000
--- a/src/vendorcode/amd/cimx/sb800/ECfanc.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-#include "SBPLATFORM.h"
-#include "ECfan.h"
-/**
- * Table for Function Number
- *
- *
- *
- *
- */
-const static UINT8 FunctionNumber[] =
-{
- Fun_81,
- Fun_83,
- Fun_85,
- Fun_89,
-};
-
-/**
- * Table for Max Thermal Zone
- *
- *
- *
- *
- */
-const static UINT8 MaxZone[] =
-{
- 4,
- 4,
- 4,
- 4,
-};
-
-/**
- * Table for Max Register
- *
- *
- *
- *
- */
-const static UINT8 MaxRegister[] =
-{
- MSG_REG9,
- MSG_REGB,
- MSG_REG9,
- MSG_REGA,
-};
-
-/*-------------------------------------------------------------------------------
-;Procedure: IsZoneFuncEnable
-;
-;Description: This routine will check every zone support function with BitMap from user define
-;
-;
-;Exit: None
-;
-;Modified: None
-;
-;-----------------------------------------------------------------------------
-*/
-BOOLEAN
-IsZoneFuncEnable (
- UINT16 Flag,
- UINT8 func,
- UINT8 Zone
-)
-{
- return (BOOLEAN)(((Flag >> (func *4)) & 0xF) & ((UINT8 )1 << Zone));
-}
-
-/*-------------------------------------------------------------------------------
-;Procedure: sbECfancontrolservice
-;
-;Description: This routine service EC fan policy
-;
-;
-;Exit: None
-;
-;Modified: None
-;
-;-----------------------------------------------------------------------------
-*/
-VOID
-sbECfancontrolservice (
- IN AMDSBCFG* pConfig
- )
-{
- UINT8 ZoneNum;
- UINT8 FunNum;
- UINT8 RegNum;
- UINT8 * CurPoint;
- UINT8 FunIndex;
- BOOLEAN IsSendEcMsg;
-
- CurPoint = &pConfig->Pecstruct.MSGFun81zone0MSGREG0 + MaxZone[0] * (MaxRegister[0] - MSG_REG0 + 1);
- for ( FunIndex = 1; FunIndex <= 3; FunIndex++ ) {
- FunNum = FunctionNumber[FunIndex];
- for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) {
- IsSendEcMsg = IsZoneFuncEnable (pConfig->Pecstruct.IMCFUNSupportBitMap, FunIndex, ZoneNum);
- for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) {
- if (IsSendEcMsg) {
- WriteECmsg (RegNum, AccWidthUint8, CurPoint); //
- }
- CurPoint += 1;
- }
- if (IsSendEcMsg) {
- WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &FunNum); // function number
- WaitForEcLDN9MailboxCmdAck ();
- }
- }
- }
- CurPoint = &pConfig->Pecstruct.MSGFun81zone0MSGREG0;
- for ( FunIndex = 0; FunIndex <= 0; FunIndex++ ) {
- FunNum = FunctionNumber[FunIndex];
- for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) {
- IsSendEcMsg = IsZoneFuncEnable (pConfig->Pecstruct.IMCFUNSupportBitMap, FunIndex, ZoneNum);
- for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) {
- if (IsSendEcMsg) {
- WriteECmsg (RegNum, AccWidthUint8, CurPoint); //
- }
- CurPoint += 1;
- }
- if (IsSendEcMsg) {
- WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &FunNum); // function number
- WaitForEcLDN9MailboxCmdAck ();
- }
- }
- }
-}
-
-/*-------------------------------------------------------------------------------
-;Procedure: SBIMCFanInitializeS3
-;
-;Description: This routine initialize IMC fan when S3 resume
-;
-;
-;Exit: None
-;
-;Modified: None
-;
-;-----------------------------------------------------------------------------
-*/
-VOID
-SBIMCFanInitializeS3 (VOID)
-{
- UINT8 dbPortStatus,Value80,Value82,Value83,Value84;
-
- getChipSysMode (&dbPortStatus);
- if ((dbPortStatus & ChipSysEcEnable) != 0) {
- Value80 = 0x98;
- Value82 = 0x00;
- Value83 = 0x02;
- Value84 = 0x00;
-
- // Clear MSG_REG0 to receive acknowledge byte
- WriteECmsg (MSG_REG0, AccWidthUint8, &Value82);
-
- // Set MSG_REG1
- // 0x02 - Notify IMC that the system is waken from any sleep state
- WriteECmsg (MSG_REG1, AccWidthUint8, &Value83);
-
- // Set timeout counter value to 00 which disables watchdog timer
- WriteECmsg (MSG_REG2, AccWidthUint8, &Value84);
-
- // Write mailbox function number to kick off the command
- // 0x98 - IMC System Sleep and Wake Services
- WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &Value80);
-
- // Read acknowledge byte to make sure function is executed properly
- WaitForEcLDN9MailboxCmdAck ();
- }
-}
diff --git a/src/vendorcode/amd/cimx/sb800/Ec.c b/src/vendorcode/amd/cimx/sb800/Ec.c
new file mode 100644
index 0000000..9e70e8b
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/Ec.c
@@ -0,0 +1,131 @@
+
+/**
+ * @file
+ *
+ * Config Southbridge EC Controller
+ *
+ * Init EC features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$ @e \$Date:$
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "SBPLATFORM.h"
+#include "cbtypes.h"
+
+#ifndef NO_EC_SUPPORT
+
+/**
+ * Config EC controller during power-on
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+ecPowerOnInit (
+ IN AMDSBCFG* pConfig
+ )
+{
+ //Enable config mode
+ EnterEcConfig ();
+
+ //Do settings for mailbox - logical device 0x09
+ RWEC8 (0x07, 0x00, 0x09); //switch to device 9 (Mailbox)
+ RWEC8 (0x60, 0x00, (MailBoxPort >> 8)); //set MSB of Mailbox port
+ RWEC8 (0x61, 0x00, (MailBoxPort & 0xFF)); //set LSB of Mailbox port
+ RWEC8 (0x30, 0x00, 0x01); //;Enable Mailbox Registers Interface, bit0=1
+
+ if ( pConfig->BuildParameters.EcKbd == CIMX_OPTION_ENABLED) {
+ //Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD6, AccWidthUint8, ~BIT8, BIT0 + BIT1 + BIT2 + BIT3);
+
+ //Disable LPC Decoding of port 60/64
+ RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG47), AccWidthUint8 | S3_SAVE, ~BIT5, 0);
+
+ //Enable logical device 0x07 (Keyboard controller)
+ RWEC8 (0x07, 0x00, 0x07);
+ RWEC8 (0x30, 0x00, 0x01);
+ }
+
+ if ( pConfig->BuildParameters.EcChannel0 == CIMX_OPTION_ENABLED) {
+ //Logical device 0x03
+ RWEC8 (0x07, 0x00, 0x03);
+ RWEC8 (0x60, 0x00, 0x00);
+ RWEC8 (0x61, 0x00, 0x62);
+ RWEC8 (0x30, 0x00, 0x01); //;Enable Device 8
+ }
+
+ //Enable EC (IMC) to generate SMI to BIOS
+ RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB3, AccWidthUint8, ~BIT6, BIT6);
+ ExitEcConfig ();
+}
+
+/**
+ * Config EC controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+ecInitBeforePciEnum (
+ IN AMDSBCFG* pConfig
+ )
+{
+ AMDSBCFG* pTmp; // dummy code
+ pTmp = pConfig;
+}
+
+/**
+ * Prepare EC controller to boot to OS.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+ecInitLatePost (
+ IN AMDSBCFG* pConfig
+ )
+{
+ AMDSBCFG* pTmp; // dummy code
+ pTmp = pConfig;
+}
+#endif
diff --git a/src/vendorcode/amd/cimx/sb800/EcFan.h b/src/vendorcode/amd/cimx/sb800/EcFan.h
new file mode 100644
index 0000000..3fd5fea
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/EcFan.h
@@ -0,0 +1,70 @@
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "cbtypes.h"
+
+VOID WriteECmsg (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value);
+VOID WaitForEcLDN9MailboxCmdAck (VOID);
+VOID ReadECmsg (IN UINT8 Address, IN UINT8 OpFlag, OUT VOID* Value);
+
+// IMC Message Register Software Interface
+#define CPU_MISC_BUS_DEV_FUN ((0x18 << 3) + 3)
+
+#define MSG_SYS_TO_IMC 0x80
+#define Fun_80 0x80
+#define Fun_81 0x81
+#define Fun_82 0x82
+#define Fun_83 0x83
+#define Fun_84 0x84
+#define Fun_85 0x85
+#define Fun_86 0x86
+#define Fun_87 0x87
+#define Fun_88 0x88
+#define Fun_89 0x89
+#define Fun_90 0x90
+#define MSG_IMC_TO_SYS 0x81
+#define MSG_REG0 0x82
+#define MSG_REG1 0x83
+#define MSG_REG2 0x84
+#define MSG_REG3 0x85
+#define MSG_REG4 0x86
+#define MSG_REG5 0x87
+#define MSG_REG6 0x88
+#define MSG_REG7 0x89
+#define MSG_REG8 0x8A
+#define MSG_REG9 0x8B
+#define MSG_REGA 0x8C
+#define MSG_REGB 0x8D
+#define MSG_REGC 0x8E
+#define MSG_REGD 0x8F
+
+
diff --git a/src/vendorcode/amd/cimx/sb800/EcFanLib.c b/src/vendorcode/amd/cimx/sb800/EcFanLib.c
new file mode 100644
index 0000000..9ac6c88
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/EcFanLib.c
@@ -0,0 +1,96 @@
+/**
+ * @file
+ *
+ * Southbridge EC IO access common routine
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "SBPLATFORM.h"
+#include "ECfan.h"
+
+VOID
+ReadECmsg (
+ IN UINT8 Address,
+ IN UINT8 OpFlag,
+ OUT VOID* Value
+ )
+{
+ UINT8 i;
+
+ OpFlag = OpFlag & 0x7f;
+ if (OpFlag == 0x02) OpFlag = 0x03;
+ for (i = 0; i <= OpFlag; i++) {
+ WriteIO(MailBoxPort, AccWidthUint8, &Address); // EC_LDN9_MAILBOX_BASE_ADDRESS
+ Address++;
+ ReadIO(MailBoxPort + 1, AccWidthUint8, (UINT8 *)Value+i); // EC_LDN9_MAILBOX_BASE_ADDRESS
+ }
+}
+
+
+VOID
+WriteECmsg (
+ IN UINT8 Address,
+ IN UINT8 OpFlag,
+ IN VOID* Value
+ )
+{
+ UINT8 i;
+
+ OpFlag = OpFlag & 0x7f;
+ if (OpFlag == 0x02) OpFlag = 0x03;
+ for (i = 0; i <= OpFlag; i++) {
+ WriteIO(MailBoxPort, AccWidthUint8, &Address); // EC_LDN9_MAILBOX_BASE_ADDRESS
+ Address++;
+ WriteIO(MailBoxPort + 1, AccWidthUint8, (UINT8 *)Value+i); // EC_LDN9_MAILBOX_BASE_ADDRESS
+ }
+}
+
+VOID
+WaitForEcLDN9MailboxCmdAck (
+ VOID
+ )
+{
+ UINT8 Msgdata;
+ UINT16 Delaytime;
+ Msgdata = 0;
+ for (Delaytime = 0; Delaytime <= 500; Delaytime++) {
+ ReadECmsg (MSG_REG0, AccWidthUint8, &Msgdata);
+ if ( Msgdata == 0xfa) {
+ break;
+ }
+ SbStall (1000); // Wait for 1ms
+ }
+}
+
+
diff --git a/src/vendorcode/amd/cimx/sb800/EcFanc.c b/src/vendorcode/amd/cimx/sb800/EcFanc.c
new file mode 100644
index 0000000..7e679c9
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/EcFanc.c
@@ -0,0 +1,204 @@
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+
+#include "SBPLATFORM.h"
+#include "ECfan.h"
+/**
+ * Table for Function Number
+ *
+ *
+ *
+ *
+ */
+const static UINT8 FunctionNumber[] =
+{
+ Fun_81,
+ Fun_83,
+ Fun_85,
+ Fun_89,
+};
+
+/**
+ * Table for Max Thermal Zone
+ *
+ *
+ *
+ *
+ */
+const static UINT8 MaxZone[] =
+{
+ 4,
+ 4,
+ 4,
+ 4,
+};
+
+/**
+ * Table for Max Register
+ *
+ *
+ *
+ *
+ */
+const static UINT8 MaxRegister[] =
+{
+ MSG_REG9,
+ MSG_REGB,
+ MSG_REG9,
+ MSG_REGA,
+};
+
+/*-------------------------------------------------------------------------------
+;Procedure: IsZoneFuncEnable
+;
+;Description: This routine will check every zone support function with BitMap from user define
+;
+;
+;Exit: None
+;
+;Modified: None
+;
+;-----------------------------------------------------------------------------
+*/
+BOOLEAN
+IsZoneFuncEnable (
+ UINT16 Flag,
+ UINT8 func,
+ UINT8 Zone
+)
+{
+ return (BOOLEAN)(((Flag >> (func *4)) & 0xF) & ((UINT8 )1 << Zone));
+}
+
+/*-------------------------------------------------------------------------------
+;Procedure: sbECfancontrolservice
+;
+;Description: This routine service EC fan policy
+;
+;
+;Exit: None
+;
+;Modified: None
+;
+;-----------------------------------------------------------------------------
+*/
+VOID
+sbECfancontrolservice (
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT8 ZoneNum;
+ UINT8 FunNum;
+ UINT8 RegNum;
+ UINT8 * CurPoint;
+ UINT8 FunIndex;
+ BOOLEAN IsSendEcMsg;
+
+ CurPoint = &pConfig->Pecstruct.MSGFun81zone0MSGREG0 + MaxZone[0] * (MaxRegister[0] - MSG_REG0 + 1);
+ for ( FunIndex = 1; FunIndex <= 3; FunIndex++ ) {
+ FunNum = FunctionNumber[FunIndex];
+ for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) {
+ IsSendEcMsg = IsZoneFuncEnable (pConfig->Pecstruct.IMCFUNSupportBitMap, FunIndex, ZoneNum);
+ for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) {
+ if (IsSendEcMsg) {
+ WriteECmsg (RegNum, AccWidthUint8, CurPoint); //
+ }
+ CurPoint += 1;
+ }
+ if (IsSendEcMsg) {
+ WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &FunNum); // function number
+ WaitForEcLDN9MailboxCmdAck ();
+ }
+ }
+ }
+ CurPoint = &pConfig->Pecstruct.MSGFun81zone0MSGREG0;
+ for ( FunIndex = 0; FunIndex <= 0; FunIndex++ ) {
+ FunNum = FunctionNumber[FunIndex];
+ for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) {
+ IsSendEcMsg = IsZoneFuncEnable (pConfig->Pecstruct.IMCFUNSupportBitMap, FunIndex, ZoneNum);
+ for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) {
+ if (IsSendEcMsg) {
+ WriteECmsg (RegNum, AccWidthUint8, CurPoint); //
+ }
+ CurPoint += 1;
+ }
+ if (IsSendEcMsg) {
+ WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &FunNum); // function number
+ WaitForEcLDN9MailboxCmdAck ();
+ }
+ }
+ }
+}
+
+/*-------------------------------------------------------------------------------
+;Procedure: SBIMCFanInitializeS3
+;
+;Description: This routine initialize IMC fan when S3 resume
+;
+;
+;Exit: None
+;
+;Modified: None
+;
+;-----------------------------------------------------------------------------
+*/
+VOID
+SBIMCFanInitializeS3 (VOID)
+{
+ UINT8 dbPortStatus,Value80,Value82,Value83,Value84;
+
+ getChipSysMode (&dbPortStatus);
+ if ((dbPortStatus & ChipSysEcEnable) != 0) {
+ Value80 = 0x98;
+ Value82 = 0x00;
+ Value83 = 0x02;
+ Value84 = 0x00;
+
+ // Clear MSG_REG0 to receive acknowledge byte
+ WriteECmsg (MSG_REG0, AccWidthUint8, &Value82);
+
+ // Set MSG_REG1
+ // 0x02 - Notify IMC that the system is waken from any sleep state
+ WriteECmsg (MSG_REG1, AccWidthUint8, &Value83);
+
+ // Set timeout counter value to 00 which disables watchdog timer
+ WriteECmsg (MSG_REG2, AccWidthUint8, &Value84);
+
+ // Write mailbox function number to kick off the command
+ // 0x98 - IMC System Sleep and Wake Services
+ WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &Value80);
+
+ // Read acknowledge byte to make sure function is executed properly
+ WaitForEcLDN9MailboxCmdAck ();
+ }
+}
diff --git a/src/vendorcode/amd/cimx/sb800/EcLib.c b/src/vendorcode/amd/cimx/sb800/EcLib.c
new file mode 100644
index 0000000..54d87e7
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/EcLib.c
@@ -0,0 +1,156 @@
+/**
+ * @file
+ *
+ * Southbridge EC IO access common routine
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "SBPLATFORM.h"
+#include "cbtypes.h"
+
+// #ifndef NO_EC_SUPPORT
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * EnterEcConfig - Force EC into Config mode
+ *
+ *
+ *
+ *
+ */
+VOID
+EnterEcConfig (
+ )
+{
+ UINT16 dwEcIndexPort;
+
+ ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
+ dwEcIndexPort &= ~(BIT0);
+ RWIO (dwEcIndexPort, AccWidthUint8, 0x00, 0x5A);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * ExitEcConfig - Force EC exit Config mode
+ *
+ *
+ *
+ *
+ */
+VOID
+ExitEcConfig (
+ )
+{
+ UINT16 dwEcIndexPort;
+
+ ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
+ dwEcIndexPort &= ~(BIT0);
+ RWIO (dwEcIndexPort, AccWidthUint8, 0x00, 0xA5);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * ReadEC8 - Read EC register data
+ *
+ *
+ *
+ * @param[in] Address - EC Register Offset Value
+ * @param[in] Value - Read Data Buffer
+ *
+ */
+VOID
+ReadEC8 (
+ IN UINT8 Address,
+ IN UINT8* Value
+ )
+{
+ UINT16 dwEcIndexPort;
+
+ ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
+ dwEcIndexPort &= ~(BIT0);
+ WriteIO (dwEcIndexPort, AccWidthUint8, &Address);
+ ReadIO (dwEcIndexPort + 1, AccWidthUint8, Value);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * WriteEC8 - Write date into EC register
+ *
+ *
+ *
+ * @param[in] Address - EC Register Offset Value
+ * @param[in] Value - Write Data Buffer
+ *
+ */
+VOID
+WriteEC8 (
+ IN UINT8 Address,
+ IN UINT8* Value
+ )
+{
+ UINT16 dwEcIndexPort;
+
+ ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
+ dwEcIndexPort &= ~(BIT0);
+
+ WriteIO (dwEcIndexPort, AccWidthUint8, &Address);
+ WriteIO (dwEcIndexPort + 1, AccWidthUint8, Value);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * RWEC8 - Read/Write EC register
+ *
+ *
+ *
+ * @param[in] Address - EC Register Offset Value
+ * @param[in] AndMask - Data And Mask 8 bits
+ * @param[in] OrMask - Data OR Mask 8 bits
+ *
+ */
+VOID
+RWEC8 (
+ IN UINT8 Address,
+ IN UINT8 AndMask,
+ IN UINT8 OrMask
+ )
+{
+ UINT8 Result;
+ ReadEC8 (Address, &Result);
+ Result = (Result & AndMask) | OrMask;
+ WriteEC8 (Address, &Result);
+}
+
+// #endif
+
diff --git a/src/vendorcode/amd/cimx/sb800/GEC.c b/src/vendorcode/amd/cimx/sb800/GEC.c
deleted file mode 100644
index d1715bc..0000000
--- a/src/vendorcode/amd/cimx/sb800/GEC.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/**
- * @file
- *
- * Config Southbridge GEC controller
- *
- * Init GEC features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: CIMx-SB
- * @e sub-project:
- * @e \$Revision:$ @e \$Date:$
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "SBPLATFORM.h"
-#include "cbtypes.h"
-
-/**
- * gecInitBeforePciEnum - Config GEC controller before PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-gecInitBeforePciEnum (
- IN AMDSBCFG* pConfig
- )
-{
- UINT8 cimSBGecDebugBus;
- UINT8 cimSBGecPwr;
-
- cimSBGecDebugBus = (UINT8) pConfig->SBGecDebugBus;
- cimSBGecPwr = (UINT8) pConfig->SBGecPwr;
-#if SB_CIMx_PARAMETER == 0
- cimSBGecDebugBus = cimSBGecDebugBusDefault;
- cimSBGecPwr = cimSBGecPwrDefault;
-#endif
- if ( pConfig->GecConfig == 0) {
- // GEC Enabled
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT0, 0x00);
- RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GEVENT_REG11, AccWidthUint8, 0, 0x00);
- RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GEVENT_REG21, AccWidthUint8, 0, 0x01);
- RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG166, AccWidthUint8, 0, 0x01);
- //RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG181, AccWidthUint8, 0, 0x01);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF8, AccWidthUint8, ~(BIT5 + BIT6), (UINT8) ((cimSBGecPwr) << 5));
- } else {
- // GEC Disabled
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT0, BIT0);
- return; //return if GEC controller is disabled.
- }
- if ( cimSBGecDebugBus == 1) {
- // GEC Debug Bus Enabled
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT3, BIT3);
- } else {
- // GEC Debug Bus Disabled
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT3, 0x00);
- }
-}
-
-/**
- * gecInitAfterPciEnum - Config GEC controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-gecInitAfterPciEnum (
- IN AMDSBCFG* pConfig
- )
-{
- VOID* GecRomAddress;
- VOID* GecShadowRomAddress;
- UINT32 ddTemp;
- UINT8 dbVar;
- UINT8 dbTemp;
- if ( pConfig->GecConfig == 0) {
- dbVar = 0;
- ReadPCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbVar);
- dbTemp = 0x07;
- WritePCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbTemp);
- if ( pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr != NULL ) {
- GecRomAddress = pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr;
- GecShadowRomAddress = (VOID*) (UINTN) pConfig->BuildParameters.GecShadowRomBase;
- AmdSbCopyMem (GecShadowRomAddress, GecRomAddress, 0x100);
- ReadPCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG10, AccWidthUint32, &ddTemp);
- ddTemp = ddTemp & 0xFFFFFFF0;
- RWMEM (ddTemp + 0x6804, AccWidthUint32, 0, BIT0 + BIT29);
- }
- WritePCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbVar);
- }
-}
-
-/**
- * gecInitLatePost - Prepare GEC controller to boot to OS.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-gecInitLatePost (
- IN AMDSBCFG* pConfig
- )
-{
- if ( !pConfig->GecConfig == 0) {
- return; //return if GEC controller is disabled.
- }
-}
-
-
diff --git a/src/vendorcode/amd/cimx/sb800/Gec.c b/src/vendorcode/amd/cimx/sb800/Gec.c
new file mode 100644
index 0000000..d1715bc
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/Gec.c
@@ -0,0 +1,145 @@
+/**
+ * @file
+ *
+ * Config Southbridge GEC controller
+ *
+ * Init GEC features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$ @e \$Date:$
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "SBPLATFORM.h"
+#include "cbtypes.h"
+
+/**
+ * gecInitBeforePciEnum - Config GEC controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+gecInitBeforePciEnum (
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT8 cimSBGecDebugBus;
+ UINT8 cimSBGecPwr;
+
+ cimSBGecDebugBus = (UINT8) pConfig->SBGecDebugBus;
+ cimSBGecPwr = (UINT8) pConfig->SBGecPwr;
+#if SB_CIMx_PARAMETER == 0
+ cimSBGecDebugBus = cimSBGecDebugBusDefault;
+ cimSBGecPwr = cimSBGecPwrDefault;
+#endif
+ if ( pConfig->GecConfig == 0) {
+ // GEC Enabled
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT0, 0x00);
+ RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GEVENT_REG11, AccWidthUint8, 0, 0x00);
+ RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GEVENT_REG21, AccWidthUint8, 0, 0x01);
+ RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG166, AccWidthUint8, 0, 0x01);
+ //RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG181, AccWidthUint8, 0, 0x01);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF8, AccWidthUint8, ~(BIT5 + BIT6), (UINT8) ((cimSBGecPwr) << 5));
+ } else {
+ // GEC Disabled
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT0, BIT0);
+ return; //return if GEC controller is disabled.
+ }
+ if ( cimSBGecDebugBus == 1) {
+ // GEC Debug Bus Enabled
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT3, BIT3);
+ } else {
+ // GEC Debug Bus Disabled
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT3, 0x00);
+ }
+}
+
+/**
+ * gecInitAfterPciEnum - Config GEC controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+gecInitAfterPciEnum (
+ IN AMDSBCFG* pConfig
+ )
+{
+ VOID* GecRomAddress;
+ VOID* GecShadowRomAddress;
+ UINT32 ddTemp;
+ UINT8 dbVar;
+ UINT8 dbTemp;
+ if ( pConfig->GecConfig == 0) {
+ dbVar = 0;
+ ReadPCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbVar);
+ dbTemp = 0x07;
+ WritePCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbTemp);
+ if ( pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr != NULL ) {
+ GecRomAddress = pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr;
+ GecShadowRomAddress = (VOID*) (UINTN) pConfig->BuildParameters.GecShadowRomBase;
+ AmdSbCopyMem (GecShadowRomAddress, GecRomAddress, 0x100);
+ ReadPCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG10, AccWidthUint32, &ddTemp);
+ ddTemp = ddTemp & 0xFFFFFFF0;
+ RWMEM (ddTemp + 0x6804, AccWidthUint32, 0, BIT0 + BIT29);
+ }
+ WritePCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbVar);
+ }
+}
+
+/**
+ * gecInitLatePost - Prepare GEC controller to boot to OS.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+gecInitLatePost (
+ IN AMDSBCFG* pConfig
+ )
+{
+ if ( !pConfig->GecConfig == 0) {
+ return; //return if GEC controller is disabled.
+ }
+}
+
+
diff --git a/src/vendorcode/amd/cimx/sb800/IOLIB.c b/src/vendorcode/amd/cimx/sb800/IOLIB.c
deleted file mode 100644
index 1d21d9c..0000000
--- a/src/vendorcode/amd/cimx/sb800/IOLIB.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "SBPLATFORM.h"
-#include "cbtypes.h"
-
-
-VOID
-ReadIO (
- IN UINT16 Address,
- IN UINT8 OpFlag,
- IN VOID* Value
- )
-{
- OpFlag = OpFlag & 0x7f;
- switch ( OpFlag ) {
- case AccWidthUint8:
- *(UINT8*)Value = ReadIo8 (Address);
- break;
- case AccWidthUint16:
- *(UINT16*)Value = ReadIo16 (Address);
- break;
- case AccWidthUint32:
- *(UINT32*)Value = ReadIo32 (Address);
- break;
- }
-}
-
-VOID
-WriteIO (
- IN UINT16 Address,
- IN UINT8 OpFlag,
- IN VOID* Value
- )
-{
- OpFlag = OpFlag & 0x7f;
- switch ( OpFlag ) {
- case AccWidthUint8:
- WriteIo8 (Address, *(UINT8*)Value);
- break;
- case AccWidthUint16:
- WriteIo16 (Address, *(UINT16*)Value);
- break;
- case AccWidthUint32:
- WriteIo32 (Address, *(UINT32*)Value);
- break;
- }
-}
-
-VOID
-RWIO (
- IN UINT16 Address,
- IN UINT8 OpFlag,
- IN UINT32 Mask,
- IN UINT32 Data
- )
-{
- UINT32 Result;
- ReadIO (Address, OpFlag, &Result);
- Result = (Result & Mask) | Data;
- WriteIO (Address, OpFlag, &Result);
-}
diff --git a/src/vendorcode/amd/cimx/sb800/IoLib.c b/src/vendorcode/amd/cimx/sb800/IoLib.c
new file mode 100644
index 0000000..1d21d9c
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/IoLib.c
@@ -0,0 +1,91 @@
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "SBPLATFORM.h"
+#include "cbtypes.h"
+
+
+VOID
+ReadIO (
+ IN UINT16 Address,
+ IN UINT8 OpFlag,
+ IN VOID* Value
+ )
+{
+ OpFlag = OpFlag & 0x7f;
+ switch ( OpFlag ) {
+ case AccWidthUint8:
+ *(UINT8*)Value = ReadIo8 (Address);
+ break;
+ case AccWidthUint16:
+ *(UINT16*)Value = ReadIo16 (Address);
+ break;
+ case AccWidthUint32:
+ *(UINT32*)Value = ReadIo32 (Address);
+ break;
+ }
+}
+
+VOID
+WriteIO (
+ IN UINT16 Address,
+ IN UINT8 OpFlag,
+ IN VOID* Value
+ )
+{
+ OpFlag = OpFlag & 0x7f;
+ switch ( OpFlag ) {
+ case AccWidthUint8:
+ WriteIo8 (Address, *(UINT8*)Value);
+ break;
+ case AccWidthUint16:
+ WriteIo16 (Address, *(UINT16*)Value);
+ break;
+ case AccWidthUint32:
+ WriteIo32 (Address, *(UINT32*)Value);
+ break;
+ }
+}
+
+VOID
+RWIO (
+ IN UINT16 Address,
+ IN UINT8 OpFlag,
+ IN UINT32 Mask,
+ IN UINT32 Data
+ )
+{
+ UINT32 Result;
+ ReadIO (Address, OpFlag, &Result);
+ Result = (Result & Mask) | Data;
+ WriteIO (Address, OpFlag, &Result);
+}
diff --git a/src/vendorcode/amd/cimx/sb800/LEGACY.c b/src/vendorcode/amd/cimx/sb800/LEGACY.c
deleted file mode 100644
index f95006f..0000000
--- a/src/vendorcode/amd/cimx/sb800/LEGACY.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "SBPLATFORM.h"
-#include "cbtypes.h"
-
-UINT32
-GetFixUp (
- OUT VOID
- )
-{
- AMD_CONFIG_PARAMS* Result;
- Result = (AMD_CONFIG_PARAMS*) getConfigPointer ();
- if ( Result->ImageBasePtr > 0x100000 && Result->ImageBasePtr < 0xFF000000 ) {
- return 0;
- }
- return Result->ImageBasePtr;
-}
diff --git a/src/vendorcode/amd/cimx/sb800/Legacy.c b/src/vendorcode/amd/cimx/sb800/Legacy.c
new file mode 100644
index 0000000..f95006f
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/Legacy.c
@@ -0,0 +1,47 @@
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "SBPLATFORM.h"
+#include "cbtypes.h"
+
+UINT32
+GetFixUp (
+ OUT VOID
+ )
+{
+ AMD_CONFIG_PARAMS* Result;
+ Result = (AMD_CONFIG_PARAMS*) getConfigPointer ();
+ if ( Result->ImageBasePtr > 0x100000 && Result->ImageBasePtr < 0xFF000000 ) {
+ return 0;
+ }
+ return Result->ImageBasePtr;
+}
diff --git a/src/vendorcode/amd/cimx/sb800/MEMLIB.c b/src/vendorcode/amd/cimx/sb800/MEMLIB.c
deleted file mode 100644
index 5531c62..0000000
--- a/src/vendorcode/amd/cimx/sb800/MEMLIB.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "SBPLATFORM.h"
-#include "cbtypes.h"
-
-VOID
-ReadMEM (
- IN UINT32 Address,
- IN UINT8 OpFlag,
- IN VOID* Value
- )
-{
- OpFlag = OpFlag & 0x7f;
- switch ( OpFlag ) {
- case AccWidthUint8:
- *((UINT8*)Value) = *((UINT8*) ((UINTN)Address));
- break;
- case AccWidthUint16:
- //*((UINT16*)Value) = *((UINT16*) ((UINTN)Address)); //gcc break strict-aliasing rules
- *((UINT8*)Value) = *((UINT8*) ((UINTN)Address));
- *((UINT8*)Value + 1) = *((UINT8*)((UINTN)Address) + 1);
- break;
- case AccWidthUint32:
- *((UINT32*)Value) = *((UINT32*) ((UINTN)Address));
- break;
- }
-}
-
-VOID
-WriteMEM (
- IN UINT32 Address,
- IN UINT8 OpFlag,
- IN VOID* Value
- )
-{
- OpFlag = OpFlag & 0x7f;
- switch ( OpFlag ) {
- case AccWidthUint8 :
- *((UINT8*) ((UINTN)Address)) = *((UINT8*)Value);
- break;
- case AccWidthUint16:
- //*((UINT16*) ((UINTN)Address)) = *((UINT16*)Value); //gcc break strict-aliasing rules
- *((UINT8*)((UINTN)Address)) = *((UINT8*)Value);
- *((UINT8*)((UINTN)Address) + 1) = *((UINT8*)Value + 1);
- break;
- case AccWidthUint32:
- *((UINT32*) ((UINTN)Address)) = *((UINT32*)Value);
- break;
- }
-}
-
-VOID
-RWMEM (
- IN UINT32 Address,
- IN UINT8 OpFlag,
- IN UINT32 Mask,
- IN UINT32 Data
- )
-{
- UINT32 Result;
- ReadMEM (Address, OpFlag, &Result);
- Result = (Result & Mask) | Data;
- WriteMEM (Address, OpFlag, &Result);
-}
-
-
diff --git a/src/vendorcode/amd/cimx/sb800/Makefile.inc b/src/vendorcode/amd/cimx/sb800/Makefile.inc
index fde6239..9871af1 100644
--- a/src/vendorcode/amd/cimx/sb800/Makefile.inc
+++ b/src/vendorcode/amd/cimx/sb800/Makefile.inc
@@ -27,52 +27,52 @@ CPPFLAGS_x86_64 += -I$(src)/southbridge/amd/cimx/sb800
CPPFLAGS_x86_64 += -I$(src)/include/cpu/amd/common
CPPFLAGS_x86_64 += -I$(src)/vendorcode/amd/cimx/sb800
-romstage-y += ACPILIB.c
-romstage-y += AZALIA.c
-romstage-y += DISPATCHER.c
-romstage-y += ECfanc.c
-romstage-y += ECfanLIB.c
-romstage-y += GEC.c
+romstage-y += AcpiLib.c
+romstage-y += Azalia.c
+romstage-y += Dispatcher.c
+romstage-y += EcFanc.c
+romstage-y += EcFanLib.c
+romstage-y += Gec.c
romstage-y += Gpp.c
-romstage-y += PMIO2LIB.c
-romstage-y += SATA.c
-romstage-y += SBCMN.c
-romstage-y += SBMAIN.c
-romstage-y += SBPort.c
-romstage-y += MEMLIB.c
-romstage-y += PCILIB.c
-romstage-y += IOLIB.c
-romstage-y += PMIOLIB.c
-romstage-y += AMDLIB.c
-romstage-y += SBPELIB.c
-romstage-y += AMDSBLIB.c
-romstage-y += ECLIB.c
-romstage-y += EC.c
-romstage-y += SMM.c
-romstage-y += USB.c
+romstage-y += Pmio2Lib.c
+romstage-y += Sata.c
+romstage-y += SbCmn.c
+romstage-y += SbMain.c
+romstage-y += SbPort.c
+romstage-y += MemLib.c
+romstage-y += PcoLib.c
+romstage-y += IoLib.c
+romstage-y += PmioLib.c
+romstage-y += AmdLib.c
+romstage-y += SbPeLib.c
+romstage-y += AmdSbLib.c
+romstage-y += EcLib.c
+romstage-y += Ec.c
+romstage-y += Smm.c
+romstage-y += Usb.c
-ramstage-y += ACPILIB.c
-ramstage-y += AZALIA.c
-ramstage-y += DISPATCHER.c
+ramstage-y += AcpiLib.c
+ramstage-y += Azalia.c
+ramstage-y += Dispatcher.c
ramstage-y += ECfanc.c
ramstage-y += ECfanLIB.c
-ramstage-y += GEC.c
+ramstage-y += Gec.c
ramstage-y += Gpp.c
-ramstage-y += PMIO2LIB.c
-ramstage-y += SATA.c
-ramstage-y += SBCMN.c
-ramstage-y += SBMAIN.c
-ramstage-y += SBPort.c
-ramstage-y += MEMLIB.c
-ramstage-y += PCILIB.c
-ramstage-y += IOLIB.c
-ramstage-y += PMIOLIB.c
-ramstage-y += AMDLIB.c
-ramstage-y += SBPELIB.c
-ramstage-y += AMDSBLIB.c
-ramstage-y += ECLIB.c
-ramstage-y += EC.c
-ramstage-y += SMM.c
-ramstage-y += USB.c
-#ramstage-y += LEGACY.c
+ramstage-y += Pmio2Lib.c
+ramstage-y += Sata.c
+ramstage-y += SbCmn.c
+ramstage-y += SbMain.c
+ramstage-y += SbPort.c
+ramstage-y += MemLib.c
+ramstage-y += PciLib.c
+ramstage-y += IoLib.c
+ramstage-y += PmioLib.c
+ramstage-y += AmdLib.c
+ramstage-y += SbPeLib.c
+ramstage-y += AmdSbLib.c
+ramstage-y += EcLib.c
+ramstage-y += Ec.c
+ramstage-y += Smm.c
+ramstage-y += Usb.c
+#ramstage-y += Legacy.c
#ramstage-y += SbModInf.c
diff --git a/src/vendorcode/amd/cimx/sb800/MemLib.c b/src/vendorcode/amd/cimx/sb800/MemLib.c
new file mode 100644
index 0000000..5531c62
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/MemLib.c
@@ -0,0 +1,96 @@
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "SBPLATFORM.h"
+#include "cbtypes.h"
+
+VOID
+ReadMEM (
+ IN UINT32 Address,
+ IN UINT8 OpFlag,
+ IN VOID* Value
+ )
+{
+ OpFlag = OpFlag & 0x7f;
+ switch ( OpFlag ) {
+ case AccWidthUint8:
+ *((UINT8*)Value) = *((UINT8*) ((UINTN)Address));
+ break;
+ case AccWidthUint16:
+ //*((UINT16*)Value) = *((UINT16*) ((UINTN)Address)); //gcc break strict-aliasing rules
+ *((UINT8*)Value) = *((UINT8*) ((UINTN)Address));
+ *((UINT8*)Value + 1) = *((UINT8*)((UINTN)Address) + 1);
+ break;
+ case AccWidthUint32:
+ *((UINT32*)Value) = *((UINT32*) ((UINTN)Address));
+ break;
+ }
+}
+
+VOID
+WriteMEM (
+ IN UINT32 Address,
+ IN UINT8 OpFlag,
+ IN VOID* Value
+ )
+{
+ OpFlag = OpFlag & 0x7f;
+ switch ( OpFlag ) {
+ case AccWidthUint8 :
+ *((UINT8*) ((UINTN)Address)) = *((UINT8*)Value);
+ break;
+ case AccWidthUint16:
+ //*((UINT16*) ((UINTN)Address)) = *((UINT16*)Value); //gcc break strict-aliasing rules
+ *((UINT8*)((UINTN)Address)) = *((UINT8*)Value);
+ *((UINT8*)((UINTN)Address) + 1) = *((UINT8*)Value + 1);
+ break;
+ case AccWidthUint32:
+ *((UINT32*) ((UINTN)Address)) = *((UINT32*)Value);
+ break;
+ }
+}
+
+VOID
+RWMEM (
+ IN UINT32 Address,
+ IN UINT8 OpFlag,
+ IN UINT32 Mask,
+ IN UINT32 Data
+ )
+{
+ UINT32 Result;
+ ReadMEM (Address, OpFlag, &Result);
+ Result = (Result & Mask) | Data;
+ WriteMEM (Address, OpFlag, &Result);
+}
+
+
diff --git a/src/vendorcode/amd/cimx/sb800/PCILIB.c b/src/vendorcode/amd/cimx/sb800/PCILIB.c
deleted file mode 100644
index 01be81a..0000000
--- a/src/vendorcode/amd/cimx/sb800/PCILIB.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-#include "SBPLATFORM.h"
-#include "cbtypes.h"
-
-VOID
-ReadPCI (
- IN UINT32 Address,
- IN UINT8 OpFlag,
- IN VOID* Value
- )
-{
- OpFlag = OpFlag & 0x7f;
-
- if ( (UINT16)Address < 0xff ) {
- //Normal Config Access
- UINT32 AddrCf8;
- AddrCf8 = (1 << 31) + ((Address >> 8) & 0x0FFFF00) + (Address & 0xFC);
- WriteIO (0xCf8, AccWidthUint32, &AddrCf8);
- ReadIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value);
- }
-}
-
-VOID
-WritePCI (
- IN UINT32 Address,
- IN UINT8 OpFlag,
- IN VOID* Value
- )
-{
- OpFlag = OpFlag & 0x7f;
- if ( (UINT16)Address < 0xff ) {
- //Normal Config Access
- UINT32 AddrCf8;
- AddrCf8 = (1 << 31) + ((Address >> 8)&0x0FFFF00) + (Address & 0xFC);
- WriteIO (0xCf8, AccWidthUint32, &AddrCf8);
- WriteIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value);
- }
-}
-
-VOID
-RWPCI (
- IN UINT32 Address,
- IN UINT8 OpFlag,
- IN UINT32 Mask,
- IN UINT32 Data
- )
-{
- UINT32 Result;
- Result = 0;
- OpFlag = OpFlag & 0x7f;
- ReadPCI (Address, OpFlag, &Result);
- Result = (Result & Mask) | Data;
- WritePCI (Address, OpFlag, &Result);
-}
diff --git a/src/vendorcode/amd/cimx/sb800/PMIO2LIB.c b/src/vendorcode/amd/cimx/sb800/PMIO2LIB.c
deleted file mode 100644
index 82864e6..0000000
--- a/src/vendorcode/amd/cimx/sb800/PMIO2LIB.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/**
- * @file
- *
- * Southbridge PMIO2 access common routine
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "SBPLATFORM.h"
-#include "cbtypes.h"
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read PMIO2
- *
- *
- *
- * @param[in] Address - PMIO2 Offset value
- * @param[in] OpFlag - Access sizes
- * @param[in] Value - Read Data Buffer
- *
- */
-VOID
-ReadPMIO2 (
- IN UINT8 Address,
- IN UINT8 OpFlag,
- IN VOID* Value
- )
-{
- UINT8 i;
- OpFlag = OpFlag & 0x7f;
-
- if ( OpFlag == 0x02 ) {
- OpFlag = 0x03;
- }
- for ( i = 0; i <= OpFlag; i++ ) {
- WriteIO (0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0
- Address++;
- ReadIO (0xCD1, AccWidthUint8, (UINT8 *) Value + i); // SB_IOMAP_REGCD1
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Write PMIO 2
- *
- *
- *
- * @param[in] Address - PMIO2 Offset value
- * @param[in] OpFlag - Access sizes
- * @param[in] Value - Write Data Buffer
- *
- */
-VOID
-WritePMIO2 (
- IN UINT8 Address,
- IN UINT8 OpFlag,
- IN VOID* Value
- )
-{
- UINT8 i;
- OpFlag = OpFlag & 0x7f;
-
- if ( OpFlag == 0x02 ) {
- OpFlag = 0x03;
- }
- for ( i = 0; i <= OpFlag; i++ ) {
- WriteIO (0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0
- Address++;
- WriteIO (0xCD1, AccWidthUint8, (UINT8 *)Value + i); // SB_IOMAP_REGCD1
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * RWPMIO2 - Read/Write PMIO2
- *
- *
- *
- * @param[in] Address - PMIO2 Offset value
- * @param[in] OpFlag - Access sizes
- * @param[in] AndMask - Data And Mask 32 bits
- * @param[in] OrMask - Data OR Mask 32 bits
- *
- */
-VOID
-RWPMIO2 (
- IN UINT8 Address,
- IN UINT8 OpFlag,
- IN UINT32 AndMask,
- IN UINT32 OrMask
- )
-{
- UINT32 Result;
- OpFlag = OpFlag & 0x7f;
- ReadPMIO2 (Address, OpFlag, &Result);
- Result = (Result & AndMask) | OrMask;
- WritePMIO2 (Address, OpFlag, &Result);
-}
diff --git a/src/vendorcode/amd/cimx/sb800/PMIOLIB.c b/src/vendorcode/amd/cimx/sb800/PMIOLIB.c
deleted file mode 100644
index 6cce4f1..0000000
--- a/src/vendorcode/amd/cimx/sb800/PMIOLIB.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/**
- * @file
- *
- * Southbridge PMIO access common routine
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "SBPLATFORM.h"
-#include "cbtypes.h"
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read PMIO
- *
- *
- *
- * @param[in] Address - PMIO Offset value
- * @param[in] OpFlag - Access sizes
- * @param[in] Value - Read Data Buffer
- *
- */
-VOID
-ReadPMIO (
- IN UINT8 Address,
- IN UINT8 OpFlag,
- IN VOID* Value
- )
-{
- UINT8 i;
- OpFlag = OpFlag & 0x7f;
-
- if ( OpFlag == 0x02 ) {
- OpFlag = 0x03;
- }
- for ( i = 0; i <= OpFlag; i++ ) {
- WriteIO (0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6
- Address++;
- ReadIO (0xCD7, AccWidthUint8, (UINT8 *)Value + i); // SB_IOMAP_REGCD7
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Write PMIO
- *
- *
- *
- * @param[in] Address - PMIO Offset value
- * @param[in] OpFlag - Access sizes
- * @param[in] Value - Write Data Buffer
- *
- */
-VOID
-WritePMIO (
- IN UINT8 Address,
- IN UINT8 OpFlag,
- IN VOID* Value
- )
-{
- UINT8 i;
- OpFlag = OpFlag & 0x7f;
-
- if ( OpFlag == 0x02 ) {
- OpFlag = 0x03;
- }
- for ( i = 0; i <= OpFlag; i++ ) {
- WriteIO (0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6
- Address++;
- WriteIO (0xCD7, AccWidthUint8, (UINT8 *)Value + i); // SB_IOMAP_REGCD7
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * RWPMIO - Read/Write PMIO
- *
- *
- *
- * @param[in] Address - PMIO Offset value
- * @param[in] OpFlag - Access sizes
- * @param[in] AndMask - Data And Mask 32 bits
- * @param[in] OrMask - Data OR Mask 32 bits
- *
- */
-VOID
-RWPMIO (
- IN UINT8 Address,
- IN UINT8 OpFlag,
- IN UINT32 AndMask,
- IN UINT32 OrMask
- )
-{
- UINT32 Result;
- OpFlag = OpFlag & 0x7f;
- ReadPMIO (Address, OpFlag, &Result);
- Result = (Result & AndMask) | OrMask;
- WritePMIO (Address, OpFlag, &Result);
-}
diff --git a/src/vendorcode/amd/cimx/sb800/PciLib.c b/src/vendorcode/amd/cimx/sb800/PciLib.c
new file mode 100644
index 0000000..01be81a
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/PciLib.c
@@ -0,0 +1,86 @@
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+
+#include "SBPLATFORM.h"
+#include "cbtypes.h"
+
+VOID
+ReadPCI (
+ IN UINT32 Address,
+ IN UINT8 OpFlag,
+ IN VOID* Value
+ )
+{
+ OpFlag = OpFlag & 0x7f;
+
+ if ( (UINT16)Address < 0xff ) {
+ //Normal Config Access
+ UINT32 AddrCf8;
+ AddrCf8 = (1 << 31) + ((Address >> 8) & 0x0FFFF00) + (Address & 0xFC);
+ WriteIO (0xCf8, AccWidthUint32, &AddrCf8);
+ ReadIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value);
+ }
+}
+
+VOID
+WritePCI (
+ IN UINT32 Address,
+ IN UINT8 OpFlag,
+ IN VOID* Value
+ )
+{
+ OpFlag = OpFlag & 0x7f;
+ if ( (UINT16)Address < 0xff ) {
+ //Normal Config Access
+ UINT32 AddrCf8;
+ AddrCf8 = (1 << 31) + ((Address >> 8)&0x0FFFF00) + (Address & 0xFC);
+ WriteIO (0xCf8, AccWidthUint32, &AddrCf8);
+ WriteIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value);
+ }
+}
+
+VOID
+RWPCI (
+ IN UINT32 Address,
+ IN UINT8 OpFlag,
+ IN UINT32 Mask,
+ IN UINT32 Data
+ )
+{
+ UINT32 Result;
+ Result = 0;
+ OpFlag = OpFlag & 0x7f;
+ ReadPCI (Address, OpFlag, &Result);
+ Result = (Result & Mask) | Data;
+ WritePCI (Address, OpFlag, &Result);
+}
diff --git a/src/vendorcode/amd/cimx/sb800/Pmio2Lib.c b/src/vendorcode/amd/cimx/sb800/Pmio2Lib.c
new file mode 100644
index 0000000..82864e6
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/Pmio2Lib.c
@@ -0,0 +1,130 @@
+/**
+ * @file
+ *
+ * Southbridge PMIO2 access common routine
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "SBPLATFORM.h"
+#include "cbtypes.h"
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read PMIO2
+ *
+ *
+ *
+ * @param[in] Address - PMIO2 Offset value
+ * @param[in] OpFlag - Access sizes
+ * @param[in] Value - Read Data Buffer
+ *
+ */
+VOID
+ReadPMIO2 (
+ IN UINT8 Address,
+ IN UINT8 OpFlag,
+ IN VOID* Value
+ )
+{
+ UINT8 i;
+ OpFlag = OpFlag & 0x7f;
+
+ if ( OpFlag == 0x02 ) {
+ OpFlag = 0x03;
+ }
+ for ( i = 0; i <= OpFlag; i++ ) {
+ WriteIO (0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0
+ Address++;
+ ReadIO (0xCD1, AccWidthUint8, (UINT8 *) Value + i); // SB_IOMAP_REGCD1
+ }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PMIO 2
+ *
+ *
+ *
+ * @param[in] Address - PMIO2 Offset value
+ * @param[in] OpFlag - Access sizes
+ * @param[in] Value - Write Data Buffer
+ *
+ */
+VOID
+WritePMIO2 (
+ IN UINT8 Address,
+ IN UINT8 OpFlag,
+ IN VOID* Value
+ )
+{
+ UINT8 i;
+ OpFlag = OpFlag & 0x7f;
+
+ if ( OpFlag == 0x02 ) {
+ OpFlag = 0x03;
+ }
+ for ( i = 0; i <= OpFlag; i++ ) {
+ WriteIO (0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0
+ Address++;
+ WriteIO (0xCD1, AccWidthUint8, (UINT8 *)Value + i); // SB_IOMAP_REGCD1
+ }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * RWPMIO2 - Read/Write PMIO2
+ *
+ *
+ *
+ * @param[in] Address - PMIO2 Offset value
+ * @param[in] OpFlag - Access sizes
+ * @param[in] AndMask - Data And Mask 32 bits
+ * @param[in] OrMask - Data OR Mask 32 bits
+ *
+ */
+VOID
+RWPMIO2 (
+ IN UINT8 Address,
+ IN UINT8 OpFlag,
+ IN UINT32 AndMask,
+ IN UINT32 OrMask
+ )
+{
+ UINT32 Result;
+ OpFlag = OpFlag & 0x7f;
+ ReadPMIO2 (Address, OpFlag, &Result);
+ Result = (Result & AndMask) | OrMask;
+ WritePMIO2 (Address, OpFlag, &Result);
+}
diff --git a/src/vendorcode/amd/cimx/sb800/PmioLib.c b/src/vendorcode/amd/cimx/sb800/PmioLib.c
new file mode 100644
index 0000000..6cce4f1
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/PmioLib.c
@@ -0,0 +1,129 @@
+/**
+ * @file
+ *
+ * Southbridge PMIO access common routine
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "SBPLATFORM.h"
+#include "cbtypes.h"
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read PMIO
+ *
+ *
+ *
+ * @param[in] Address - PMIO Offset value
+ * @param[in] OpFlag - Access sizes
+ * @param[in] Value - Read Data Buffer
+ *
+ */
+VOID
+ReadPMIO (
+ IN UINT8 Address,
+ IN UINT8 OpFlag,
+ IN VOID* Value
+ )
+{
+ UINT8 i;
+ OpFlag = OpFlag & 0x7f;
+
+ if ( OpFlag == 0x02 ) {
+ OpFlag = 0x03;
+ }
+ for ( i = 0; i <= OpFlag; i++ ) {
+ WriteIO (0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6
+ Address++;
+ ReadIO (0xCD7, AccWidthUint8, (UINT8 *)Value + i); // SB_IOMAP_REGCD7
+ }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PMIO
+ *
+ *
+ *
+ * @param[in] Address - PMIO Offset value
+ * @param[in] OpFlag - Access sizes
+ * @param[in] Value - Write Data Buffer
+ *
+ */
+VOID
+WritePMIO (
+ IN UINT8 Address,
+ IN UINT8 OpFlag,
+ IN VOID* Value
+ )
+{
+ UINT8 i;
+ OpFlag = OpFlag & 0x7f;
+
+ if ( OpFlag == 0x02 ) {
+ OpFlag = 0x03;
+ }
+ for ( i = 0; i <= OpFlag; i++ ) {
+ WriteIO (0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6
+ Address++;
+ WriteIO (0xCD7, AccWidthUint8, (UINT8 *)Value + i); // SB_IOMAP_REGCD7
+ }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * RWPMIO - Read/Write PMIO
+ *
+ *
+ *
+ * @param[in] Address - PMIO Offset value
+ * @param[in] OpFlag - Access sizes
+ * @param[in] AndMask - Data And Mask 32 bits
+ * @param[in] OrMask - Data OR Mask 32 bits
+ *
+ */
+VOID
+RWPMIO (
+ IN UINT8 Address,
+ IN UINT8 OpFlag,
+ IN UINT32 AndMask,
+ IN UINT32 OrMask
+ )
+{
+ UINT32 Result;
+ OpFlag = OpFlag & 0x7f;
+ ReadPMIO (Address, OpFlag, &Result);
+ Result = (Result & AndMask) | OrMask;
+ WritePMIO (Address, OpFlag, &Result);
+}
diff --git a/src/vendorcode/amd/cimx/sb800/SATA.c b/src/vendorcode/amd/cimx/sb800/SATA.c
deleted file mode 100644
index c2f2162..0000000
--- a/src/vendorcode/amd/cimx/sb800/SATA.c
+++ /dev/null
@@ -1,675 +0,0 @@
-
-/**
- * @file
- *
- * Config Southbridge SATA controller
- *
- * Init SATA features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: CIMx-SB
- * @e sub-project:
- * @e \$Revision:$ @e \$Date:$
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "SBPLATFORM.h"
-#include "cbtypes.h"
-
-//
-// Declaration of local functions
-//
-VOID sataSetIrqIntResource (IN AMDSBCFG* pConfig);
-VOID sataBar5setting (IN AMDSBCFG* pConfig, IN UINT32 *pBar5);
-VOID shutdownUnconnectedSataPortClock (IN AMDSBCFG* pConfig, IN UINT32 ddBar5);
-VOID sataDriveDetection (IN AMDSBCFG* pConfig, IN UINT32 *pBar5);
-
-/**
- * sataSetIrqIntResource - Config SATA IRQ/INT# resource
- *
- *
- * - Private function
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-sataSetIrqIntResource (
- IN AMDSBCFG* pConfig
- )
-{
- UINT8 dbValue;
- // IRQ14/IRQ15 come from IDE or SATA
- dbValue = 0x08;
- WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue);
- ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
- dbValue = dbValue & 0x0F;
- if (pConfig->SataClass == 3) {
- dbValue = dbValue | 0x50;
- } else {
- if (pConfig->SataIdeMode == 1) {
- // Both IDE & SATA set to Native mode
- dbValue = dbValue | 0xF0;
- }
- }
- WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
-}
-
-/**
- * sataBar5setting - Config SATA BAR5
- *
- * - Private function
- *
- * @param[in] pConfig - Southbridge configuration structure pointer.
- * @param[in] *pBar5 - SATA BAR5 buffer.
- *
- */
-VOID
-sataBar5setting (
- IN AMDSBCFG* pConfig,
- IN UINT32 *pBar5
- )
-{
- //Get BAR5 value
- ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, pBar5);
- //Assign temporary BAR if is not already assigned
- if ( (*pBar5 == 0) || (*pBar5 == - 1) ) {
- //assign temporary BAR5
- if ( (pConfig->TempMMIO == 0) || (pConfig->TempMMIO == - 1) ) {
- *pBar5 = 0xFEC01000;
- } else {
- *pBar5 = pConfig->TempMMIO;
- }
- WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, pBar5);
- }
- //Clear Bits 9:0
- *pBar5 = *pBar5 & 0xFFFFFC00;
-}
-/**
- * shutdownUnconnectedSataPortClock - Shutdown unconnected Sata port clock
- *
- * - Private function
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- * @param[in] ddBar5 Sata BAR5 base address.
- *
- */
-VOID
-shutdownUnconnectedSataPortClock (
- IN AMDSBCFG* pConfig,
- IN UINT32 ddBar5
- )
-{
- UINT8 dbPortNum;
- UINT8 dbPortSataStatus;
- UINT8 NumOfPorts;
- UINT8 cimSataClkAutoOff;
-
- cimSataClkAutoOff = (UINT8) pConfig->SataClkAutoOff;
-#if SB_CIMx_PARAMETER == 0
- cimSataClkAutoOff = cimSataClkAutoOffDefault;
-#endif
- NumOfPorts = 0;
- if ( cimSataClkAutoOff == TRUE ) {
- for ( dbPortNum = 0; dbPortNum < 6; dbPortNum++ ) {
- ReadMEM (ddBar5 + SB_SATA_BAR5_REG128 + (dbPortNum * 0x80), AccWidthUint8, &dbPortSataStatus);
- // Shutdown the clock for the port and do the necessary port reporting changes.
- // ?? Error port status should be 1 not 3
- if ( ((dbPortSataStatus & 0x0F) != 0x03) && (! ((pConfig->SataEspPort) & (1 << dbPortNum))) ) {
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, (1 << dbPortNum));
- RWMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, ~(1 << dbPortNum), 00);
- }
- } //end of for (dbPortNum=0;dbPortNum<6;dbPortNum++)
- ReadMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, &dbPortSataStatus);
- //if all ports are in disabled state, report atleast one port
- if ( (dbPortSataStatus & 0x3F) == 0) {
- RWMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, (UINT32) ~(0x3F), 01);
- }
- ReadMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, &dbPortSataStatus);
- for (dbPortNum = 0; dbPortNum < 6; dbPortNum ++) {
- if (dbPortSataStatus & (1 << dbPortNum)) {
- NumOfPorts++;
- }
- }
- if ( NumOfPorts == 0) {
- NumOfPorts = 0x01;
- }
- RWMEM (ddBar5 + SB_SATA_BAR5_REG00, AccWidthUint8, 0xE0, NumOfPorts - 1);
- } //end of SataClkAuto Off option
-}
-
-/**
- * Table for class code of SATA Controller in different modes
- *
- *
- *
- *
- */
-const static UINT32 sataIfCodeTable[] =
-{
- 0x01018F40, //sata class ID of IDE
- 0x01040040, //sata class ID of RAID
- 0x01060140, //sata class ID of AHCI
- 0x01018A40, //sata class ID of Legacy IDE
- 0x01018F40, //sata class ID of IDE to AHCI mode
-};
-
-/**
- * Table for device id of SATA Controller in different modes
- *
- *
- *
- *
- */
-const static UINT16 sataDeviceIDTable[] =
-{
- 0x4390, //sata device ID of IDE
- 0x4392, //sata device ID of RAID
- 0x4391, //sata class ID of AHCI
- 0x4390, //sata device ID of Legacy IDE
- 0x4390, //sata device ID of IDE->AHCI mode
-};
-
-/**
- * Table for Sata Phy Fine Setting
- *
- *
- *
- *
- */
-const static SATAPHYSETTING sataPhyTable[] =
-{
- {0x3006, 0x0056A607},
- {0x2006, 0x00061400},
- {0x1006, 0x00061302},
-
- {0x3206, 0x0056A607},
- {0x2206, 0x00061400},
- {0x1206, 0x00061302},
-
- {0x3406, 0x0056A607},
- {0x2406, 0x00061402},
- {0x1406, 0x00064300},
-
- {0x3606, 0x0056A607},
- {0x2606, 0x00061402},
- {0x1606, 0x00064300},
-
- {0x3806, 0x0056A700},
- {0x2806, 0x00061502},
- {0x1806, 0x00064302},
-
- {0x3A06, 0x0056A700},
- {0x2A06, 0x00061502},
- {0x1A06, 0x00064302}
-};
-
-/**
- * sataInitBeforePciEnum - Config SATA controller before PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-sataInitBeforePciEnum (
- IN AMDSBCFG* pConfig
- )
-{
- UINT32 ddTempVar;
- UINT32 ddValue;
- UINT32 *tempptr;
- UINT16 *pDeviceIdptr;
- UINT32 dwDeviceId;
- UINT8 dbValue;
- UINT8 pValue;
- UINT16 i;
- SATAPHYSETTING *pPhyTable;
-
- ddTempVar = 0;
- // BIT0 Enable write access to PCI header (reg 08h-0Bh) by setting SATA PCI register 40h
- // BIT4: Disable fast boot
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0 + BIT2 + BIT4);
- // BIT0 Enable write access to PCI header (reg 08h-0Bh) by setting IDE PCI register 40h
- RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0);
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8 | S3_SAVE, 0, pConfig->SataPortPower);
- dbValue = (UINT8)pConfig->SataClass;
- if (dbValue == AHCI_MODE_4394) {
- dbValue = AHCI_MODE;
- }
- if (dbValue == IDE_TO_AHCI_MODE_4394) {
- dbValue = IDE_TO_AHCI_MODE;
- }
- // Disable PATA MSI
- RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG34), AccWidthUint8 | S3_SAVE, 0x00, 0x00);
- RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG06), AccWidthUint8 | S3_SAVE, 0xEF, 0x00);
-
- // Get the appropriate class code from the table and write it to PCI register 08h-0Bh
- // Set the appropriate SATA class based on the input parameters
- // SATA IDE Controller Class ID & SSID
- tempptr = (UINT32 *) FIXUP_PTR (&sataIfCodeTable[0]);
- if ( (pConfig->SataIdeMode == 1) && (pConfig->SataClass != 3) ) {
- ddValue = tempptr[0];
- // Write the class code to IDE PCI register 08h-0Bh
- RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG08), AccWidthUint32 | S3_SAVE, 0, ddValue);
- }
- ddValue = tempptr[dbValue];
- // Write the class code to SATA PCI register 08h-0Bh
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, ddValue);
- if ( pConfig->SataClass == LEGACY_IDE_MODE ) {
- //Set PATA controller to native mode
- RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F);
- }
- if (pConfig->BuildParameters.IdeSsid != 0 ) {
- RWPCI ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.IdeSsid);
- }
- // SATA Controller Class ID & SSID
- pDeviceIdptr = (UINT16 *) FIXUP_PTR (&sataDeviceIDTable[0]);
- if ( pConfig->BuildParameters.SataIDESsid != 0 ) {
- ddTempVar = pConfig->BuildParameters.SataIDESsid;
- }
- dwDeviceId = pDeviceIdptr[dbValue];
- if ( pConfig->SataClass == RAID_MODE) {
- if ( pConfig->BuildParameters.SataRAID5Ssid != 0 ) {
- ddTempVar = pConfig->BuildParameters.SataRAID5Ssid;
- }
- dwDeviceId = V_SB_SATA_RAID5_DID;
- pValue = SATA_EFUSE_LOCATION;
- getEfuseStatus (&pValue);
- if (( pValue & SATA_EFUSE_BIT ) || ( pConfig->SataForceRaid == 1 )) {
- dwDeviceId = V_SB_SATA_RAID_DID;
- if ( pConfig->BuildParameters.SataRAIDSsid != 0 ) {
- ddTempVar = pConfig->BuildParameters.SataRAIDSsid;
- }
- }
- }
- if ( ((pConfig->SataClass) == AHCI_MODE) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE) ||
- ((pConfig->SataClass) == AHCI_MODE_4394) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE_4394) ) {
- if ( pConfig->BuildParameters.SataAHCISsid != 0 ) {
- ddTempVar = pConfig->BuildParameters.SataAHCISsid;
- }
- }
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, dwDeviceId);
- if ( ddTempVar != 0 ) {
- RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG2C, AccWidthUint32 | S3_SAVE, 0x00, ddTempVar);
- }
- // SATA IRQ Resource
- sataSetIrqIntResource (pConfig);
-
- // 8.4 SATA PHY Programming Sequence
- pPhyTable = (SATAPHYSETTING*)FIXUP_PTR (&sataPhyTable[0]);
- for (i = 0; i < (sizeof (sataPhyTable) / sizeof (SATAPHYSETTING)); i++) {
- RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG84, AccWidthUint16 | S3_SAVE, ~(BIT1 + BIT2 + BIT9 + BIT10 + BIT11 + BIT12 + BIT13 + BIT14), pPhyTable->wPhyCoreControl);
- RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG94, AccWidthUint32 | S3_SAVE, 0x00, pPhyTable->dwPhyFineTune);
- ++pPhyTable;
- }
-
-// CallBackToOEM (SATA_PHY_PROGRAMMING, NULL, pConfig);
-
- RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0);
- // Disable write access to PCI header
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0);
-}
-
-/**
- * sataInitAfterPciEnum - Config SATA controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-sataInitAfterPciEnum (
- IN AMDSBCFG* pConfig
- )
-{
- UINT32 ddAndMask;
- UINT32 ddOrMask;
- UINT32 ddBar5;
- UINT8 dbVar;
- UINT8 dbPortNum;
- UINT8 dbEfuse;
- UINT8 dbPortMode;
- UINT16 SataPortMode;
- UINT8 cimSataAggrLinkPmCap;
- UINT8 cimSataPortMultCap;
- UINT8 cimSataPscCap;
- UINT8 cimSataSscCap;
- UINT8 cimSataFisBasedSwitching;
- UINT8 cimSataCccSupport;
-
- cimSataAggrLinkPmCap = (UINT8) pConfig->SataAggrLinkPmCap;
- cimSataPortMultCap = (UINT8) pConfig->SataPortMultCap;
- cimSataPscCap = (UINT8) pConfig->SataPscCap;
- cimSataSscCap = (UINT8) pConfig->SataSscCap;
- cimSataFisBasedSwitching = (UINT8) pConfig->SataFisBasedSwitching;
- cimSataCccSupport = (UINT8) pConfig->SataCccSupport;
-
-#if SB_CIMx_PARAMETER == 0
- cimSataAggrLinkPmCap = cimSataAggrLinkPmCapDefault;
- cimSataPortMultCap = cimSataPortMultCapDefault;
- cimSataPscCap = cimSataPscCapDefault;
- cimSataSscCap = cimSataSscCapDefault;
- cimSataFisBasedSwitching = cimSataFisBasedSwitchingDefault;
- cimSataCccSupport = cimSataCccSupportDefault;
-#endif
-
- ddAndMask = 0;
- ddOrMask = 0;
- ddBar5 = 0;
- if ( pConfig->SATAMODE.SataMode.SataController == 0 ) {
- return; //return if SATA controller is disabled.
- }
-
- //Enable write access to pci header, pm capabilities
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
- //Disable AHCI Prefetch function
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8 | S3_SAVE, 0x7F, BIT7);
-
- sataBar5setting (pConfig, &ddBar5);
-
- ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8,0xFF, 0x03); //memory and io access enable
- dbEfuse = SATA_FIS_BASE_EFUSE_LOC;
- getEfuseStatus (&dbEfuse);
-
- if ( !cimSataPortMultCap ) {
- ddAndMask |= BIT12;
- }
- if ( cimSataAggrLinkPmCap ) {
- ddOrMask |= BIT11;
- } else {
- ddAndMask |= BIT11;
- }
- if ( cimSataPscCap ) {
- ddOrMask |= BIT1;
- }
- if ( cimSataSscCap ) {
- ddOrMask |= BIT26;
- }
- if ( cimSataFisBasedSwitching ) {
- if (dbEfuse & BIT1) {
- ddAndMask |= BIT10;
- } else {
- ddOrMask |= BIT10;
- }
- } else {
- ddAndMask |= BIT10;
- }
- // RPR 8.10 Disabling CCC (Command Completion Coalescing) support.
- if ( cimSataCccSupport ) {
- ddOrMask |= BIT19;
- } else {
- ddAndMask |= BIT19;
- }
- RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint32 | S3_SAVE, ~ddAndMask, ddOrMask);
-
-
- // SATA ESP port setting
- // These config bits are set for SATA driver to identify which ports are external SATA ports and need to
- // support hotplug. If a port is set as an external SATA port and need to support hotplug, then driver will
- // not enable power management (HIPM & DIPM) for these ports.
- if ( pConfig->SataEspPort != 0 ) {
- RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(pConfig->SataEspPort), 0);
- RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT12 + BIT13 + BIT14 + BIT15 + BIT16 + BIT17 + BIT5 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), (pConfig->SataEspPort << 12));
- // RPR 8.7 External SATA Port Indication Registers
- // If any of the ports was programmed as an external port, HCAP.SXS should also be set
- RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint32 | S3_SAVE, ~(BIT20), BIT20);
- } else {
- // RPR 8.7 External SATA Port Indication Registers
- // If any of the ports was programmed as an external port, HCAP.SXS should also be set (Clear for no ESP port)
- RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT5 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), 0x00);
- RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint32 | S3_SAVE, ~(BIT20), 0x00);
- }
- if ( cimSataFisBasedSwitching ) {
- if (dbEfuse & BIT1) {
- RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT22 + BIT23 + BIT24 + BIT25 + BIT26 + BIT27), 0x00);
- } else {
- RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT22 + BIT23 + BIT24 + BIT25 + BIT26 + BIT27), (BIT22 + BIT23 + BIT24 + BIT25 + BIT26 + BIT27));
- }
- } else {
- RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT22 + BIT23 + BIT24 + BIT25 + BIT26 + BIT27), 0x00);
- }
-
- // Disabled SATA MSI and D3 Power State capability
- // RPR 8.13 SATA MSI and D3 Power State Capability
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG34), AccWidthUint8 | S3_SAVE, 0, 0x70);
-
- if (((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE)) {
- // RAID or AHCI
- if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == SATA_IDE_COMBINE_DISABLE) {
- RWMEM ((ddBar5 + SB_SATA_BAR5_REG00), AccWidthUint8 | S3_SAVE, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT0);
- RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0xC0, 0x3F);
- // RPR 8.10 Disabling CCC (Command Completion Coalescing) support.
- // 8 messages
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2 + BIT1);
- } else {
- // RPR 8.10 Disabling CCC (Command Completion Coalescing) support.
- if ( pConfig->SataCccSupport ) {
- // 8 messages
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2 + BIT1);
- } else {
- // 4 messages
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2);
- }
- }
- }
-
- if ( pConfig->BIOSOSHandoff == 1 ) {
- RWMEM ((ddBar5 + SB_SATA_BAR5_REG24), AccWidthUint8 | S3_SAVE, ~BIT0, BIT0);
- } else {
- RWMEM ((ddBar5 + SB_SATA_BAR5_REG24), AccWidthUint8 | S3_SAVE, ~BIT0, 0x00);
- }
-
- SataPortMode = (UINT16)pConfig->SataPortMode;
- dbPortNum = 0;
- while ( dbPortNum < 6 ) {
- dbPortMode = (UINT8) (SataPortMode & 3);
- if ( (dbPortMode == BIT0) || (dbPortMode == BIT1) ) {
- if ( dbPortMode == BIT0 ) {
- // set GEN 1
- RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0x0F, 0x10);
- }
- if ( dbPortMode == BIT1 ) {
- // set GEN2 (default is GEN3)
- RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0x0F, 0x20);
- }
- RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFF, 0x01);
- }
- SataPortMode >>= 2;
- dbPortNum ++;
- }
- SbStall (1000);
- SataPortMode = (UINT16)pConfig->SataPortMode;
- dbPortNum = 0;
- while ( dbPortNum < 6 ) {
- dbPortMode = (UINT8) (SataPortMode & 3);
- if ( (dbPortMode == BIT0) || (dbPortMode == BIT1) ) {
- RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00);
- }
- dbPortNum ++;
- SataPortMode >>= 2;
- }
- WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
- //Disable write access to pci header, pm capabilities
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0);
-}
-
-
-/**
- * sataInitMidPost - Config SATA controller in Middle POST.
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-sataInitMidPost (
- IN AMDSBCFG* pConfig
- )
-{
- UINT32 ddBar5;
- sataBar5setting (pConfig, &ddBar5);
- //If this is not S3 resume and also if SATA set to one of IDE mode, then implement drive detection workaround.
- if ( ! (pConfig->S3Resume) && ( ((pConfig->SataClass) != AHCI_MODE) && ((pConfig->SataClass) != RAID_MODE) ) ) {
- sataDriveDetection (pConfig, &ddBar5);
- }
-}
-
-/**
- * sataDriveDetection - Sata drive detection
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- * @param[in] *pBar5 Sata BAR5 base address.
- *
- */
-VOID
-sataDriveDetection (
- IN AMDSBCFG* pConfig,
- IN UINT32 *pBar5
- )
-{
- UINT32 ddVar0;
- UINT8 dbPortNum;
- UINT8 dbVar0;
- UINT16 dwIoBase;
- UINT32 dwVar0;
- if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) ) {
- for ( dbPortNum = 0; dbPortNum < 4; dbPortNum++ ) {
- ReadMEM (*pBar5 + SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint32, &ddVar0);
- if ( ( ddVar0 & 0x0F ) == 0x03 ) {
- if ( dbPortNum & BIT0 ) {
- //this port belongs to secondary channel
- ReadPCI (((UINT32) (SATA_BUS_DEV_FUN << 16) + SB_SATA_REG18), AccWidthUint16, &dwIoBase);
- } else {
- //this port belongs to primary channel
- ReadPCI (((UINT32) (SATA_BUS_DEV_FUN << 16) + SB_SATA_REG10), AccWidthUint16, &dwIoBase);
- }
- //if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them
- if ( pConfig->SataClass == LEGACY_IDE_MODE ) {
- dwIoBase = ( (0x170) | ((UINT16) ( (~((UINT8) (dbPortNum & BIT0) << 7)) & 0x80 )) );
- }
- if ( dbPortNum & BIT1 ) {
- //this port is slave
- dbVar0 = 0xB0;
- } else {
- //this port is master
- dbVar0 = 0xA0;
- }
- dwIoBase &= 0xFFF8;
- WriteIO (dwIoBase + 6, AccWidthUint8, &dbVar0);
- //Wait in loop for 30s for the drive to become ready
- for ( dwVar0 = 0; dwVar0 < 300000; dwVar0++ ) {
- ReadIO (dwIoBase + 7, AccWidthUint8, &dbVar0);
- if ( (dbVar0 & 0x88) == 0 ) {
- break;
- }
- SbStall (100);
- }
- } //end of if ( ( ddVar0 & 0x0F ) == 0x03)
- } //for (dbPortNum = 0; dbPortNum < 4; dbPortNum++)
- } //if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE))
-}
-
-/**
- * sataInitLatePost - Prepare SATA controller to boot to OS.
- *
- * - Set class ID to AHCI (if set to AHCI * Mode)
- * - Enable AHCI interrupt
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-sataInitLatePost (
- IN AMDSBCFG* pConfig
- )
-{
- UINT32 ddBar5;
- UINT8 dbVar;
- UINT8 dbPortNum;
-
- //Return immediately is sata controller is not enabled
- if ( pConfig->SATAMODE.SataMode.SataController == 0 ) {
- return;
- }
- //Enable write access to pci header, pm capabilities
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0);
-
-// if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == SATA_IDE_COMBINE_DISABLE) {
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 1), AccWidthUint8 | S3_SAVE, ~BIT7, BIT7);
-// }
- sataBar5setting (pConfig, &ddBar5);
-
- ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
- //Enable memory and io access
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, 0xFF, 0x03);
-
- shutdownUnconnectedSataPortClock (pConfig, ddBar5);
-
- if (( pConfig->SataClass == IDE_TO_AHCI_MODE) || ( pConfig->SataClass == IDE_TO_AHCI_MODE_4394 )) {
- //program the AHCI class code
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, 0x01060100);
- //Set interrupt enable bit
- RWMEM ((ddBar5 + 0x04), AccWidthUint8, (UINT32)~0, BIT1);
- //program the correct device id for AHCI mode
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, 0x4391);
- }
-
- if (( pConfig->SataClass == AHCI_MODE_4394 ) || ( pConfig->SataClass == IDE_TO_AHCI_MODE_4394 )) {
- //program the correct device id for AHCI 4394 mode
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, 0x4394);
- }
-
- //Clear error status ?? only 4 port
- RWMEM ((ddBar5 + SB_SATA_BAR5_REG130), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
- RWMEM ((ddBar5 + SB_SATA_BAR5_REG1B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
- RWMEM ((ddBar5 + SB_SATA_BAR5_REG230), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
- RWMEM ((ddBar5 + SB_SATA_BAR5_REG2B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
- RWMEM ((ddBar5 + SB_SATA_BAR5_REG330), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
- RWMEM ((ddBar5 + SB_SATA_BAR5_REG3B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
- //Restore memory and io access bits
- WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar );
- //Disable write access to pci header and pm capabilities
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0);
- for ( dbPortNum = 0; dbPortNum < 6; dbPortNum++ ) {
- RWMEM ((ddBar5 + 0x110 + (dbPortNum * 0x80)), AccWidthUint32, 0xFFFFFFFF, 0x00);
- }
-}
-
-
diff --git a/src/vendorcode/amd/cimx/sb800/SBCMN.c b/src/vendorcode/amd/cimx/sb800/SBCMN.c
deleted file mode 100644
index 8e9f0e2..0000000
--- a/src/vendorcode/amd/cimx/sb800/SBCMN.c
+++ /dev/null
@@ -1,1066 +0,0 @@
-/**
- * @file
- *
- * Southbridge Initial routine
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: CIMx-SB
- * @e sub-project:
- * @e \$Revision:$ @e \$Date:$
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "SBPLATFORM.h"
-#include "cbtypes.h"
-//
-// Declaration of local functions
-//
-
-VOID abcfgTbl (IN ABTBLENTRY* pABTbl);
-
-/**
- * sbUsbPhySetting - USB Phy Calibration Adjustment
- *
- *
- * @param[in] Value Controller PCI config address (bus# + device# + function#)
- *
- */
-VOID sbUsbPhySetting (IN UINT32 Value);
-
-
-/*--------------------------- Documentation Pages ---------------------------*/
-/**
- * @page LegacyInterfaceCalls Legacy Interface Calls
- * <TD>@subpage SB_POWERON_INIT_Page "SB_POWERON_INIT"</TD><TD></TD>
- * <TD>@subpage SB_BEFORE_PCI_INIT_Page "SB_BEFORE_PCI_INIT"</TD><TD></TD>
- * <TD>@subpage SB_AFTER_PCI_INIT_Page "SB_AFTER_PCI_INIT"</TD><TD></TD>
- * <TD>@subpage SB_LATE_POST_INIT_Page "SB_LATE_POST_INIT"</TD><TD></TD>
- * <TD>@subpage SB_BEFORE_PCI_RESTORE_INIT_Page "SB_BEFORE_PCI_RESTORE_INIT"</TD><TD></TD>
- * <TD>@subpage SB_AFTER_PCI_RESTORE_INIT_Page "SB_AFTER_PCI_RESTORE_INIT"</TD><TD></TD>
- * <TD>@subpage SB_SMM_SERVICE_Page "SB_SMM_SERVICE"</TD><TD></TD>
- * <TD>@subpage SB_SMM_ACPION_Page "SB_SMM_ACPION"</TD><TD></TD>
- *
- * @page LegacyInterfaceCallOuts Legacy Interface CallOuts
- * <TD>@subpage CB_SBGPP_RESET_ASSERT_Page CB_SBGPP_RESET_ASSERT
- * <TD>@subpage CB_SBGPP_RESET_DEASSERT_Page CB_SBGPP_RESET_DEASSERT
- *
-*/
-
-/**
- * sbEarlyPostByteInitTable - PCI device registers initial during early POST.
- *
- */
-const static REG8MASK sbEarlyPostByteInitTable[] =
-{
- // SMBUS Device (Bus 0, Dev 20, Func 0)
- {0x00, SMBUS_BUS_DEV_FUN, 0},
- {SB_CFG_REG10, 0X00, (SBCIMx_Version & 0xFF)}, //Program the version information
- {SB_CFG_REG11, 0X00, (SBCIMx_Version >> 8)},
- {0xFF, 0xFF, 0xFF},
-
- // IDE Device (Bus 0, Dev 20, Func 1)
- {0x00, IDE_BUS_DEV_FUN, 0},
- {SB_IDE_REG62 + 1, ~BIT0, BIT5}, // Enabling IDE Explicit Pre-Fetch IDE PCI Config 0x62[8]=0
- // Allow MSI capability of IDE controller to be visible. IDE PCI Config 0x62[13]=1
- {0xFF, 0xFF, 0xFF},
-
- // Azalia Device (Bus 0, Dev 20, Func 2)
- {0x00, AZALIA_BUS_DEV_FUN, 0},
- {SB_AZ_REG4C, ~BIT0, BIT0},
- {0xFF, 0xFF, 0xFF},
-
- // LPC Device (Bus 0, Dev 20, Func 3)
- {0x00, LPC_BUS_DEV_FUN, 0},
- {SB_LPC_REG40, ~BIT2, BIT2}, // RPR 1.1 Enabling LPC DMA Function 0x40[2]=1b 0x78[0]=0b
- {SB_LPC_REG78, ~BIT0, 00}, // RPR 1.1 Enabling LPC DMA Function 0x40[2]=1b 0x78[0]=0b
- {SB_LPC_REG78, ~BIT1, 00}, // Disables MSI capability
- {SB_LPC_REGBB, ~BIT0, BIT0 + BIT3 + BIT4 + BIT5}, // Enabled SPI Prefetch from HOST.
- {0xFF, 0xFF, 0xFF},
-
- // PCIB Bridge (Bus 0, Dev 20, Func 4)
- {0x00, PCIB_BUS_DEV_FUN, 0},
- {SB_PCIB_REG40, 0xFF, BIT5}, // RPR PCI-bridge Subtractive Decode
- {SB_PCIB_REG4B, 0xFF, BIT7}, //
- {SB_PCIB_REG66, 0xFF, BIT4}, // RPR Enabling One-Prefetch-Channel Mode, PCIB_PCI_config 0x64 [20]
- {SB_PCIB_REG65, 0xFF, BIT7}, // RPR proper operation of CLKRUN#.
- {SB_PCIB_REG0D, 0x00, 0x40}, // Setting Latency Timers to 0x40, Enables the PCIB to retain ownership
- {SB_PCIB_REG1B, 0x00, 0x40}, // of the bus on the Primary side and on the Secondary side when GNT# is deasserted.
- {SB_PCIB_REG66 + 1, 0xFF, BIT1}, // RPR Enable PCI bus GNT3#..
- {0xFF, 0xFF, 0xFF},
-
- // SATA Device (Bus 0, Dev 17, Func 0)
- {0x00, SATA_BUS_DEV_FUN, 0},
- {SB_SATA_REG44, 0xff, BIT0}, // Enables the SATA watchdog timer register prior to the SATA BIOS post
- {SB_SATA_REG44 + 2, 0, 0x20}, // RPR 8.12 SATA PCI Watchdog timer setting
- // [SB01923] Set timer out to 0x20 to fix IDE to SATA Bridge dropping drive issue.
- {0xFF, 0xFF, 0xFF},
-};
-
-
-/**
- * sbPmioEPostInitTable - Southbridge ACPI MMIO initial during POST.
- *
- */
-const static AcpiRegWrite sbPmioEPostInitTable[] =
-{
- // HPET workaround
- {PMIO_BASE >> 8, SB_PMIOA_REG54 + 3, 0xFC, BIT0 + BIT1},
- {PMIO_BASE >> 8, SB_PMIOA_REG54 + 2, 0x7F, BIT7},
- {PMIO_BASE >> 8, SB_PMIOA_REG54 + 2, 0x7F, 0x00},
- // End of HPET workaround
- // Enable SB800 A12 ACPI bits at PMIO 0xC0 [30,10:3]
- // ClrAllStsInThermalEvent 3 Set to 1 to allow ASF remote power down/power cycle, Thermal event, Fan slow event to clear all the Gevent status and enabled bits. The bit should be set to 1 all the time.
- // UsbGoodClkDlyEn 4 Set to 1 to delay de-assertion of Usb clk by 6 Osc clk. The bit should be set to 1 all the time.
- // ForceNBCPUPwr 5 Set to 1 to force CPU pwrGood to be toggled along with NB pwrGood.
- // MergeUsbPerReq 6 Set to 1 to merge usb perdical traffic into usb request as one of break event.
- // IMCWatchDogRstEn 7 Set to 1 to allow IMC watchdog timer to reset entire acpi block. The bit should be set to 1 when IMC is enabled.
- // GeventStsFixEn 8 1: Gevent status is not reset by its enable bit. 0: Gevent status is reset by its enable bit.
- // PmeTimerFixEn 9 Set to 1 to reset Pme Timer when going to sleep state.
- // UserRst2EcEn 10 Set to 1 to route user reset event to Ec. The bit should be set to 1 when IMC is enabled.
- // Smbus0ClkSEn 30 Set to 1 to enable SMBus0 controller clock stretch support.
- {PMIO_BASE >> 8, SB_PMIOA_REGC4, ~(BIT2 + BIT4), BIT2 + BIT4},
- {PMIO_BASE >> 8, SB_PMIOA_REGC0, 0, 0xF9},
- // PM_reg xC1 [3] = 1b, per RPR 2.7 CPU PwrGood Setting
- {PMIO_BASE >> 8, SB_PMIOA_REGC0 + 1, 0x04, 0x0B},
- // RtcSts 19-17 RTC_STS set only in Sleep State.
- // GppPme 20 Set to 1 to enable PME request from SB GPP.
- // Pcireset 22 Set to 1 to allow SW to reset PCIe.
- {PMIO_BASE >> 8, SB_PMIOA_REGC2, 0x20, 0x58},
- {PMIO_BASE >> 8, SB_PMIOA_REGC2 + 1, 0, 0x40},
-
- //Item Id: SB02037: RTC_STS should be set in S state
- //set PMIO 0xC0 [19:16] Set to 1110 to allow RTC_STS to be set only in non_G0 state.
- //{PMIO_BASE >> 8, SB_PMIOA_REGC2, (UINT8)~(0x0F), 0x0E},
-
- //Item Id: SB02034
- //Title: SB GPP NIC auto wake at second time sleep
- //set PMIO 0xC4 bit 2 to 1 then set PMIO 0xC0 bit 20 to 1 to enable fix for SB02034
-
- {PMIO_BASE >> 8, SB_PMIOA_REGC2, ~(BIT4), BIT4},
-
- //{GPIO_BASE >> 8, SB_GPIO_REG62 , 0x00, 0x4E},
- {PMIO_BASE >> 8, SB_PMIOA_REG74, 0x00, BIT0 + BIT1 + BIT2 + BIT4},
- {PMIO_BASE >> 8, SB_PMIOA_REGDE + 1, ~(BIT0 + BIT1), BIT0 + BIT1},
- {PMIO_BASE >> 8, SB_PMIOA_REGDE, ~BIT4, BIT4},
- {PMIO_BASE >> 8, SB_PMIOA_REGBA, ~BIT3, BIT3},
- {PMIO_BASE >> 8, SB_PMIOA_REGBA + 1, ~BIT6, BIT6},
- {PMIO_BASE >> 8, SB_PMIOA_REGBC, ~BIT1, BIT1},
- {PMIO_BASE >> 8, SB_PMIOA_REGED, ~(BIT0 + BIT1), 0},
- //RPR Hiding Flash Controller PM_IO 0xDC[7] = 0x0 & PM_IO 0xDC [1:0]=0x01
- {PMIO_BASE >> 8, SB_PMIOA_REGDC, 0x7C, BIT0},
- // RPR Turning off FC clock
- {MISC_BASE >> 8, SB_MISC_REG40 + 1, ~(BIT3 + BIT2), BIT3 + BIT2},
- {MISC_BASE >> 8, SB_MISC_REG40 + 2, ~BIT0, BIT0},
- {SMI_BASE >> 8, SB_SMI_Gevent0, 0, 29},
- {SMI_BASE >> 8, SB_SMI_Gevent1, 0, 1},
- {SMI_BASE >> 8, SB_SMI_Gevent2, 0, 29},
- {SMI_BASE >> 8, SB_SMI_Gevent3, 0, 29},
- {SMI_BASE >> 8, SB_SMI_Gevent4, 0, 4},
- {SMI_BASE >> 8, SB_SMI_Gevent5, 0, 5},
- {SMI_BASE >> 8, SB_SMI_Gevent6, 0, 6},
- {SMI_BASE >> 8, SB_SMI_Gevent7, 0, 29},
-
- {SMI_BASE >> 8, SB_SMI_Gevent9, 0, 29},
- {SMI_BASE >> 8, SB_SMI_Gevent10, 0, 29},
- {SMI_BASE >> 8, SB_SMI_Gevent11, 0, 29},
- {SMI_BASE >> 8, SB_SMI_Gevent12, 0, 29},
- {SMI_BASE >> 8, SB_SMI_Gevent13, 0, 29},
- {SMI_BASE >> 8, SB_SMI_Gevent14, 0, 29},
- {SMI_BASE >> 8, SB_SMI_Gevent15, 0, 29},
- {SMI_BASE >> 8, SB_SMI_Gevent16, 0, 29},
- {SMI_BASE >> 8, SB_SMI_Gevent17, 0, 29},
- {SMI_BASE >> 8, SB_SMI_Gevent18, 0, 29},
- {SMI_BASE >> 8, SB_SMI_Gevent19, 0, 29},
- {SMI_BASE >> 8, SB_SMI_Gevent20, 0, 29},
- {SMI_BASE >> 8, SB_SMI_Gevent21, 0, 29},
- {SMI_BASE >> 8, SB_SMI_Gevent22, 0, 29},
- {SMI_BASE >> 8, SB_SMI_Gevent23, 0, 29},
-//
- {SMI_BASE >> 8, SB_SMI_Usbwakup0, 0, 11},
- {SMI_BASE >> 8, SB_SMI_Usbwakup1, 0, 11},
- {SMI_BASE >> 8, SB_SMI_Usbwakup2, 0, 11},
- {SMI_BASE >> 8, SB_SMI_Usbwakup3, 0, 11},
- {SMI_BASE >> 8, SB_SMI_IMCGevent0, 0, 12},
- {SMI_BASE >> 8, SB_SMI_IMCGevent1, 0, 29},
- {SMI_BASE >> 8, SB_SMI_FanThGevent, 0, 13},
- {SMI_BASE >> 8, SB_SMI_SBGppPme0, 0, 15},
- {SMI_BASE >> 8, SB_SMI_SBGppPme1, 0, 16},
- {SMI_BASE >> 8, SB_SMI_SBGppPme2, 0, 17},
- {SMI_BASE >> 8, SB_SMI_SBGppPme3, 0, 18},
- {SMI_BASE >> 8, SB_SMI_SBGppHp0, 0, 29},
- {SMI_BASE >> 8, SB_SMI_SBGppHp1, 0, 29},
- {SMI_BASE >> 8, SB_SMI_SBGppHp2, 0, 29},
- {SMI_BASE >> 8, SB_SMI_SBGppHp3, 0, 29},
- {SMI_BASE >> 8, SB_SMI_GecPme, 0, 19},
- {SMI_BASE >> 8, SB_SMI_CIRPme, 0, 23},
- {SMI_BASE >> 8, SB_SMI_Gevent8, 0, 26},
- {SMI_BASE >> 8, SB_SMI_AzaliaPme, 0, 27},
- {SMI_BASE >> 8, SB_SMI_SataGevent0, 0, 30},
- {SMI_BASE >> 8, SB_SMI_SataGevent1, 0, 31},
-
- {SMI_BASE >> 8, SB_SMI_WakePinGevent, 0, 29},
- {SMI_BASE >> 8, SB_SMI_ASFMasterIntr, 0, 29},
- {SMI_BASE >> 8, SB_SMI_ASFSlaveIntr, 0, 29},
-
-// {SMI_BASE >> 8, SB_SMI_REG04, ~BIT4, BIT4},
-// {SMI_BASE >> 8, SB_SMI_REG04 + 1, ~BIT0, BIT0},
-// {SMI_BASE >> 8, SB_SMI_REG04 + 2, ~BIT3, BIT3},
- {SMI_BASE >> 8, SB_SMI_REG08, ~BIT4, 0},
- {SMI_BASE >> 8, SB_SMI_REG08+3, ~BIT2, 0},
-// {SMI_BASE >> 8, SB_SMI_REG0C, ~BIT4, BIT4},
- {SMI_BASE >> 8, SB_SMI_REG0C + 2, ~BIT3, BIT3},
- {SMI_BASE >> 8, SB_SMI_TWARN, 0, 9},
- {SMI_BASE >> 8, SB_SMI_TMI, 0, 29},
- {0xFF, 0xFF, 0xFF, 0xFF},
-};
-
-/**
- * abTblEntry800 - AB-Link Configuration Table for SB800
- *
- */
-const static ABTBLENTRY abTblEntry800[] =
-{
- // RPR Enable downstream posted transactions to pass non-posted transactions.
- {ABCFG, SB_ABCFG_REG10090, BIT8 + BIT16, BIT8 + BIT16},
-
- // RPR Enable SB800 to issue memory read/write requests in the upstream direction.
- {AXCFG, SB_AB_REG04, BIT2, BIT2},
-
- // RPR Enabling IDE/PCIB Prefetch for Performance Enhancement
- // PCIB prefetch ABCFG 0x10060 [20] = 1 ABCFG 0x10064 [20] = 1
- {ABCFG, SB_ABCFG_REG10060, BIT20, BIT20}, // PCIB prefetch enable
- {ABCFG, SB_ABCFG_REG10064, BIT20, BIT20}, // PCIB prefetch enable
-
- // RPR Controls the USB OHCI controller prefetch used for enhancing performance of ISO out devices.
- // RPR Setting B-Link Prefetch Mode (ABCFG 0x80 [18:17] = 11)
- {ABCFG, SB_ABCFG_REG80, BIT0 + BIT17 + BIT18, BIT0 + BIT17 + BIT18},
-
- // RPR Enabled SMI ordering enhancement. ABCFG 0x90[21]
- // RPR USB Delay A-Link Express L1 State. ABCFG 0x90[17]
- {ABCFG, SB_ABCFG_REG90, BIT21 + BIT17, BIT21 + BIT17},
-
- // RPR Disable the credit variable in the downstream arbitration equation
- // RPR Register bit to qualify additional address bits into downstream register programming. (A12 BIT1 default is set)
- {ABCFG, SB_ABCFG_REG9C, BIT0, BIT0},
-
- // RPR Enabling Detection of Upstream Interrupts ABCFG 0x94 [20] = 1
- // ABCFG 0x94 [19:0] = cpu interrupt delivery address [39:20]
- {ABCFG, SB_ABCFG_REG94, BIT20, BIT20 + 0x00FEE},
-
- // RPR Programming cycle delay for AB and BIF clock gating
- // RPR Enable the AB and BIF clock-gating logic.
- // RPR Enable the A-Link int_arbiter enhancement to allow the A-Link bandwidth to be used more efficiently
- // RPR Enable the requester ID for upstream traffic. [16]: SB/NB link [17]: GPP
- {ABCFG, SB_ABCFG_REG10054, 0x00FFFFFF, 0x010407FF},
- {ABCFG, SB_ABCFG_REG98, 0xFFFF00FF, 0x00034700},
- {ABCFG, SB_ABCFG_REG54, 0x00FF0000, 0x00040000},
- // RPR Non-Posted Memory Write Support
- {AX_INDXC, SB_AX_INDXC_REG10, BIT9, BIT9},
- {ABCFG, 0, 0, (UINT8) 0xFF}, // This dummy entry is to clear ab index
- { (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF},
-};
-
-/**
- * SbPcieOrderRule - AB-Link Configuration Table for ablink Post Pass Np Downstream/Upstream Feature
- *
- */
-const static ABTBLENTRY SbPcieOrderRule[] =
-{
-// abPostPassNpDownStreamTbl
- {ABCFG, SB_ABCFG_REG10060, BIT31, BIT31},
- {ABCFG, SB_ABCFG_REG1009C, BIT4 + BIT5, BIT4 + BIT5},
- {ABCFG, SB_ABCFG_REG9C, BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7, BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7},
- {ABCFG, SB_ABCFG_REG90, BIT21 + BIT22 + BIT23, BIT21 + BIT22 + BIT23},
- {ABCFG, SB_ABCFG_REGF0, BIT6 + BIT5, BIT6 + BIT5},
- {AXINDC, SB_AX_INDXC_REG02, BIT9, BIT9},
- {ABCFG, SB_ABCFG_REG10090, BIT9 + BIT10 + BIT11 + BIT12, BIT9 + BIT10 + BIT11 + BIT12},
-// abPostPassNpUpStreamTbl
- {ABCFG, SB_ABCFG_REG58, BIT10, BIT10},
- {ABCFG, SB_ABCFG_REGF0, BIT3 + BIT4, BIT3 + BIT4},
- {ABCFG, SB_ABCFG_REG54, BIT1, BIT1},
- { (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF},
-};
-
-/**
- * commonInitEarlyBoot - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB.
- *
- * This settings should be done during S3 resume also
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-commonInitEarlyBoot (
- IN AMDSBCFG* pConfig
- )
-{
- UINT32 abValue;
- UINT16 dwTempVar;
- CPUID_DATA CpuId;
- UINT8 cimNativepciesupport;
- UINT8 cimIrConfig;
- UINT8 Data;
-
- cimNativepciesupport = (UINT8) pConfig->NativePcieSupport;
- cimIrConfig = (UINT8) pConfig->IrConfig;
-#if SB_CIMx_PARAMETER == 0
- cimNativepciesupport = cimNativepciesupportDefault;
- cimIrConfig = cimIrConfigDefault;
-#endif
-
- //IR init Logical device 0x05
- if ( cimIrConfig ) {
- // Enable EC_PortActive
- RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4), AccWidthUint16 | S3_SAVE, 0xFFFE, BIT0);
- EnterEcConfig ();
- RWEC8 (0x07, 0x00, 0x05); //Select logical device 05, IR controller
- RWEC8 (0x60, 0x00, 0x05); //Set Base Address to 550h
- RWEC8 (0x61, 0x00, 0x50);
- RWEC8 (0x70, 0xF0, 0x05); //Set IRQ to 05h
- RWEC8 (0x30, 0x00, 0x01); //Enable logical device 5, IR controller
- Data = 0xAB;
- WriteIO (0x550, AccWidthUint8, &Data);
- ReadIO (0x551, AccWidthUint8, &Data);
- Data = ((Data & 0xFC ) | cimIrConfig);
- WriteIO (0x551, AccWidthUint8, &Data);
- ExitEcConfig ();
- Data = 0xA0; // EC APIC index
- WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &Data);
- Data = 0x05; // IRQ5
- WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &Data);
- } else {
- EnterEcConfig ();
- RWEC8 (0x07, 0x00, 0x05); //Select logical device 05, IR controller
- RWEC8 (0x30, 0x00, 0x00); //Disable logical device 5, IR controller
- ExitEcConfig ();
- }
-
-
- CpuidRead (0x01, &CpuId);
-
- //
- // SB CFG programming
- //
- //Make BAR registers of smbus visible.
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0);
- //Early post initialization of pci config space
- programPciByteTable ((REG8MASK*) FIXUP_PTR (&sbEarlyPostByteInitTable[0]), sizeof (sbEarlyPostByteInitTable) / sizeof (REG8MASK) );
- if ( pConfig->BuildParameters.SmbusSsid != 0 ) {
- RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.SmbusSsid);
- }
- //Make BAR registers of smbus invisible.
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, BIT6);
-
- //
- // LPC CFG programming
- //
- // SSID for LPC Controller
- if (pConfig->BuildParameters.LpcSsid != 0 ) {
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.LpcSsid);
- }
- // LPC MSI
- if ( pConfig->BuildParameters.LpcMsi) {
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG78, AccWidthUint32 | S3_SAVE, ~BIT1, BIT1);
- }
-
- //
- // PCIB CFG programming
- //
- //Disable or Enable PCI Clks based on input
- RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG42, AccWidthUint8 | S3_SAVE, ~(BIT5 + BIT4 + BIT3 + BIT2), ((pConfig->PciClks) & 0x0F) << 2 );
- RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG4A, AccWidthUint8 | S3_SAVE, ~(BIT1 + BIT0), (pConfig->PciClks) >> 4 );
- // PCIB MSI
- if ( pConfig->BuildParameters.PcibMsi) {
- RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG40, AccWidthUint8 | S3_SAVE, ~BIT3, BIT3);
- }
-
- //
- // AB CFG programming
- //
- // Read Arbiter address, Arbiter address is in PMIO 6Ch
- ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6C, AccWidthUint16, &dwTempVar);
- RWIO (dwTempVar, AccWidthUint8, 0, 0); // Write 0 to enable the arbiter
-
- abLinkInitBeforePciEnum (pConfig); // Set ABCFG registers
- // AB MSI
- if ( pConfig->BuildParameters.AbMsi) {
- abValue = readAlink (SB_ABCFG_REG94 | (UINT32) (ABCFG << 29));
- abValue = abValue | BIT20;
- writeAlink (SB_ABCFG_REG94 | (UINT32) (ABCFG << 29), abValue);
- }
-
-
- //
- // SB Specific Function programming
- //
-
- // PCIE Native setting
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGBA + 1, AccWidthUint8, ~BIT14, 0);
- if ( pConfig->NativePcieSupport == 1) {
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG74 + 3, AccWidthUint8, ~(BIT3 + BIT1 + BIT0), BIT2 + BIT0);
- } else {
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG74 + 3, AccWidthUint8, ~(BIT3 + BIT1 + BIT0), BIT2);
- }
-
-#ifdef ACPI_SLEEP_TRAP
- // Set SLP_TYPE as SMI event
- RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB0, AccWidthUint8, ~(BIT2 + BIT3), BIT2);
- // Disabled SLP function for S1/S3/S4/S5
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGBE, AccWidthUint8, ~BIT5, 0x00);
- // Set S state transition disabled (BIT0) force ACPI to send SMI message when writing to SLP_TYP Acpi register. (BIT1)
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG08 + 3, AccWidthUint8, ~(BIT0 + BIT1), BIT1);
- // Enabled Global Smi ( BIT7 clear as 0 to enable )
- RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REG98 + 3 , AccWidthUint8, ~BIT7, 0x00);
-#endif
- if ( pConfig->SbUsbPll == 0) {
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF3, AccWidthUint8, 0, 0x20);
- }
- // Set Stutter timer settings
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 1, AccWidthUint8, ~(BIT3 + BIT4), BIT3 + BIT4);
- // Set LDTSTP# duration to 10us for HydraD CPU, or when HT link is 200MHz
- if ((pConfig->AnyHT200MhzLink) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100080) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100090) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x1000A0)) {
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8, 0, 0x0A);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 3, AccWidthUint8 | S3_SAVE, 0xFE, 0x28);
- } else {
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8, 0, 0x01);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 3, AccWidthUint8 | S3_SAVE, 0xFE, 0x20);
- }
-
- //PM_Reg 0x7A[15] (CountHaltMsgEn) should be set when C1e option is enabled
- //PM_Reg 0x7A[3:0] (NumOfCpu) should be set to 1h when C1e option is enabled
- //PM_Reg 0x80[13] has to set to 1 to enable Message C scheme.
- if (pConfig->MTC1e) {
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7A, AccWidthUint16 | S3_SAVE, 0x7FF0, BIT15 + 1);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 1, AccWidthUint8 | S3_SAVE, ~BIT5, BIT5);
- }
-
- programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr));
-}
-
-/**
- * abSpecialSetBeforePciEnum - Special setting ABCFG registers before PCI emulation.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-abSpecialSetBeforePciEnum (
- IN AMDSBCFG* pConfig
- )
-{
- UINT32 abValue;
- abValue = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29));
- abValue &= 0xf0;
- if ( pConfig->SbPcieOrderRule && abValue ) {
- abValue = readAlink (SB_RCINDXC_REG02 | (UINT32) (RCINDXC << 29));
- abValue = abValue | BIT9;
- writeAlink (SB_RCINDXC_REG02 | (UINT32) (RCINDXC << 29), abValue);
- }
-}
-
-VOID
-usbDesertPll (
- IN AMDSBCFG* pConfig
- )
-{
- if ( pConfig->SbUsbPll == 0) {
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF3, AccWidthUint8, 0, 0x00);
- }
-}
-
-/**
- * commonInitEarlyPost - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB.
- *
- * This settings might not program during S3 resume
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-commonInitEarlyPost (
- IN AMDSBCFG* pConfig
- )
-{
- UINT8 dbPortStatus;
- UINT8 cimSpreadSpectrum;
- UINT32 cimSpreadSpectrumType;
- AMDSBCFG* pTmp;
- pTmp = pConfig;
-
- cimSpreadSpectrum = pConfig->SpreadSpectrum;
- cimSpreadSpectrumType = pConfig->BuildParameters.SpreadSpectrumType;
-#if SB_CIMx_PARAMETER == 0
- cimSpreadSpectrum = cimSpreadSpectrumDefault;
- cimSpreadSpectrumType = cimSpreadSpectrumTypeDefault;
-#endif
- programSbAcpiMmioTbl ((AcpiRegWrite*) FIXUP_PTR (&sbPmioEPostInitTable[0]));
-
- // CallBackToOEM (PULL_UP_PULL_DOWN_SETTINGS, NULL, pConfig);
-
- if ( cimSpreadSpectrum ) {
- // Misc_Reg_40[25]=1 -> allow to change spread profile
- // Misc_Reg19=83 -> new spread profile
- // Misc_Reg[12:10]=9975be
- // Misc_Reg0B=91
- // Misc_Reg09=21
- // Misc_Misc_Reg_08[0]=1 -> enable spread
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x43, AccWidthUint8, ~BIT1, BIT1);
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x19, AccWidthUint8, 0, 0x83);
- getChipSysMode (&dbPortStatus);
- if ( ((dbPortStatus & ChipSysIntClkGen) != ChipSysIntClkGen) ) {
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1A, AccWidthUint8, ~(BIT5 + BIT6 + BIT7), 0x80);
- }
-
- if ( cimSpreadSpectrumType == 0 ) {
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x12, AccWidthUint8, 0, 0x99);
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x11, AccWidthUint8, 0, 0x75);
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccWidthUint8, 0, 0xBE);
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x0B, AccWidthUint8, 0, 0x91);
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x09, AccWidthUint8, 0, 0x21);
- } else { // Spread profile for Ontario CPU related platform
- // This spread profile setting is for Ontario HDMI & DVI output from DP with -0.425%
- // Misc_Reg[12:10]=828FA8
- // Misc_Reg0B=11
- // Misc_Reg09=21
- // Misc_Reg10[25:24]=01b
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x12, AccWidthUint8, 0, 0x82);
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x11, AccWidthUint8, 0, 0x8F);
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccWidthUint8, 0, 0xA8);
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x0B, AccWidthUint8, 0, 0x11);
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x09, AccWidthUint8, 0, 0x21);
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x13, AccWidthUint8, 0xFC, 0x1);
- }
-
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG08, AccWidthUint8, 0xFE, 0x01);
- } else {
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG08, AccWidthUint8, 0xFE, 0x00);
- }
-
- // RPR PLL 100Mhz Reference Clock Buffer setting for internal clock generator mode
- getChipSysMode (&dbPortStatus);
- if ( ((dbPortStatus & ChipSysIntClkGen) == ChipSysIntClkGen) ) {
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG04 + 1, AccWidthUint8, ~BIT5, BIT5);
- }
-
- // Set ASF SMBUS master function enabled here (temporary)
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG28, AccWidthUint16 | S3_SAVE, ~(BIT0 + BIT2), BIT0 + BIT2);
-
- programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr));
-#ifndef NO_EC_SUPPORT
- // Software IMC enable
- if (((pConfig->BuildParameters.ImcEnableOverWrite == 1) && ((dbPortStatus & ChipSysEcEnable) == 0)) || ((pConfig->BuildParameters.ImcEnableOverWrite == 2) && ((dbPortStatus & ChipSysEcEnable) == ChipSysEcEnable))) {
- if (validateImcFirmware (pConfig)) {
- softwareToggleImcStrapping (pConfig);
- } else {
- CallBackToOEM (IMC_FIRMWARE_FAIL, 0, pConfig);
- }
- }
-#endif
-
-}
-/**
- * abLinkInitBeforePciEnum - Set ABCFG registers before PCI emulation.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-abLinkInitBeforePciEnum (
- IN AMDSBCFG* pConfig
- )
-{
- UINT32 cimResetCpuOnSyncFlood;
- ABTBLENTRY *pAbTblPtr;
- AMDSBCFG* Temp;
-
- cimResetCpuOnSyncFlood = pConfig->ResetCpuOnSyncFlood;
-#if SB_CIMx_PARAMETER == 0
- cimResetCpuOnSyncFlood = cimResetCpuOnSyncFloodDefault;
-#endif
- Temp = pConfig;
- if ( pConfig->SbPcieOrderRule ) {
- pAbTblPtr = (ABTBLENTRY *) FIXUP_PTR (&SbPcieOrderRule[0]);
- abcfgTbl (pAbTblPtr);
- }
- pAbTblPtr = (ABTBLENTRY *) FIXUP_PTR (&abTblEntry800[0]);
- abcfgTbl (pAbTblPtr);
- if ( cimResetCpuOnSyncFlood ) {
- rwAlink (SB_ABCFG_REG10050 | (UINT32) (ABCFG << 29), ~BIT2, BIT2);
- }
-}
-
-/**
- * abcfgTbl - Program ABCFG by input table.
- *
- *
- * @param[in] pABTbl ABCFG config table.
- *
- */
-VOID
-abcfgTbl (
- IN ABTBLENTRY* pABTbl
- )
-{
- UINT32 ddValue;
-
- while ( (pABTbl->regType) != 0xFF ) {
- if ( pABTbl->regType > AXINDC ) {
- ddValue = pABTbl->regIndex | (pABTbl->regType << 29);
- writeAlink (ddValue, ((readAlink (ddValue)) & (0xFFFFFFFF^ (pABTbl->regMask))) | pABTbl->regData);
- } else {
- ddValue = 0x30 | (pABTbl->regType << 29);
- writeAlink (ddValue, pABTbl->regIndex);
- ddValue = 0x34 | (pABTbl->regType << 29);
- writeAlink (ddValue, ((readAlink (ddValue)) & (0xFFFFFFFF^ (pABTbl->regMask))) | pABTbl->regData);
- }
- ++pABTbl;
- }
-
- //Clear ALink Access Index
- ddValue = 0;
- WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &ddValue);
-}
-
-/**
- * commonInitLateBoot - Prepare Southbridge register setting to boot to OS.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-commonInitLateBoot (
- IN AMDSBCFG* pConfig
- )
-{
- UINT8 dbValue;
- UINT32 ddVar;
- // We need to do the following setting in late post also because some bios core pci enumeration changes these values
- // programmed during early post.
- // RPR 4.5 Master Latency Timer
-
- dbValue = 0x40;
- WritePCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG0D, AccWidthUint8, &dbValue);
- WritePCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG1B, AccWidthUint8, &dbValue);
-
- //SB P2P AutoClock control settings.
- ddVar = (pConfig->PcibAutoClkCtrlHigh << 16) | (pConfig->PcibAutoClkCtrlLow);
- WritePCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG4C, AccWidthUint32, &ddVar);
- ddVar = (pConfig->PcibClkStopOverride);
- RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG50, AccWidthUint16, 0x3F, (UINT16) (ddVar << 6));
-
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBB, AccWidthUint8, 0xBF | S3_SAVE, BIT3 + BIT4 + BIT5);
-
- // USB Phy Calibration Adjustment
- ddVar = (USB1_EHCI_BUS_DEV_FUN << 16);
- sbUsbPhySetting (ddVar);
- ddVar = (USB2_EHCI_BUS_DEV_FUN << 16);
- sbUsbPhySetting (ddVar);
- ddVar = (USB3_EHCI_BUS_DEV_FUN << 16);
- sbUsbPhySetting (ddVar);
-
- c3PopupSetting (pConfig);
- FusionRelatedSetting (pConfig);
-}
-
-/**
- * sbUsbPhySetting - USB Phy Calibration Adjustment
- *
- *
- * @param[in] Value Controller PCI config address (bus# + device# + function#)
- *
- */
-VOID
-sbUsbPhySetting (
- IN UINT32 Value
- )
-{
- UINT32 ddBarAddress;
- UINT32 ddPhyStatus03;
- UINT32 ddPhyStatus4;
- UINT8 dbRevId;
- //Get BAR address
- ReadPCI ((UINT32) Value + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress);
- if ( (ddBarAddress != - 1) && (ddBarAddress != 0) ) {
- ReadMEM ( ddBarAddress + SB_EHCI_BAR_REGA8, AccWidthUint32, &ddPhyStatus03);
- ReadMEM ( ddBarAddress + SB_EHCI_BAR_REGAC, AccWidthUint32, &ddPhyStatus4);
- ddPhyStatus03 &= 0x07070707;
- ddPhyStatus4 &= 0x00000007;
- if ( (ddPhyStatus03 != 0x00) | (ddPhyStatus4 != 0x00) ) {
- // RPR 7.7 USB 2.0 Ports Driving Strength step 1
- //Make BAR registers of smbus visible.
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0);
- ReadPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG08, AccWidthUint8, &dbRevId);
- //Make BAR registers of smbus invisible.
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, BIT6);
- if (dbRevId == 0x41) { // A12
- RWMEM (ddBarAddress + SB_EHCI_BAR_REGC0, AccWidthUint32, 0xFFFF00FF, 0x1500);
- RWMEM (ddBarAddress + SB_EHCI_BAR_REGC4, AccWidthUint32, 0xFFFFF0FF, 0);
- } else if (dbRevId == 0x42) { // A13
- RWMEM (ddBarAddress + SB_EHCI_BAR_REGC0, AccWidthUint32, 0xFFFF00FF, 0x0F00);
- RWMEM (ddBarAddress + SB_EHCI_BAR_REGC4, AccWidthUint32, 0xFFFFF0FF, 0x0100);
- }
- }
- }
-}
-
-/**
- * hpetInit - Program Southbridge HPET function
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- * @param[in] pStaticOptions Platform build configuration table.
- *
- */
-VOID
-hpetInit (
- IN AMDSBCFG* pConfig,
- IN BUILDPARAM *pStaticOptions
- )
-{
- DESCRIPTION_HEADER* pHpetTable;
- UINT8 cimHpetTimer;
- UINT8 cimHpetMsiDis;
-
- cimHpetTimer = (UINT8) pConfig->HpetTimer;
- cimHpetMsiDis = (UINT8) pConfig->HpetMsiDis;
-#if SB_CIMx_PARAMETER == 0
- cimHpetTimer = cimHpetTimerDefault;
- cimHpetMsiDis = cimHpetMsiDisDefault;
-#endif
- pHpetTable = NULL;
- if ( cimHpetTimer == TRUE ) {
- //Program the HPET BAR address
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, pStaticOptions->HpetBase);
- //Enabling decoding of HPET MMIO
- //Enable HPET MSI support
- //Enable High Precision Event Timer (also called Multimedia Timer) interrupt
- if ( cimHpetMsiDis == FALSE ) {
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, BIT0 + BIT1 + BIT2 + BIT3 + BIT4);
- } else {
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, BIT0 + BIT1);
- }
-
- } else {
- if ( ! (pConfig->S3Resume) ) {
- pHpetTable = (DESCRIPTION_HEADER*) ACPI_LocateTable (Int32FromChar('H', 'P', 'E', 'T'));
- }
- if ( pHpetTable != NULL ) {
- pHpetTable->Signature = Int32FromChar('T', 'E', 'P', 'H');
- }
- }
-}
-
-/**
- * c3PopupSetting - Program Southbridge C state function
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-c3PopupSetting (
- IN AMDSBCFG* pConfig
- )
-{
- AMDSBCFG* Temp;
- UINT8 dbValue;
- Temp = pConfig;
- //RPR C-State and VID/FID Change
- dbValue = getNumberOfCpuCores ();
- if (dbValue > 1) {
- //PM 0x80[2]=1, For system with dual core CPU, set this bit to 1 to automatically clear BM_STS when the C3 state is being initiated.
- //PM 0x80[1]=1, For system with dual core CPU, set this bit to 1 and BM_STS will cause C3 to wakeup regardless of BM_RLD
- //PM 0x7E[6]=1, Enable pop-up for C3. For internal bus mastering or BmReq# from the NB, the SB will de-assert
- //LDTSTP# (pop-up) to allow DMA traffic, then assert LDTSTP# again after some idle time.
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint8 | S3_SAVE, ~(BIT1 + BIT2), (BIT1 + BIT2));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7E, AccWidthUint8 | S3_SAVE, ~BIT6, BIT6);
- }
- //SB800 needs to changed for RD790 support
- //PM 0x80 [8] = 0 for system with RS780
- //Note: RS690 north bridge has AllowLdtStop built for both display and PCIE traffic to wake up the HT link.
- //BmReq# needs to be ignored otherwise may cause LDTSTP# not to toggle.
- //PM_IO 0x80[3]=1, Ignore BM_STS_SET message from NB
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint16 | S3_SAVE, ~(BIT9 + BIT8 + BIT7 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), 0x21F);
- //LdtStartTime = 10h for minimum LDTSTP# de-assertion duration of 16us in StutterMode. This is to guarantee that
- //the HT link has been safely reconnected before it can be disconnected again. If C3 pop-up is enabled, the 16us also
- //serves as the minimum idle time before LDTSTP# can be asserted again. This allows DMA to finish before the HT
- //link is disconnected.
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94 + 2, AccWidthUint8, 0, 0x10);
-
- //This setting provides 16us delay before the assertion of LDTSTOP# when C3 is entered. The
- //delay will allow USB DMA to go on in a continuous manner
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG98 + 1, AccWidthUint8, 0, 0x10);
- // Not in the RPR so far, it's hand writing from ASIC
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7C, AccWidthUint8 | S3_SAVE, 0, 0x85);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7C + 1, AccWidthUint8 | S3_SAVE, 0, 0x01);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7E + 1, AccWidthUint8 | S3_SAVE, ~(BIT7 + BIT5), BIT7 + BIT5);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88 + 1, AccWidthUint8 | S3_SAVE, ~BIT4, BIT4);
- // RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8, 0, 0x10);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG98 + 3, AccWidthUint8, 0, 0x10);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGB4 + 1, AccWidthUint8, 0, 0x0B);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8 | S3_SAVE, 0xFF, BIT4);
- if (pConfig->LdtStpDisable) {
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8 | S3_SAVE, ~BIT5, 0);
- }
-}
-
-/**
- * FusionRelatedSetting - Program Fusion C related function
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-FusionRelatedSetting (
- IN AMDSBCFG* pConfig
- )
-{
- UINT8 cimAcDcMsg;
- UINT8 cimTimerTickTrack;
- UINT8 cimClockInterruptTag;
- UINT8 cimOhciTrafficHanding;
- UINT8 cimEhciTrafficHanding;
- UINT8 cimFusionMsgCMultiCore;
- UINT8 cimFusionMsgCStage;
- UINT32 ddValue;
-
- cimAcDcMsg = (UINT8) pConfig->AcDcMsg;
- cimTimerTickTrack = (UINT8) pConfig->TimerTickTrack;
- cimClockInterruptTag = (UINT8) pConfig->ClockInterruptTag;
- cimOhciTrafficHanding = (UINT8) pConfig->OhciTrafficHanding;
- cimEhciTrafficHanding = (UINT8) pConfig->EhciTrafficHanding;
- cimFusionMsgCMultiCore = (UINT8) pConfig->FusionMsgCMultiCore;
- cimFusionMsgCStage = (UINT8) pConfig->FusionMsgCStage;
-#if SB_CIMx_PARAMETER == 0
- cimAcDcMsg = cimAcDcMsgDefault;
- cimTimerTickTrack = cimTimerTickTrackDefault;
- cimClockInterruptTag = cimClockInterruptTagDefault;
- cimOhciTrafficHanding = cimOhciTrafficHandingDefault;
- cimEhciTrafficHanding = cimEhciTrafficHandingDefault;
- cimFusionMsgCMultiCore = cimFusionMsgCMultiCoreDefault;
- cimFusionMsgCStage = cimFusionMsgCStageDefault;
-#endif
- ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGA0, AccWidthUint32 | S3_SAVE, &ddValue);
- ddValue = ddValue & 0xC07F00A0;
- if ( cimAcDcMsg ) {
- ddValue = ddValue | BIT0;
- }
- if ( cimTimerTickTrack ) {
- ddValue = ddValue | BIT1;
- }
- if ( cimClockInterruptTag ) {
- ddValue = ddValue | BIT10;
- }
- if ( cimOhciTrafficHanding ) {
- ddValue = ddValue | BIT13;
- }
- if ( cimEhciTrafficHanding ) {
- ddValue = ddValue | BIT15;
- }
- if ( cimFusionMsgCMultiCore ) {
- ddValue = ddValue | BIT23;
- }
- if ( cimFusionMsgCStage ) {
- ddValue = (ddValue | (BIT6 + BIT4 + BIT3 + BIT2));
- }
- WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGA0, AccWidthUint32 | S3_SAVE, &ddValue);
-}
-#ifndef NO_EC_SUPPORT
-/**
- * validateImcFirmware - Validate IMC Firmware.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- * @retval TRUE Pass
- * @retval FALSE Failed
- */
-BOOLEAN
-validateImcFirmware (
- IN AMDSBCFG* pConfig
- )
-{
- UINT32 ImcSig;
- UINT32 ImcSigAddr;
- UINT32 ImcAddr;
- UINT32 CurAddr;
- UINT32 ImcBinSig0;
- UINT32 ImcBinSig1;
- UINT16 ImcBinSig2;
- UINT8 dbIMCChecksume;
- UINT8 dbIMC;
- ImcAddr = 0;
-
- // Software IMC enable
- ImcSigAddr = 0x80000; // start from 512k to 64M
- ImcSig = 0x0; //
- while ( ( ImcSig != 0x55aa55aa ) && ( ImcSigAddr <= 0x4000000 ) ) {
- CurAddr = 0xffffffff - ImcSigAddr + 0x20001;
- ReadMEM (CurAddr, AccWidthUint32, &ImcSig);
- ReadMEM ((CurAddr + 4), AccWidthUint32, &ImcAddr);
- ImcSigAddr <<= 1;
- }
-
- dbIMCChecksume = 0xff;
- if ( ImcSig == 0x55aa55aa ) {
- // "_AMD_IMC_C" at offset 0x2000 of the binary
- ReadMEM ((ImcAddr + 0x2000), AccWidthUint32, &ImcBinSig0);
- ReadMEM ((ImcAddr + 0x2004), AccWidthUint32, &ImcBinSig1);
- ReadMEM ((ImcAddr + 0x2008), AccWidthUint16, &ImcBinSig2);
- if ((ImcBinSig0 == 0x444D415F) && (ImcBinSig1 == 0x434D495F) && (ImcBinSig2 == 0x435F) ) {
- dbIMCChecksume = 0;
- for ( CurAddr = ImcAddr; CurAddr < ImcAddr + 0x10000; CurAddr++ ) {
- ReadMEM (CurAddr, AccWidthUint8, &dbIMC);
- dbIMCChecksume = dbIMCChecksume + dbIMC;
- }
- }
- }
- if ( dbIMCChecksume ) {
- return FALSE;
- } else {
- return TRUE;
- }
-}
-
-/**
- * softwareToggleImcStrapping - Software Toggle IMC Firmware Strapping.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-softwareToggleImcStrapping (
- IN AMDSBCFG* pConfig
- )
-{
- UINT8 dbValue;
- UINT8 dbPortStatus;
- UINT32 abValue;
- UINT32 abValue1;
-
- getChipSysMode (&dbPortStatus);
-
- ReadPMIO (SB_PMIOA_REGBF, AccWidthUint8, &dbValue);
- //if ( (dbValue & (BIT6 + BIT7)) != 0xC0 ) { // PwrGoodOut =1, PwrGoodEnB=1
- //The strapStatus register is not mapped into StrapOveride not in the same bit position. The following is difference.
-
- //StrapStatus StrapOverride
- // bit4 bit17
- // bit6 bit12
- // bit12 bit15
- // bit15 bit16
- // bit16 bit18
- ReadMEM ((ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80), AccWidthUint32, &abValue);
- abValue1 = abValue;
- if (abValue & BIT4) {
- abValue1 = (abValue1 & ~BIT4) | BIT17;
- }
- if (abValue & BIT6) {
- abValue1 = (abValue1 & ~BIT6) | BIT12;
- }
- if (abValue & BIT12) {
- abValue1 = (abValue1 & ~BIT12) | BIT15;
- }
- if (abValue & BIT15) {
- abValue1 = (abValue1 & ~BIT15) | BIT16;
- }
- if (abValue & BIT16) {
- abValue1 = (abValue1 & ~BIT16) | BIT18;
- }
- abValue1 |= BIT31; // Overwrite enable
- if ((dbPortStatus & ChipSysEcEnable) == 0) {
- abValue1 |= BIT2; // bit2- EcEnableStrap
- } else {
- abValue1 &= ~BIT2; // bit2=0 EcEnableStrap
- }
- WriteMEM ((ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG84), AccWidthUint32, &abValue1);
- dbValue |= BIT6; // PwrGoodOut =1
- dbValue &= ~BIT7; // PwrGoodEnB =0
- WritePMIO (SB_PMIOA_REGBF, AccWidthUint8, &dbValue);
-
- dbValue = 06;
- WriteIO (0xcf9, AccWidthUint8, &dbValue);
- SbStall (0xffffffff);
-}
-#endif
-
-#ifndef NO_HWM_SUPPORT
-/**
- * validateImcFirmware - Validate IMC Firmware.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-hwmInit (
- IN AMDSBCFG* pConfig
- )
-{
- RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xB2, AccWidthUint8 | S3_SAVE, 0, 0x55);
- RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xB3, AccWidthUint8 | S3_SAVE, 0, 0x55);
- RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x91, AccWidthUint8 | S3_SAVE, 0, 0x55);
- RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x92, AccWidthUint8 | S3_SAVE, 0, 0x55);
-
- RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x00, AccWidthUint8 | S3_SAVE, 0, 0x06);
- RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x10, AccWidthUint8 | S3_SAVE, 0, 0x06);
- RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x20, AccWidthUint8 | S3_SAVE, 0, 0x06);
- RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x30, AccWidthUint8 | S3_SAVE, 0, 0x06);
- RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x40, AccWidthUint8 | S3_SAVE, 0, 0x06);
-
- RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x66, AccWidthUint8 | S3_SAVE, 0, 0x01);
- RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x6B, AccWidthUint8 | S3_SAVE, 0, 0x01);
- RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x70, AccWidthUint8 | S3_SAVE, 0, 0x01);
- RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x75, AccWidthUint8 | S3_SAVE, 0, 0x01);
- RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x7A, AccWidthUint8 | S3_SAVE, 0, 0x01);
-
- RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xF8, AccWidthUint8 | S3_SAVE, 0, 0x05);
- RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xF9, AccWidthUint8 | S3_SAVE, 0, 0x06);
- RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xFF, AccWidthUint8 | S3_SAVE, 0, 0x42);
- RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xE9, AccWidthUint8 | S3_SAVE, 0, 0xFF);
- RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xEB, AccWidthUint8 | S3_SAVE, 0, 0x1F);
- RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xEF, AccWidthUint8 | S3_SAVE, 0, 0x04);
- RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xFB, AccWidthUint8 | S3_SAVE, 0, 0x00);
-}
-#endif
diff --git a/src/vendorcode/amd/cimx/sb800/SBDEF.h b/src/vendorcode/amd/cimx/sb800/SBDEF.h
deleted file mode 100644
index 79310fd..0000000
--- a/src/vendorcode/amd/cimx/sb800/SBDEF.h
+++ /dev/null
@@ -1,261 +0,0 @@
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-//AMD Library Routines (AMDLIB.C)
-unsigned char getNumberOfCpuCores (OUT void);
-unsigned int readAlink (IN unsigned int Index);
-void writeAlink (IN unsigned int Index, IN unsigned int Data);
-void rwAlink (IN unsigned int Index, IN unsigned int AndMask, IN unsigned int OrMask);
-
-//AMD Library Routines (LEGACY.C)
-unsigned int GetFixUp (OUT void);
-
-//AMD Library Routines (IOLIB.C)
-void ReadIO (IN unsigned short Address, IN unsigned char OpFlag, IN void *Value);
-void WriteIO (IN unsigned short Address, IN unsigned char OpFlag, IN void *Value);
-void RWIO (IN unsigned short Address, IN unsigned char OpFlag, IN unsigned int Mask, IN unsigned int Data);
-
-
-
-//AMD Library Routines (MEMLIB.C)
-void ReadMEM (IN unsigned int Address, IN unsigned char OpFlag, IN void* Value);
-void WriteMEM (IN unsigned int Address, IN unsigned char OpFlag, IN void* Value);
-void RWMEM (IN unsigned int Address, IN unsigned char OpFlag, IN unsigned int Mask, IN unsigned int Data);
-
-//AMD Library Routines (PCILIB.C)
-void ReadPCI (IN unsigned int Address, IN unsigned char OpFlag, IN void *Value);
-void WritePCI (IN unsigned int Address, IN unsigned char OpFlag, IN void *Value);
-void RWPCI (IN unsigned int Address, IN unsigned char OpFlag, IN unsigned int Mask, IN unsigned int Data);
-
-//AMD Library Routines (SBPELIB.C)
-/**
- * Read Southbridge Revision ID cie Base
- *
- *
- * @retval 0xXXXXXXXX Revision ID
- *
- */
-unsigned char getRevisionID (OUT void);
-
-/**
- * programPciByteTable - Program PCI register by table (8 bits data)
- *
- *
- *
- * @param[in] pPciByteTable - Table data pointer
- * @param[in] dwTableSize - Table length
- *
- */
-void programPciByteTable (IN REG8MASK* pPciByteTable, IN unsigned short dwTableSize);
-
-/**
- * programSbAcpiMmioTbl - Program SB ACPI MMIO register by table (8 bits data)
- *
- *
- *
- * @param[in] pAcpiTbl - Table data pointer
- *
- */
-void programSbAcpiMmioTbl (IN AcpiRegWrite *pAcpiTbl);
-
-/**
- * getChipSysMode - Get Chip status
- *
- *
- * @param[in] Value - Return Chip strap status
- * StrapStatus [15.0] - SB800 chip Strap Status
- * @li <b>0001</b> - Not USED FWH
- * @li <b>0002</b> - Not USED LPC ROM
- * @li <b>0004</b> - EC enabled
- * @li <b>0008</b> - Reserved
- * @li <b>0010</b> - Internal Clock mode
- *
- */
-void getChipSysMode (IN void* Value);
-
-/**
- * Read Southbridge CIMx configuration structure pointer
- *
- *
- *
- * @retval 0xXXXXXXXX CIMx configuration structure pointer.
- *
- */
-AMDSBCFG* getConfigPointer (OUT void);
-
-//AMD Library Routines (PMIOLIB.C)
-/**
- * Read PMIO
- *
- *
- *
- * @param[in] Address - PMIO Offset value
- * @param[in] OpFlag - Access sizes
- * @param[in] Value - Read Data Buffer
- *
- */
-void ReadPMIO (IN unsigned char Address, IN unsigned char OpFlag, IN void* Value);
-
-/**
- * Write PMIO
- *
- *
- *
- * @param[in] Address - PMIO Offset value
- * @param[in] OpFlag - Access sizes
- * @param[in] Value - Write Data Buffer
- *
- */
-void WritePMIO (IN unsigned char Address, IN unsigned char OpFlag, IN void* Value);
-
-/**
- * RWPMIO - Read/Write PMIO
- *
- *
- *
- * @param[in] Address - PMIO Offset value
- * @param[in] OpFlag - Access sizes
- * @param[in] AndMask - Data And Mask 32 bits
- * @param[in] OrMask - Data OR Mask 32 bits
- *
- */
-void RWPMIO (IN unsigned char Address, IN unsigned char OpFlag, IN unsigned int AndMask, IN unsigned int OrMask);
-
-//AMD Library Routines (PMIO2LIB.C)
-
-/**
- * Read PMIO2
- *
- *
- *
- * @param[in] Address - PMIO2 Offset value
- * @param[in] OpFlag - Access sizes
- * @param[in] Value - Read Data Buffer
- *
- */
-void ReadPMIO2 (IN unsigned char Address, IN unsigned char OpFlag, IN void* Value);
-
-/**
- * Write PMIO 2
- *
- *
- *
- * @param[in] Address - PMIO2 Offset value
- * @param[in] OpFlag - Access sizes
- * @param[in] Value - Write Data Buffer
- *
- */
-void WritePMIO2 (IN unsigned char Address, IN unsigned char OpFlag, IN void* Value);
-
-/**
- * RWPMIO2 - Read/Write PMIO2
- *
- *
- *
- * @param[in] Address - PMIO2 Offset value
- * @param[in] OpFlag - Access sizes
- * @param[in] AndMask - Data And Mask 32 bits
- * @param[in] OrMask - Data OR Mask 32 bits
- *
- */
-void RWPMIO2 (IN unsigned char Address, IN unsigned char OpFlag, IN unsigned int AndMask, IN unsigned int OrMask);
-//AMD Library Routines (ECLIB.C)
-// ECLIB Routines
-
-// #ifndef NO_EC_SUPPORT
-
-/**
- * EnterEcConfig - Force EC into Config mode
- *
- *
- *
- *
- */
-void EnterEcConfig (void);
-
-/**
- * ExitEcConfig - Force EC exit Config mode
- *
- *
- *
- *
- */
-void ExitEcConfig (void);
-
-/**
- * ReadEC8 - Read EC register data
- *
- *
- *
- * @param[in] Address - EC Register Offset Value
- * @param[in] Value - Read Data Buffer
- *
- */
-void ReadEC8 (IN unsigned char Address, IN unsigned char* Value);
-
-/**
- * WriteEC8 - Write date into EC register
- *
- *
- *
- * @param[in] Address - EC Register Offset Value
- * @param[in] Value - Write Data Buffer
- *
- */
-void WriteEC8 (IN unsigned char Address, IN unsigned char* Value);
-
-/**
- * RWEC8 - Read/Write EC register
- *
- *
- *
- * @param[in] Address - EC Register Offset Value
- * @param[in] AndMask - Data And Mask 8 bits
- * @param[in] OrMask - Data OR Mask 8 bits
- *
- */
-void RWEC8 (IN unsigned char Address, IN unsigned char AndMask, IN unsigned char OrMask);
-
-/**
- * IsZoneFuncEnable - check every zone support function with BitMap from user define
- *
- */
-unsigned char IsZoneFuncEnable ( unsigned short Flag, unsigned char func, unsigned char Zone);
-
-void sbECfancontrolservice (IN AMDSBCFG* pConfig);
-void SBIMCFanInitializeS3 (void);
-void GetSbAcpiMmioBase (OUT unsigned int* AcpiMmioBase);
-void GetSbAcpiPmBase (OUT unsigned short* AcpiPmBase);
-
-// #endif
-
diff --git a/src/vendorcode/amd/cimx/sb800/SBMAIN.c b/src/vendorcode/amd/cimx/sb800/SBMAIN.c
deleted file mode 100644
index a494d30..0000000
--- a/src/vendorcode/amd/cimx/sb800/SBMAIN.c
+++ /dev/null
@@ -1,258 +0,0 @@
-/**
- * @file
- *
- * SB Initialization.
- *
- * Init IOAPIC/IOMMU/Misc NB features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: CIMx-SB
- * @e sub-project:
- * @e \$Revision:$ @e \$Date:$
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "SBPLATFORM.h"
-#include "cbtypes.h"
-
-#ifndef B1_IMAGE
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * sbBeforePciInit - Config Southbridge before PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-
-VOID
-sbBeforePciInit (
- IN AMDSBCFG* pConfig
- )
-{
- commonInitEarlyBoot (pConfig);
- commonInitEarlyPost (pConfig);
-#ifndef NO_EC_SUPPORT
- ecInitBeforePciEnum (pConfig);
-#endif
- usbInitBeforePciEnum (pConfig); // USB POST TIME Only
- sataInitBeforePciEnum (pConfig); // Init SATA class code and PHY
- gecInitBeforePciEnum (pConfig); // Init GEC
- azaliaInitBeforePciEnum (pConfig); // Detect and configure High Definition Audio
- sbPcieGppEarlyInit (pConfig); // Gpp port init
- abSpecialSetBeforePciEnum (pConfig);
- usbDesertPll (pConfig);
-}
-
-/**
- * sbAfterPciInit - Config Southbridge after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-sbAfterPciInit (
- IN AMDSBCFG* pConfig
- )
-{
- usbInitAfterPciInit (pConfig); // Init USB MMIO
- sataInitAfterPciEnum (pConfig); // SATA port enumeration
- gecInitAfterPciEnum (pConfig);
- azaliaInitAfterPciEnum (pConfig); // Detect and configure High Definition Audio
-
-#ifndef NO_HWM_SUPPORT
- hwmInit (pConfig);
-#endif
-}
-
-/**
- * sbMidPostInit - Config Southbridge during middle of POST
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-sbMidPostInit (
- IN AMDSBCFG* pConfig
- )
-{
- sataInitMidPost (pConfig);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * sbLatePost - Prepare Southbridge to boot to OS.
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-sbLatePost (
- IN AMDSBCFG* pConfig
- )
-{
-// UINT16 dwVar;
- BUILDPARAM *pStaticOptions;
- pStaticOptions = &(pConfig->BuildParameters);
- commonInitLateBoot (pConfig);
- sataInitLatePost (pConfig);
- gecInitLatePost (pConfig);
- hpetInit (pConfig, pStaticOptions); // SB Configure HPET base and enable bit
-#ifndef NO_EC_SUPPORT
- ecInitLatePost (pConfig);
-#endif
- sbPcieGppLateInit (pConfig);
-
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * sbBeforePciRestoreInit - Config Southbridge before ACPI S3 resume PCI config device restore
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-
-VOID
-sbBeforePciRestoreInit (
- IN AMDSBCFG* pConfig
- )
-{
- pConfig->S3Resume = 1;
- commonInitEarlyBoot (pConfig); // set /SMBUS/ACPI/IDE/LPC/PCIB
- abLinkInitBeforePciEnum (pConfig); // Set ABCFG registers
- usbInitBeforePciEnum (pConfig); // USB POST TIME Only
- sataInitBeforePciEnum (pConfig);
- gecInitBeforePciEnum (pConfig); // Init GEC
- azaliaInitBeforePciEnum (pConfig); // Detect and configure High Definition Audio
- sbPcieGppEarlyInit (pConfig); // Gpp port init
- abSpecialSetBeforePciEnum (pConfig);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * sbAfterPciRestoreInit - Config Southbridge after ACPI S3 resume PCI config device restore
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-
-VOID
-sbAfterPciRestoreInit (
- IN AMDSBCFG* pConfig
- )
-{
- BUILDPARAM *pStaticOptions;
-
- pConfig->S3Resume = 1;
-
- usbSetPllDuringS3 (pConfig);
- pStaticOptions = &(pConfig->BuildParameters);
- commonInitLateBoot (pConfig);
- sataInitAfterPciEnum (pConfig);
- gecInitAfterPciEnum (pConfig);
- azaliaInitAfterPciEnum (pConfig); // Detect and configure High Definition Audio
- hpetInit (pConfig, pStaticOptions); // SB Configure HPET base and enable bit
- sataInitLatePost (pConfig);
- c3PopupSetting (pConfig);
-
-#ifndef NO_HWM_SUPPORT
- SBIMCFanInitializeS3 ();
-#endif
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * sbSmmAcpiOn - Config Southbridge during ACPI_ON
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-sbSmmAcpiOn (
- IN AMDSBCFG* pConfig
- )
-{
- // Commented the following code since we need to leave the IRQ1/12 filtering enabled always as per latest
- // recommendation in RPR. This is required to fix the keyboard stuck issue when playing games under Windows
- AMDSBCFG* pTmp; //lx-dummy for /W4 build
- pTmp = pConfig;
-
- // Disable Power Button SMI
- RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB2, AccWidthUint8, ~(BIT4 + BIT5), 0);
- RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGAC, AccWidthUint8, ~(BIT6 + BIT7), 0);
-}
-
-#endif
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Call Back routine.
- *
- *
- *
- * @param[in] Func Callback ID.
- * @param[in] Data Callback specific data.
- * @param[in] pConfig Southbridge configuration structure pointer.
- */
-UINT32
-CallBackToOEM (
- IN UINT32 Func,
- IN UINT32 Data,
- IN AMDSBCFG* pConfig
- )
-{
- UINT32 Result;
- Result = 0;
- if ( pConfig->StdHeader.CALLBACK.CalloutPtr == NULL ) return Result;
- Result = (pConfig->StdHeader.CALLBACK.CalloutPtr) ( Func, Data, pConfig);
-
- return Result;
-}
-
-
diff --git a/src/vendorcode/amd/cimx/sb800/SBPELIB.c b/src/vendorcode/amd/cimx/sb800/SBPELIB.c
deleted file mode 100644
index 403f21f..0000000
--- a/src/vendorcode/amd/cimx/sb800/SBPELIB.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/**
- * @file
- *
- * Southbridge IO access common routine
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: CIMx-SB
- * @e sub-project:
- * @e \$Revision:$ @e \$Date:$
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "SBPLATFORM.h"
-#include "cbtypes.h"
-
-/**
- * Read Southbridge Revision ID cie Base
- *
- *
- * @retval 0xXXXXXXXX Revision ID
- *
- */
-UINT8
-getRevisionID (
- OUT VOID
- )
-{
- UINT8 dbVar0;
- ReadPCI (((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG08), AccWidthUint8, &dbVar0);
- return dbVar0;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * programPciByteTable - Program PCI register by table (8 bits data)
- *
- *
- *
- * @param[in] pPciByteTable - Table data pointer
- * @param[in] dwTableSize - Table length
- *
- */
-VOID
-programPciByteTable (
- IN REG8MASK* pPciByteTable,
- IN UINT16 dwTableSize
- )
-{
- UINT8 i;
- UINT8 dbBusNo;
- UINT8 dbDevFnNo;
- UINT32 ddBDFR;
-
- dbBusNo = pPciByteTable->bRegIndex;
- dbDevFnNo = pPciByteTable->bANDMask;
- pPciByteTable++;
-
- for ( i = 1; i < dwTableSize; i++ ) {
- if ( (pPciByteTable->bRegIndex == 0xFF) && (pPciByteTable->bANDMask == 0xFF) && (pPciByteTable->bORMask == 0xFF) ) {
- pPciByteTable++;
- dbBusNo = pPciByteTable->bRegIndex;
- dbDevFnNo = pPciByteTable->bANDMask;
- pPciByteTable++;
- i++;
- } else {
- ddBDFR = (dbBusNo << 24) + (dbDevFnNo << 16) + (pPciByteTable->bRegIndex) ;
- RWPCI (ddBDFR, AccWidthUint8 | S3_SAVE, pPciByteTable->bANDMask, pPciByteTable->bORMask);
- pPciByteTable++;
- }
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * programSbAcpiMmioTbl - Program SB ACPI MMIO register by table (8 bits data)
- *
- *
- *
- * @param[in] pAcpiTbl - Table data pointer
- *
- */
-VOID
-programSbAcpiMmioTbl (
- IN AcpiRegWrite *pAcpiTbl
- )
-{
- UINT8 i;
- UINT32 ddtempVar;
- if (pAcpiTbl != NULL) {
- for ( i = 1; pAcpiTbl->MmioBase < 0xf0; i++ ) {
- ddtempVar = 0xFED80000 | (pAcpiTbl->MmioBase) << 8 | pAcpiTbl->MmioReg;
- RWMEM (ddtempVar, AccWidthUint8, ((pAcpiTbl->DataANDMask) | 0xFFFFFF00), pAcpiTbl->DataOrMask);
- pAcpiTbl++;
- }
- }
-}
-
-/**
- * getChipSysMode - Get Chip status
- *
- *
- * @param[in] Value - Return Chip strap status
- * StrapStatus [15.0] - SB800 chip Strap Status
- * @li <b>0001</b> - Not USED FWH
- * @li <b>0002</b> - Not USED LPC ROM
- * @li <b>0004</b> - EC enabled
- * @li <b>0008</b> - Reserved
- * @li <b>0010</b> - Internal Clock mode
- *
- */
-VOID
-getChipSysMode (
- IN VOID* Value
- )
-{
- ReadMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80, AccWidthUint8, Value);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read Southbridge CIMx configuration structure pointer
- *
- *
- *
- * @retval 0xXXXXXXXX CIMx configuration structure pointer.
- *
- */
-AMDSBCFG*
-getConfigPointer (
- OUT VOID
- )
-{
- UINT8 dbReg;
- UINT8 dbValue;
- UINT8 i;
- UINT32 ddValue;
- ddValue = 0;
- dbReg = SB_ECMOS_REG08;
-
- for ( i = 0; i <= 3; i++ ) {
- WriteIO (SB_IOMAP_REG72, AccWidthUint8, &dbReg);
- ReadIO (SB_IOMAP_REG73, AccWidthUint8, &dbValue);
- ddValue |= (dbValue << (i * 8));
- dbReg++;
- }
- return ( (AMDSBCFG*) (UINTN)ddValue);
-}
-
-/**
- * getEfuseStatue - Get Efuse status
- *
- *
- * @param[in] Value - Return Chip strap status
- *
- */
-VOID
-getEfuseStatus (
- IN VOID* Value
- )
-{
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, ~BIT5, BIT5);
- WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, Value);
- ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8 + 1, AccWidthUint8, Value);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, ~BIT5, 0);
-}
diff --git a/src/vendorcode/amd/cimx/sb800/SBPort.c b/src/vendorcode/amd/cimx/sb800/SBPort.c
deleted file mode 100644
index 048850d..0000000
--- a/src/vendorcode/amd/cimx/sb800/SBPort.c
+++ /dev/null
@@ -1,366 +0,0 @@
-
-/**
- * @file
- *
- * Southbridge Init during POWER-ON
- *
- * Prepare Southbridge environment during power on stage.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: CIMx-SB
- * @e sub-project:
- * @e \$Revision:$ @e \$Date:$
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "SBPLATFORM.h"
-#include "cbtypes.h"
-/**
- * sbPorInitPciTable - PCI device registers initial during the power on stage.
- */
-const static REG8MASK sbPorInitPciTable[] =
-{
- // SATA device
- {0x00, SATA_BUS_DEV_FUN, 0},
- {SB_SATA_REG84 + 3, ~BIT2, 0},
- {SB_SATA_REG84 + 1, ~(BIT4 + BIT5), BIT4 + BIT5},
- {SB_SATA_REGA0, ~(BIT2 + BIT3 + BIT4 + BIT5 + BIT6), BIT2 + BIT3 + BIT4 + BIT5},
- {0xFF, 0xFF, 0xFF},
- // LPC Device (Bus 0, Dev 20, Func 3)
- {0x00, LPC_BUS_DEV_FUN, 0},
- {SB_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2},
- {SB_LPC_REG7C, 0x00, BIT0 + BIT2},
- {SB_LPC_REGBB, 0xFF, BIT3 + BIT4 + BIT5},
- // A12 set 0xBB [5:3] = 111 to improve SPI timing margin.
- // A12 Set 0xBA [6:5] = 11 improve SPI timing margin. (SPI Prefetch enhancement)
- {SB_LPC_REGBB, 0xBE, BIT0 + BIT3 + BIT4 + BIT5},
- {SB_LPC_REGBA, 0x9F, BIT5 + BIT6},
- {0xFF, 0xFF, 0xFF},
- // P2P Bridge (Bus 0, Dev 20, Func 4)
- {0x00, PCIB_BUS_DEV_FUN, 0},
- {SB_PCIB_REG4B, 0xFF, BIT6 + BIT7 + BIT4},
- // Enable IO but not allocate any IO range. This is for post code display on debug port behind P2P bridge.
- {SB_PCIB_REG1C, 0x00, 0xF0},
- {SB_PCIB_REG1D, 0x00, 0x00},
- {SB_PCIB_REG04, 0x00, 0x21},
- {SB_PCIB_REG40, 0xDF, 0x20},
- {SB_PCIB_REG50, 0x02, 0x01},
- {0xFF, 0xFF, 0xFF},
-};
-
-/**
- * sbPmioPorInitTable - Southbridge ACPI MMIO initial during the power on stage.
- */
-const static AcpiRegWrite sbPmioPorInitTable[] =
-{
- {PMIO_BASE >> 8, SB_PMIOA_REG5D, 0x00, BIT0},
- {PMIO_BASE >> 8, SB_PMIOA_REGD2, 0xCF, BIT4 + BIT5},
- {SMBUS_BASE >> 8, SB_SMBUS_REG12, 0x00, BIT0},
- {PMIO_BASE >> 8, SB_PMIOA_REG28, 0xFF, BIT0},
- {PMIO_BASE >> 8, SB_PMIOA_REG44 + 3, 0x7F, BIT7},
- {PMIO_BASE >> 8, SB_PMIOA_REG48, 0xFF, BIT0},
- {PMIO_BASE >> 8, SB_PMIOA_REG00, 0xFF, 0x0E},
- {PMIO_BASE >> 8, SB_PMIOA_REG00 + 2, 0xFF, 0x40},
- {PMIO_BASE >> 8, SB_PMIOA_REG00 + 3, 0xFF, 0x08},
- {PMIO_BASE >> 8, SB_PMIOA_REG34, 0xEF, BIT0 + BIT1},
- {PMIO_BASE >> 8, SB_PMIOA_REGEC, 0xFD, BIT1},
- {PMIO_BASE >> 8, SB_PMIOA_REG5B, 0xF9, BIT1 + BIT2},
- {PMIO_BASE >> 8, SB_PMIOA_REG08, 0xFE, BIT2 + BIT4},
- {PMIO_BASE >> 8, SB_PMIOA_REG08 + 1, 0xFF, BIT0},
- {PMIO_BASE >> 8, SB_PMIOA_REG54, 0x00, BIT4 + BIT7},
- {PMIO_BASE >> 8, SB_PMIOA_REG04 + 3, 0xFD, BIT1},
- {PMIO_BASE >> 8, SB_PMIOA_REG74, 0xF6, BIT0 + BIT3},
- {PMIO_BASE >> 8, SB_PMIOA_REGF0, ~BIT2, 0x00},
- // RPR GEC I/O Termination Setting
- // PM_Reg 0xF6 = Power-on default setting
- // PM_Reg 0xF7 = Power-on default setting
- // PM_Reg 0xF8 = 0x6C
- // PM_Reg 0xF9 = 0x21
- // PM_Reg 0xFA = 0x00 SB800 A12 GEC I/O Pad settings for 3.3V CMOS
- {PMIO_BASE >> 8, SB_PMIOA_REGF8, 0x00, 0x6C},
- {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 1, 0x00, 0x27},
- {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 2, 0x00, 0x00},
- {PMIO_BASE >> 8, SB_PMIOA_REGC4, 0xFE, 0x14},
- {PMIO_BASE >> 8, SB_PMIOA_REGC0 + 2, 0xBF, 0x40},
-
- {PMIO_BASE >> 8, SB_PMIOA_REGBE, 0xDF, BIT5},//ENH210907 SB800: request to no longer clear kb_pcirst_en (bit 1) of PM_Reg BEh per the RPR
-
- {0xFF, 0xFF, 0xFF, 0xFF},
-};
-
-/**
- * sbPowerOnInit - Config Southbridge during power on stage.
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-sbPowerOnInit (
- IN AMDSBCFG* pConfig
- )
-{
-
- UINT8 dbPortStatus;
- UINT8 dbSysConfig;
- UINT32 abValue;
- UINT8 dbValue;
- UINT8 dbEfuse;
- UINT8 dbCg2WR;
- UINT8 dbCg1Pll;
- UINT8 cimNbSbGen2;
- UINT8 cimSataMode;
- UINT8 cimSpiFastReadEnable;
- UINT8 cimSpiFastReadSpeed;
- UINT8 cimSioHwmPortEnable;
- UINT8 SataPortNum;
-
- cimNbSbGen2 = pConfig->NbSbGen2;
- cimSataMode = pConfig->SATAMODE.SataModeReg;
-// Adding Fast Read Function support
- if (pConfig->BuildParameters.SpiFastReadEnable != 0 ) {
- cimSpiFastReadEnable = (UINT8) pConfig->BuildParameters.SpiFastReadEnable;
- } else {
- cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
- }
- cimSpiFastReadSpeed = (UINT8) pConfig->BuildParameters.SpiFastReadSpeed;
- cimSioHwmPortEnable = pConfig->SioHwmPortEnable;
-#if SB_CIMx_PARAMETER == 0
- cimNbSbGen2 = cimNbSbGen2Default;
- cimSataMode = (UINT8) ((cimSataMode & 0xFB) | cimSataSetMaxGen2Default);
- cimSataMode = (UINT8) ((cimSataMode & 0x0F) | (cimSATARefClkSelDefault + cimSATARefDivSelDefault));
- cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
- cimSpiFastReadSpeed = cimSpiFastReadSpeedDefault;
- cimSioHwmPortEnable = cimSioHwmPortEnableDefault;
-#endif
-
-// SB800 Only Enabled (Mmio_mem_enablr) // Default value is correct
- RWPMIO (SB_PMIOA_REG24, AccWidthUint8, 0xFF, BIT0);
-
-// Set A-Link bridge access address. This address is set at device 14h, function 0,
-// register 0f0h. This is an I/O address. The I/O address must be on 16-byte boundary.
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGE0, AccWidthUint32, 00, ALINK_ACCESS_INDEX);
- writeAlink (0x80000004, 0x04); // RPR 4.2 Enable SB800 to issue memory read/write requests in the upstream direction
- abValue = readAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29)); // RPR 4.5 Disable the credit variable in the downstream arbitration equation
- abValue = abValue | BIT0;
- writeAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29), abValue);
- writeAlink (0x30, 0x10); // AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform.
- writeAlink (0x34, readAlink (0x34) | BIT9);
-
- dbEfuse = FUSE_ID_EFUSE_LOC;
- getEfuseStatus (&dbEfuse);
- if ( dbEfuse == M1_D1_FUSE_ID ) {
- dbEfuse = MINOR_ID_EFUSE_LOC;
- getEfuseStatus (&dbEfuse);
- if ( dbEfuse == M1_MINOR_ID ) {
- // Limit ALink speed to 2.5G if Hudson-M1
- cimNbSbGen2 = 0;
- }
- }
-// Step 1:
-// AXINDP_Reg 0xA4[0] = 0x1
-// Step 2:
-// AXCFG_Reg 0x88[3:0] = 0x2
-// Step3:
-// AXINDP_Reg 0xA4[18] = 0x1
- if ( cimNbSbGen2 == TRUE ) {
- rwAlink (SB_AX_INDXP_REGA4, 0xFFFFFFFF, BIT0);
- rwAlink ((UINT32)SB_AX_CFG_REG88, 0xFFFFFFF0, 0x2);
- rwAlink (SB_AX_INDXP_REGA4, 0xFFFFFFFF, BIT18);
- }
-
-// Set Build option into SB
- WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioPmeBaseAddress));
- if (cimSioHwmPortEnable) {
- // Use Wide IO Port 1 to provide access to the superio HWM registers.
- WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG66 , AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioHwmBaseAddress));
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG48 + 3, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); // Wide IO Port 1: enable
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG74 , AccWidthUint8 | S3_SAVE, 0xFF, BIT2); // set width 0:512, 1:16 bytes
- }
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F, (pConfig->BuildParameters.SpiRomBaseAddress));
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint32 | S3_SAVE, 0, (pConfig->BuildParameters.GecShadowRomBase + 1));
-// Enabled SMBUS0/SMBUS1 (ASF) Base Address
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2C, AccWidthUint16, 06, (pConfig->BuildParameters.Smbus0BaseAddress) + BIT0); //protect BIT[2:1]
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG28, AccWidthUint16, 00, (pConfig->BuildParameters.Smbus1BaseAddress));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG60, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1EvtBlkAddr));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG62, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1CntBlkAddr));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmTmrBlkAddr));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG66, AccWidthUint16, 00, (pConfig->BuildParameters.CpuControlBlkAddr));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG68, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiGpe0BlkAddr));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6A, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6C, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmaCntBlkAddr));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6E, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr) + 8);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG48, AccWidthUint32, 00, (pConfig->BuildParameters.WatchDogTimerBase));
-
- dbEfuse = SATA_FIS_BASE_EFUSE_LOC;
- getEfuseStatus (&dbEfuse);
-
- programSbAcpiMmioTbl ((AcpiRegWrite*) FIXUP_PTR (&sbPmioPorInitTable[0]));
-
-
- SataPortNum = 0;
- for ( SataPortNum = 0; SataPortNum < 0x06; SataPortNum++ ) {
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, 1 << SataPortNum);
- SbStall (2);
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, (0xFF ^ (1 << SataPortNum)) , 0x00);
- SbStall (2);
- }
-
-
- //The following bits must be set before enabling SPI prefetch.
- // Set SPI MMio bit offset 00h[19] to 1 and offset 00h[26:24] to 111, offset 0ch[21:16] to 1, Set LPC cfg BBh[6] to 0 ( by default it is 0).
- // if Ec is enable
- // Maximum spi speed that can be supported by SB is 22M (SPI Mmio offset 0ch[13:12] to 10) if the rom can run at the speed.
- // else
- // Maximum spi speed that can be supported by SB is 33M (SPI Mmio offset 0ch[13:12] to 01 in normal mode or offset 0ch[15:14] in fast mode) if the rom can run at
- // the speed.
- getChipSysMode (&dbSysConfig);
- if (pConfig->BuildParameters.SpiSpeed < 0x02) {
- pConfig->BuildParameters.SpiSpeed = 0x01;
- if (dbSysConfig & ChipSysEcEnable) pConfig->BuildParameters.SpiSpeed = 0x02;
- }
-
- if (pConfig->SbSpiSpeedSupport) {
- RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, (BIT19 + BIT24 + BIT25 + BIT26));
- RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, 0xFFC0FFFF, 1 << 16 );
- RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT13 + BIT12), (pConfig->BuildParameters.SpiSpeed << 12));
- }
- // SPI Fast Read Function
- if ( cimSpiFastReadEnable ) {
- RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFBFFFF, BIT18);
- } else {
- RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFBFFFF, 0x00);
- }
-
- if ( cimSpiFastReadSpeed ) {
- RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT15 + BIT14), ( cimSpiFastReadSpeed << 14));
- }
- //Program power on pci init table
- programPciByteTable ( (REG8MASK*) FIXUP_PTR (&sbPorInitPciTable[0]), sizeof (sbPorInitPciTable) / sizeof (REG8MASK) );
-
- programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr));
-
- dbValue = 0x0A;
- WriteIO (SB_IOMAP_REG70, AccWidthUint8, &dbValue);
- ReadIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
- dbValue &= 0xEF;
- WriteIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
-
-// Change the CG PLL multiplier to x1.1
- if ( pConfig->UsbRxMode !=0 ) {
- dbCg2WR = 0x00;
- dbCg1Pll = 0x3A;
- ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, &dbCg2WR);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, 0, 0x3A);
- ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD9, AccWidthUint8, &dbCg1Pll);
- dbCg2WR &= BIT4;
- if (( dbCg2WR == 0x00 ) && ( dbCg1Pll !=0x10 ))
- {
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x18, AccWidthUint8, 0xE1, 0x10);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, 0, 0x3A);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD9, AccWidthUint8, 0, USB_PLL_Voltage);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, 0xEF, 0x10);
- dbValue = 0x06;
- WriteIO (0xCF9, AccWidthUint8, &dbValue);
- } else {
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, 0xEF, 0x00);
- }
- }
-
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint32 | S3_SAVE, ~(pConfig->BuildParameters.BiosSize << 4), 0);
-
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0, (pConfig->SATAMODE.SataModeReg) & 0xFD );
-
- if (dbEfuse & BIT0) {
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0xFB, 0x04);
- }
-
- ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, &dbPortStatus);
- if ( ((dbPortStatus & 0xF0) == 0x10) ) {
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_PMIOA_REG08, AccWidthUint8, 0, BIT5);
- }
-
- if ( pConfig->BuildParameters.LegacyFree ) {
- RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000);
- } else {
- RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5);
- }
-
- dbValue = 0x09;
- WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue);
- ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
- if ( !pConfig->BuildParameters.EcKbd ) {
- // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
- dbValue = dbValue & 0xF9;
- }
- if ( pConfig->BuildParameters.LegacyFree ) {
- // Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation.
- dbValue = dbValue & 0x9F;
- }
- // Enabled IRQ input
- dbValue = dbValue | BIT4;
- WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
-
-#ifndef NO_EC_SUPPORT
- getChipSysMode (&dbPortStatus);
- if ( ((dbPortStatus & ChipSysEcEnable) == 0x00) ) {
- // EC is disabled by jumper setting or board config
- RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4), AccWidthUint16 | S3_SAVE, 0xFFFE, BIT0);
- } else {
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xF7, 0x08);
- ecPowerOnInit ( pConfig);
- }
-#endif
-
- ReadMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80, AccWidthUint8, &dbValue);
- if (dbValue & ChipSysIntClkGen) {
- ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, &dbValue);
- if (dbValue & BIT2) {
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC0 + 2, AccWidthUint8, 0xDF, 0x20);
- } else {
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xFB, 0x40);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC0 + 2, AccWidthUint8, 0xDF, 0x20);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xFB, 0x00);
- }
- }
-
- // Restore GPP clock to on as it may be off during last POST when some device was disabled;
- // the device can't be detected if enabled again as the values retain on S5 and warm reset.
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG00, AccWidthUint32, 0xFFFFFFFF, 0xFFFFFFFF);
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG04, AccWidthUint8, 0xFF, 0xFF);
-
- // Set PMx88[5]to enable LdtStp# output to do the C3 or FidVid transation
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8, 0xFF, BIT5);
-}
diff --git a/src/vendorcode/amd/cimx/sb800/SBSUBFUN.h b/src/vendorcode/amd/cimx/sb800/SBSUBFUN.h
deleted file mode 100644
index 6b8c8d4..0000000
--- a/src/vendorcode/amd/cimx/sb800/SBSUBFUN.h
+++ /dev/null
@@ -1,523 +0,0 @@
-/**
- * @file
- *
- * Southbridge CIMx Function Support Define (All)
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: CIMx-SB
- * @e sub-project:
- * @e \$Revision:$ @e \$Date:$
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-// Southbridge SBMAIN Routines
-
-/**
- * Southbridge Main Function Public Function
- *
- */
-
-/**
- * sbBeforePciInit - Config Southbridge before PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void sbBeforePciInit (IN AMDSBCFG* pConfig);
-
-
-/**
- * sbAfterPciInit - Config Southbridge after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void sbAfterPciInit (IN AMDSBCFG* pConfig);
-
-/**
- * sbMidPostInit - Config Southbridge during middle of POST
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void sbMidPostInit (IN AMDSBCFG* pConfig);
-
-/**
- * sbLatePost - Prepare Southbridge to boot to OS.
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void sbLatePost (IN AMDSBCFG* pConfig);
-
-/**
- * sbBeforePciRestoreInit - Config Southbridge before ACPI S3 resume PCI config device restore
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void sbBeforePciRestoreInit (IN AMDSBCFG* pConfig);
-
-/**
- * sbAfterPciRestoreInit - Config Southbridge after ACPI S3 resume PCI config device restore
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void sbAfterPciRestoreInit (IN AMDSBCFG* pConfig);
-
-/**
- * sbSmmAcpiOn - Config Southbridge during ACPI_ON
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void sbSmmAcpiOn (IN AMDSBCFG* pConfig);
-
-/**
- * CallBackToOEM - Call Back routine.
- *
- *
- *
- * @param[in] Func Callback ID.
- * @param[in] Data Callback specific data.
- * @param[in] pConfig Southbridge configuration structure pointer.
- */
-unsigned int CallBackToOEM (IN unsigned int Func, IN unsigned int Data, IN AMDSBCFG* pConfig);
-
-
-// Southbridge SBPOR Routines
-
-/**
- * Southbridge power-on initial Public Function
- *
- */
-
-/**
- * sbPowerOnInit - Config Southbridge during power on stage.
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void sbPowerOnInit (IN AMDSBCFG* pConfig);
-
-
-// Southbridge Common Routines
-
-/**
- * Southbridge Common Public Function
- *
- */
-
-/**
- * commonInitEarlyBoot - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB.
- *
- * This settings should be done during S3 resume also
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void commonInitEarlyBoot (IN AMDSBCFG* pConfig);
-
-/**
- * commonInitEarlyPost - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB.
- *
- * This settings might not program during S3 resume
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void commonInitEarlyPost (IN AMDSBCFG* pConfig);
-
-/**
- * commonInitLateBoot - Prepare Southbridge register setting to boot to OS.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void commonInitLateBoot (IN AMDSBCFG* pConfig);
-
-/**
- * abSpecialSetBeforePciEnum - Special setting ABCFG registers before PCI emulation.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void abSpecialSetBeforePciEnum (IN AMDSBCFG* pConfig);
-
-void usbSetPllDuringS3 (IN AMDSBCFG* pConfig);
-void usbDesertPll (IN AMDSBCFG* pConfig);
-
-/**
- * hpetInit - Program Southbridge HPET function
- *
- * ** Eric
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- * @param[in] pStaticOptions Platform build configuration table.
- *
- */
-void hpetInit (IN AMDSBCFG* pConfig, IN BUILDPARAM *pStaticOptions);
-
-/**
- * c3PopupSetting - Program Southbridge C state function
- *
- * ** Eric
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void c3PopupSetting (IN AMDSBCFG* pConfig);
-
-/**
- * FusionRelatedSetting - Program Fusion C related function
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void FusionRelatedSetting (IN AMDSBCFG* pConfig);
-
-/**
- * Southbridge Common Private Function
- *
- */
-
-/**
- * abLinkInitBeforePciEnum - Set ABCFG registers before PCI emulation.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void abLinkInitBeforePciEnum (IN AMDSBCFG* pConfig);
-
-// Southbridge SATA Routines
-
-/**
- * Southbridge SATA Controller Public Function
- *
- */
-
-/**
- * sataInitMidPost - Config SATA controller in Middle POST.
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void sataInitMidPost (IN AMDSBCFG* pConfig);
-
-/**
- * sataInitAfterPciEnum - Config SATA controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void sataInitAfterPciEnum (IN AMDSBCFG* pConfig);
-
-/**
- * sataInitBeforePciEnum - Config SATA controller before PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void sataInitBeforePciEnum (IN AMDSBCFG* pConfig);
-
-/**
- * sataInitLatePost - Prepare SATA controller to boot to OS.
- *
- * - Set class ID to AHCI (if set to AHCI * Mode)
- * - Enable AHCI interrupt
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void sataInitLatePost (IN AMDSBCFG* pConfig);
-
-// Southbridge GEC Routines
-
-/**
- * Southbridge GEC Controller Public Function
- *
- */
-
-/**
- * gecInitBeforePciEnum - Config GEC controller before PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void gecInitBeforePciEnum (IN AMDSBCFG* pConfig);
-
-/**
- * gecInitAfterPciEnum - Config GEC controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void gecInitAfterPciEnum (IN AMDSBCFG* pConfig);
-
-/**
- * gecInitLatePost - Prepare GEC controller to boot to OS.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void gecInitLatePost (IN AMDSBCFG* pConfig);
-
-// Southbridge USB Routines
-
-/**
- * Southbridge USB Controller Public Function
- *
- */
-
-/**
- * Config USB controller before PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void usbInitBeforePciEnum (IN AMDSBCFG* pConfig);
-
-/**
- * Config USB controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void usbInitAfterPciInit (IN AMDSBCFG* pConfig);
-
-/**
- * Config USB1 EHCI controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void usb1EhciInitAfterPciInit (IN AMDSBCFG* pConfig);
-void usb2EhciInitAfterPciInit (IN AMDSBCFG* pConfig);
-void usb3EhciInitAfterPciInit (IN AMDSBCFG* pConfig);
-void usb1OhciInitAfterPciInit (IN AMDSBCFG* pConfig);
-void usb2OhciInitAfterPciInit (IN AMDSBCFG* pConfig);
-void usb3OhciInitAfterPciInit (IN AMDSBCFG* pConfig);
-void usb4OhciInitAfterPciInit (IN AMDSBCFG* pConfig);
-
-// Southbridge SMI Service Routines (SMM.C)
-
-/**
- * Southbridge SMI Service Routines Public Function
- *
- */
-
-/**
- * Southbridge SMI service module
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void sbSmmService (IN AMDSBCFG* pConfig);
-
-/**
- * softwareSMIservice - Software SMI service
- *
- * ** Eric
- *
- * @param[in] void Southbridge software SMI service ID.
- *
- */
-void softwareSMIservice (IN void);
-
-// Southbridge GPP Controller Routines
-
-/**
- * Southbridge GPP Controller Routines Public Function
- *
- */
-
-/**
- * GPP early programming and link training. On exit all populated EPs should be fully operational.
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void sbPcieGppEarlyInit (IN AMDSBCFG* pConfig);
-
-/**
- * sbPcieGppLateInit - Late PCIE initialization for SB800 GPP component
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void sbPcieGppLateInit (IN AMDSBCFG* pConfig);
-
-// Southbridge HD Controller Routines (AZALIA.C)
-
-/**
- * Southbridge HD Controller Routines (AZALIA.C) Public Function
- *
- */
-
-/**
- * Config HD Audio Before PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void azaliaInitBeforePciEnum (IN AMDSBCFG* pConfig);
-
-/**
- * Config HD Audio after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-void azaliaInitAfterPciEnum (IN AMDSBCFG* pConfig);
-
-
-// Southbridge EC Routines
-
-#ifndef NO_EC_SUPPORT
-/**
- * Southbridge EC Controller Public Function
- *
- */
-
-/**
- * Config EC controller during power-on
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
- void ecPowerOnInit (IN AMDSBCFG* pConfig);
-
-/**
- * Config EC controller before PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
- void ecInitBeforePciEnum (IN AMDSBCFG* pConfig);
-
-/**
- * Prepare EC controller to boot to OS.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
- void ecInitLatePost (IN AMDSBCFG* pConfig);
-
-/**
- * validateImcFirmware - Validate IMC Firmware.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- * @retval TRUE Pass
- * @retval FALSE Failed
- */
- unsigned char validateImcFirmware (IN AMDSBCFG* pConfig);
-
-/**
- * validateImcFirmware - Validate IMC Firmware.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
- void softwareToggleImcStrapping (IN AMDSBCFG* pConfig);
-#endif
-
-#ifndef NO_HWM_SUPPORT
-/**
- * validateImcFirmware - Validate IMC Firmware.
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
- void hwmInit (IN AMDSBCFG* pConfig);
-#endif
-
diff --git a/src/vendorcode/amd/cimx/sb800/SBTYPE.h b/src/vendorcode/amd/cimx/sb800/SBTYPE.h
deleted file mode 100644
index b897950..0000000
--- a/src/vendorcode/amd/cimx/sb800/SBTYPE.h
+++ /dev/null
@@ -1,1135 +0,0 @@
-
-/**
- * @file
- *
- * Southbridge CIMx configuration structure define
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: CIMx-SB
- * @e sub-project:
- * @e \$Revision:$ @e \$Date:$
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _AMD_SBTYPE_H_
-#define _AMD_SBTYPE_H_
-
-#pragma pack (push, 1)
-
-/**
- * Entry point of Southbridge CIMx
- *
- *
- * @param[in] Param1 Southbridge CIMx Function ID.
- * @param[in] Param2 Southbridge Input Data.
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-typedef unsigned int (*SBCIM_HOOK_ENTRY) (unsigned int Param1, unsigned int Param2, void* pConfig);
-/**
- * SMM_SERVICE_ROUTINE - Southbridge SMI service routine
- *
- */
-typedef void (*SMM_SERVICE_ROUTINE) (void);
-
-
-/**
- * The STATIC platform information for CIMx Module.
- *
- */
-typedef struct _BUILDPARAM {
- unsigned int BiosSize:3; /**< BiosSize
- * @par
- * BIOSSize [2.0] - BIOS Image Size
- * @li <b>0</b> - 1M
- * @li <b>1</b> - 2M
- * @li <b>3</b> - 4M
- * @li <b>7</b> - 8M
- * In SB800, default ROM size is 1M Bytes, if your platform ROM bigger then 1M
- * you have to set the ROM size outside CIMx module and before AGESA module get call
- *
- */
- unsigned int LegacyFree:1; /**< LegacyFree
- * @par
- * Config Southbridge CIMx module for Legacy Free Mode
- */
- unsigned int SpiSpeed:2; /**< SpiSpeed
- * @par
- * SPI Speed [1.0] - the clock speed for non-fast read command
- * @li <b>00</b> - 66Mhz
- * @li <b>01</b> - 33Mhz
- * @li <b>10</b> - 22Mhz
- * @li <b>11</b> - 16.5Mhz
- *
- */
- unsigned int ImcEnableOverWrite:2; /**< ImcEnableOverWrite
- * @par
- * Imc Enable OverWrite
- * @li <b>00</b> - by default strapping
- * @li <b>01</b> - On
- * @li <b>10</b> - Off
- *
- */
- unsigned int SpiFastReadEnable:1; /**< SpiFastReadEnable
- * @par
- * @li <b>00</b> - Disable SPI Fast Read Function
- * @li <b>01</b> - Enable SPI Fast Read Function
- */
- unsigned int SpiFastReadSpeed:2; /**< SpiFastReadSpeed
- * @par
- * @li <b>00</b> - 66Mhz
- * @li <b>01</b> - 33Mhz
- * @li <b>10</b> - 22Mhz
- * @li <b>11</b> - 16.5Mhz
- */
- unsigned int SpreadSpectrumType:1; /**< SpreadSpectrumType
- * @par
- * @li <b>0</b> - Spread Spectrum for normal platform
- * @li <b>1</b> - Spread Spectrum for Ontario platform
- */
-/** Dummy0 - Reserved */
- unsigned int Dummy0:4;
- unsigned int EcKbd:1; /**< EcKbd
- * @par
- * EcKbd [16] - Platform use EC (as SIO) or SIO chip for PS/2 Keyboard and Mouse
- * @li <b>0</b> - Use SIO PS/2 function.
- * @li <b>1</b> - Use EC PS/2 function instead of SIO PS/2 function. **
- * @li <b>**</b> When set 1, EC function have to enable, otherwise, CIMx treat as legacy-free system.
- */
-/** EcChannel0 - Reserved */
- unsigned int EcChannel0:1;
-/** UsbMsi - Reserved */
- unsigned int UsbMsi:1;
-/** HdAudioMsi - Reserved */
- unsigned int HdAudioMsi:1;
-/** LpcMsi - Reserved */
- unsigned int LpcMsi:1;
-/** PcibMsi - Reserved */
- unsigned int PcibMsi:1;
-/** AbMsi - Reserved */
- unsigned int AbMsi:1;
-/** Dummy1 - Reserved */
- unsigned int Dummy1:9;
-
- unsigned int Smbus0BaseAddress; /**< Smbus0BaseAddress
- * @par
- * Smbus BASE Address
- */
- unsigned int Smbus1BaseAddress; /**< Smbus1BaseAddress
- * @par
- * Smbus1 (ASF) BASE Address
- */
- unsigned int SioPmeBaseAddress; /**< SioPmeBaseAddress
- * @par
- * SIO PME BASE Address
- */
- unsigned int SioHwmBaseAddress; /**< SioHwmBaseAddress
- * @par
- * SIO HWM BASE Address
- */
- unsigned int WatchDogTimerBase; /**< WatchDogTimerBase
- * @par
- * Watch Dog Timer Address
- */
- unsigned int GecShadowRomBase; /**< GecShadowRomBase
- * @par
- * GEC (NIC) SHADOWROM BASE Address
- */
- unsigned int SpiRomBaseAddress; /**< SpiRomBaseAddress
- * @par
- * SPI ROM BASE Address
- */
- unsigned short AcpiPm1EvtBlkAddr; /**< AcpiPm1EvtBlkAddr
- * @par
- * ACPI PM1 event block Address
- */
- unsigned short AcpiPm1CntBlkAddr; /**< AcpiPm1CntBlkAddr
- * @par
- * ACPI PM1 Control block Address
- */
- unsigned short AcpiPmTmrBlkAddr; /**< AcpiPmTmrBlkAddr
- * @par
- * ACPI PM timer block Address
- */
- unsigned short CpuControlBlkAddr; /**< CpuControlBlkAddr
- * @par
- * ACPI CPU control block Address
- */
- unsigned short AcpiGpe0BlkAddr; /**< AcpiGpe0BlkAddr
- * @par
- * ACPI GPE0 block Address
- */
- unsigned short SmiCmdPortAddr; /**< SmiCmdPortAddr
- * @par
- * SMI command port Address
- */
- unsigned short AcpiPmaCntBlkAddr; /**< AcpiPmaCntBlkAddr
- * @par
- * ACPI PMA Control block Address
- */
- unsigned int HpetBase; /**< HpetBase
- * @par
- * HPET Base address
- */
- unsigned int SataIDESsid; /**< SataIDESsid
- * @par
- * SATA IDE mode SSID
- */
- unsigned int SataRAIDSsid; /**< SataRAIDSsid
- * @par
- * SATA RAID mode SSID
- */
- unsigned int SataRAID5Ssid; /**< SataRAID5Ssid
- * @par
- * SATA RAID5 mode SSID
- */
- unsigned int SataAHCISsid; /**< SataAHCISsid
- * @par
- * SATA AHCI mode SSID
- */
- unsigned int OhciSsid; /**< OhciSsid
- * @par
- * OHCI Controller SSID
- */
- unsigned int EhciSsid; /**< EhciSsid
- * @par
- * EHCI Controller SSID
- */
- unsigned int Ohci4Ssid; /**< Ohci4Ssid
- * @par
- * OHCI4 Controller SSID (Force USB 1.1 mode)
- */
- unsigned int SmbusSsid; /**< SmbusSsid
- * @par
- * SMBUS controller SSID
- */
- unsigned int IdeSsid; /**< IdeSsid
- * @par
- * IDE (Sata) controller SSID
- */
- unsigned int AzaliaSsid; /**< AzaliaSsid
- * @par
- * HD Audio controller SSID
- */
- unsigned int LpcSsid; /**< LpcSsid
- * @par
- * LPC controller SSID
- */
- unsigned int PCIBSsid; /**< PCIBSsid
- * @par
- * PCIB controller SSID
- */
-} BUILDPARAM;
-
-/**
- * The EC fan MSGREG struct for CIMx Module. *
- */
-typedef struct _EC_struct {
- unsigned char MSGFun81zone0MSGREG0; ///<Thermal zone
- unsigned char MSGFun81zone0MSGREG1; ///<Thermal zone
- unsigned char MSGFun81zone0MSGREG2; ///<Thermal zone control byte 1
- unsigned char MSGFun81zone0MSGREG3; ///<Thermal zone control byte 2
- unsigned char MSGFun81zone0MSGREG4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
- unsigned char MSGFun81zone0MSGREG5; ///<Hysteresis inforamtion
- unsigned char MSGFun81zone0MSGREG6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
- unsigned char MSGFun81zone0MSGREG7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
- unsigned char MSGFun81zone0MSGREG8; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
- unsigned char MSGFun81zone0MSGREG9; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
-
- //EC LDN9 funtion 81 zone 1
- unsigned char MSGFun81zone1MSGREG0; ///<Thermal zone
- unsigned char MSGFun81zone1MSGREG1; ///<Thermal zone
- unsigned char MSGFun81zone1MSGREG2; ///<Thermal zone control byte 1
- unsigned char MSGFun81zone1MSGREG3; ///<Thermal zone control byte 2
- unsigned char MSGFun81zone1MSGREG4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
- unsigned char MSGFun81zone1MSGREG5; ///<Hysteresis inforamtion
- unsigned char MSGFun81zone1MSGREG6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
- unsigned char MSGFun81zone1MSGREG7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
- unsigned char MSGFun81zone1MSGREG8; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
- unsigned char MSGFun81zone1MSGREG9; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
-
- //EC LDN9 funtion 81 zone 2
- unsigned char MSGFun81zone2MSGREG0; ///<Thermal zone
- unsigned char MSGFun81zone2MSGREG1; ///<Thermal zone
- unsigned char MSGFun81zone2MSGREG2; ///<Thermal zone control byte 1
- unsigned char MSGFun81zone2MSGREG3; ///<Thermal zone control byte 2
- unsigned char MSGFun81zone2MSGREG4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
- unsigned char MSGFun81zone2MSGREG5; ///<Hysteresis inforamtion
- unsigned char MSGFun81zone2MSGREG6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
- unsigned char MSGFun81zone2MSGREG7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
- unsigned char MSGFun81zone2MSGREG8; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
- unsigned char MSGFun81zone2MSGREG9; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
-
- //EC LDN9 funtion 81 zone 3
- unsigned char MSGFun81zone3MSGREG0; ///<Thermal zone
- unsigned char MSGFun81zone3MSGREG1; ///<Thermal zone
- unsigned char MSGFun81zone3MSGREG2; ///<Thermal zone control byte 1
- unsigned char MSGFun81zone3MSGREG3; ///<Thermal zone control byte 2
- unsigned char MSGFun81zone3MSGREG4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
- unsigned char MSGFun81zone3MSGREG5; ///<Hysteresis inforamtion
- unsigned char MSGFun81zone3MSGREG6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
- unsigned char MSGFun81zone3MSGREG7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
- unsigned char MSGFun81zone3MSGREG8; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
- unsigned char MSGFun81zone3MSGREG9; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
-
- //EC LDN9 funtion 83 zone 0
- unsigned char MSGFun83zone0MSGREG0; ///<Thermal zone
- unsigned char MSGFun83zone0MSGREG1; ///<Thermal zone
- unsigned char MSGFun83zone0MSGREG2; ///<_AC0
- unsigned char MSGFun83zone0MSGREG3; ///<_AC1
- unsigned char MSGFun83zone0MSGREG4; ///<_AC2
- unsigned char MSGFun83zone0MSGREG5; ///<_AC3
- unsigned char MSGFun83zone0MSGREG6; ///<_AC4
- unsigned char MSGFun83zone0MSGREG7; ///<_AC5
- unsigned char MSGFun83zone0MSGREG8; ///<_AC6
- unsigned char MSGFun83zone0MSGREG9; ///<_AC7
- unsigned char MSGFun83zone0MSGREGA; ///<_CRT
- unsigned char MSGFun83zone0MSGREGB; ///<_PSV
-
- //EC LDN9 funtion 83 zone 1
- unsigned char MSGFun83zone1MSGREG0; ///<Thermal zone
- unsigned char MSGFun83zone1MSGREG1; ///<Thermal zone
- unsigned char MSGFun83zone1MSGREG2; ///<_AC0
- unsigned char MSGFun83zone1MSGREG3; ///<_AC1
- unsigned char MSGFun83zone1MSGREG4; ///<_AC2
- unsigned char MSGFun83zone1MSGREG5; ///<_AC3
- unsigned char MSGFun83zone1MSGREG6; ///<_AC4
- unsigned char MSGFun83zone1MSGREG7; ///<_AC5
- unsigned char MSGFun83zone1MSGREG8; ///<_AC6
- unsigned char MSGFun83zone1MSGREG9; ///<_AC7
- unsigned char MSGFun83zone1MSGREGA; ///<_CRT
- unsigned char MSGFun83zone1MSGREGB; ///<_PSV
-
- //EC LDN9 funtion 83 zone 2
- unsigned char MSGFun83zone2MSGREG0; ///<Thermal zone
- unsigned char MSGFun83zone2MSGREG1; ///<Thermal zone
- unsigned char MSGFun83zone2MSGREG2; ///<_AC0
- unsigned char MSGFun83zone2MSGREG3; ///<_AC1
- unsigned char MSGFun83zone2MSGREG4; ///<_AC2
- unsigned char MSGFun83zone2MSGREG5; ///<_AC3
- unsigned char MSGFun83zone2MSGREG6; ///<_AC4
- unsigned char MSGFun83zone2MSGREG7; ///<_AC5
- unsigned char MSGFun83zone2MSGREG8; ///<_AC6
- unsigned char MSGFun83zone2MSGREG9; ///<_AC7
- unsigned char MSGFun83zone2MSGREGA; ///<_CRT
- unsigned char MSGFun83zone2MSGREGB; ///<_PSV
-
- //EC LDN9 funtion 83 zone 3
- unsigned char MSGFun83zone3MSGREG0; ///<Thermal zone
- unsigned char MSGFun83zone3MSGREG1; ///<Thermal zone
- unsigned char MSGFun83zone3MSGREG2; ///<_AC0
- unsigned char MSGFun83zone3MSGREG3; ///<_AC1
- unsigned char MSGFun83zone3MSGREG4; ///<_AC2
- unsigned char MSGFun83zone3MSGREG5; ///<_AC3
- unsigned char MSGFun83zone3MSGREG6; ///<_AC4
- unsigned char MSGFun83zone3MSGREG7; ///<_AC5
- unsigned char MSGFun83zone3MSGREG8; ///<_AC6
- unsigned char MSGFun83zone3MSGREG9; ///<_AC7
- unsigned char MSGFun83zone3MSGREGA; ///<_CRT
- unsigned char MSGFun83zone3MSGREGB; ///<_PSV
-
- //EC LDN9 funtion 85 zone 0
- unsigned char MSGFun85zone0MSGREG0; ///<Thermal zone
- unsigned char MSGFun85zone0MSGREG1; ///<Thermal zone
- unsigned char MSGFun85zone0MSGREG2; ///<AL0 PWM level in percentage (0 - 100%)
- unsigned char MSGFun85zone0MSGREG3; ///<AL1 PWM level in percentage (0 - 100%)
- unsigned char MSGFun85zone0MSGREG4; ///<AL2 PWM level in percentage (0 - 100%)
- unsigned char MSGFun85zone0MSGREG5; ///<AL3 PWM level in percentage (0 - 100%)
- unsigned char MSGFun85zone0MSGREG6; ///<AL4 PWM level in percentage (0 - 100%)
- unsigned char MSGFun85zone0MSGREG7; ///<AL5 PWM level in percentage (0 - 100%)
- unsigned char MSGFun85zone0MSGREG8; ///<AL6 PWM level in percentage (0 - 100%)
- unsigned char MSGFun85zone0MSGREG9; ///<AL7 PWM level in percentage (0 - 100%)
-
- //EC LDN9 funtion 85 zone 1
- unsigned char MSGFun85zone1MSGREG0; ///<Thermal zone
- unsigned char MSGFun85zone1MSGREG1; ///<Thermal zone
- unsigned char MSGFun85zone1MSGREG2; ///<AL0 PWM level in percentage (0 - 100%)
- unsigned char MSGFun85zone1MSGREG3; ///<AL1 PWM level in percentage (0 - 100%)
- unsigned char MSGFun85zone1MSGREG4; ///<AL2 PWM level in percentage (0 - 100%)
- unsigned char MSGFun85zone1MSGREG5; ///<AL3 PWM level in percentage (0 - 100%)
- unsigned char MSGFun85zone1MSGREG6; ///<AL4 PWM level in percentage (0 - 100%)
- unsigned char MSGFun85zone1MSGREG7; ///<AL5 PWM level in percentage (0 - 100%)
- unsigned char MSGFun85zone1MSGREG8; ///<AL6 PWM level in percentage (0 - 100%)
- unsigned char MSGFun85zone1MSGREG9; ///<AL7 PWM level in percentage (0 - 100%)
-
- //EC LDN9 funtion 85 zone 2
- unsigned char MSGFun85zone2MSGREG0; ///<Thermal zone
- unsigned char MSGFun85zone2MSGREG1; ///<Thermal zone
- unsigned char MSGFun85zone2MSGREG2; ///<AL0 PWM level in percentage (0 - 100%)
- unsigned char MSGFun85zone2MSGREG3; ///<AL1 PWM level in percentage (0 - 100%)
- unsigned char MSGFun85zone2MSGREG4; ///<AL2 PWM level in percentage (0 - 100%)
- unsigned char MSGFun85zone2MSGREG5; ///<AL3 PWM level in percentage (0 - 100%)
- unsigned char MSGFun85zone2MSGREG6; ///<AL4 PWM level in percentage (0 - 100%)
- unsigned char MSGFun85zone2MSGREG7; ///<AL5 PWM level in percentage (0 - 100%)
- unsigned char MSGFun85zone2MSGREG8; ///<AL6 PWM level in percentage (0 - 100%)
- unsigned char MSGFun85zone2MSGREG9; ///<AL7 PWM level in percentage (0 - 100%)
-
- //EC LDN9 funtion 85 zone 3
- unsigned char MSGFun85zone3MSGREG0; ///<Thermal zone
- unsigned char MSGFun85zone3MSGREG1; ///<Thermal zone
- unsigned char MSGFun85zone3MSGREG2; ///<AL0 PWM level in percentage (0 - 100%)
- unsigned char MSGFun85zone3MSGREG3; ///<AL1 PWM level in percentage (0 - 100%)
- unsigned char MSGFun85zone3MSGREG4; ///<AL2 PWM level in percentage (0 - 100%)
- unsigned char MSGFun85zone3MSGREG5; ///<AL3 PWM level in percentage (0 - 100%)
- unsigned char MSGFun85zone3MSGREG6; ///<AL4 PWM level in percentage (0 - 100%)
- unsigned char MSGFun85zone3MSGREG7; ///<AL5 PWM level in percentage (0 - 100%)
- unsigned char MSGFun85zone3MSGREG8; ///<AL6 PWM level in percentage (0 - 100%)
- unsigned char MSGFun85zone3MSGREG9; ///<AL7 PWM level in percentage (0 - 100%)
-
- //EC LDN9 funtion 89 TEMPIN channel 0
- unsigned char MSGFun89zone0MSGREG0; ///<Thermal zone
- unsigned char MSGFun89zone0MSGREG1; ///<Thermal zone
- unsigned char MSGFun89zone0MSGREG2; ///<At DWORD bit 0-7
- unsigned char MSGFun89zone0MSGREG3; ///<At DWORD bit 15-8
- unsigned char MSGFun89zone0MSGREG4; ///<At DWORD bit 23-16
- unsigned char MSGFun89zone0MSGREG5; ///<At DWORD bit 31-24
- unsigned char MSGFun89zone0MSGREG6; ///<Ct DWORD bit 0-7
- unsigned char MSGFun89zone0MSGREG7; ///<Ct DWORD bit 15-8
- unsigned char MSGFun89zone0MSGREG8; ///<Ct DWORD bit 23-16
- unsigned char MSGFun89zone0MSGREG9; ///<Ct DWORD bit 31-24
- unsigned char MSGFun89zone0MSGREGA; ///<Mode bit 0-7
-
- //EC LDN9 funtion 89 TEMPIN channel 1
- unsigned char MSGFun89zone1MSGREG0; ///<Thermal zone
- unsigned char MSGFun89zone1MSGREG1; ///<Thermal zone
- unsigned char MSGFun89zone1MSGREG2; ///<At DWORD bit 0-7
- unsigned char MSGFun89zone1MSGREG3; ///<At DWORD bit 15-8
- unsigned char MSGFun89zone1MSGREG4; ///<At DWORD bit 23-16
- unsigned char MSGFun89zone1MSGREG5; ///<At DWORD bit 31-24
- unsigned char MSGFun89zone1MSGREG6; ///<Ct DWORD bit 0-7
- unsigned char MSGFun89zone1MSGREG7; ///<Ct DWORD bit 15-8
- unsigned char MSGFun89zone1MSGREG8; ///<Ct DWORD bit 23-16
- unsigned char MSGFun89zone1MSGREG9; ///<Ct DWORD bit 31-24
- unsigned char MSGFun89zone1MSGREGA; ///<Mode bit 0-7
-
- //EC LDN9 funtion 89 TEMPIN channel 2
- unsigned char MSGFun89zone2MSGREG0; ///<Thermal zone
- unsigned char MSGFun89zone2MSGREG1; ///<Thermal zone
- unsigned char MSGFun89zone2MSGREG2; ///<At DWORD bit 0-7
- unsigned char MSGFun89zone2MSGREG3; ///<At DWORD bit 15-8
- unsigned char MSGFun89zone2MSGREG4; ///<At DWORD bit 23-16
- unsigned char MSGFun89zone2MSGREG5; ///<At DWORD bit 31-24
- unsigned char MSGFun89zone2MSGREG6; ///<Ct DWORD bit 0-7
- unsigned char MSGFun89zone2MSGREG7; ///<Ct DWORD bit 15-8
- unsigned char MSGFun89zone2MSGREG8; ///<Ct DWORD bit 23-16
- unsigned char MSGFun89zone2MSGREG9; ///<Ct DWORD bit 31-24
- unsigned char MSGFun89zone2MSGREGA; ///<Mode bit 0-7
-
- //EC LDN9 funtion 89 TEMPIN channel 3
- unsigned char MSGFun89zone3MSGREG0; ///<Thermal zone
- unsigned char MSGFun89zone3MSGREG1; ///<Thermal zone
- unsigned char MSGFun89zone3MSGREG2; ///<At DWORD bit 0-7
- unsigned char MSGFun89zone3MSGREG3; ///<At DWORD bit 15-8
- unsigned char MSGFun89zone3MSGREG4; ///<At DWORD bit 23-16
- unsigned char MSGFun89zone3MSGREG5; ///<At DWORD bit 31-24
- unsigned char MSGFun89zone3MSGREG6; ///<Ct DWORD bit 0-7
- unsigned char MSGFun89zone3MSGREG7; ///<Ct DWORD bit 15-8
- unsigned char MSGFun89zone3MSGREG8; ///<Ct DWORD bit 23-16
- unsigned char MSGFun89zone3MSGREG9; ///<Ct DWORD bit 31-24
- unsigned char MSGFun89zone3MSGREGA; ///<Mode bit 0-7
-
- // FLAG for Fun83/85/89 support
- unsigned short IMCFUNSupportBitMap; /// Bit0=81FunZone0 support(1=On;0=Off); bit1-3=81FunZone1-Zone3;Bit4-7=83FunZone0-Zone3;Bit8-11=85FunZone0-Zone3;Bit11-15=89FunZone0-Zone3;
-} EC_struct;
-/** SBGPPPORTCONFIG - Southbridge GPP port config structure */
-typedef struct {
- unsigned int PortPresent:1; /**< Port connection
- * @par
- * @li <b>0</b> - Port doesn't have slot. No need to train the link
- * @li <b>1</b> - Port connection defined and needs to be trained
- */
- unsigned int PortDetected:1; /**< Link training status
- * @par
- * @li <b>0</b> - EP not detected
- * @li <b>1</b> - EP detected
- */
- unsigned int PortIsGen2:2; /**< Port link speed configuration
- * @par
- * @li <b>00</b> - Auto
- * @li <b>01</b> - Forced GEN1
- * @li <b>10</b> - Forced GEN2
- * @li <b>11</b> - Reserved
- */
-
- unsigned int PortHotPlug:1; /**< Support hot plug?
- * @par
- * @li <b>0</b> - No support
- * @li <b>1</b> - support
- */
-/** PortMisc - Reserved */
- unsigned int PortMisc:27;
-} SBGPPPORTCONFIG;
-
-/** CODECENTRY - Southbridge HD Audio OEM Codec structure */
-typedef struct _CODECENTRY {
-/** Nid - Reserved ?? */
- unsigned char Nid;
-/** Byte40 - Reserved ?? */
- unsigned int Byte40;
-} CODECENTRY;
-
-/** CODECTBLLIST - Southbridge HD Audio Codec table list */
-typedef struct _CODECTBLLIST {
-/** CodecID - Codec ID */
- unsigned int CodecID;
-/** CodecTablePtr - Codec table pointer */
- CODECENTRY* CodecTablePtr;
-} CODECTBLLIST;
-
-/** Sata Controller structure */
-typedef struct _SATAST {
- unsigned char SataController:1; /**< SataController
- * @par
- * Sata Controller
- * @li <b>0</b> - disable
- * @li <b>1</b> - enable
- */
- unsigned char SataIdeCombMdPriSecOpt:1; /**< SataIdeCombMdPriSecOpt - Reserved */
- unsigned char SataSetMaxGen2:1; /**< SataSetMaxGen2
- * @par
- * Sata Controller Set to Max Gen2 mode
- * @li <b>0</b> - disable
- * @li <b>1</b> - enable
- */
- unsigned char SataIdeCombinedMode:1; /**< SataIdeCombinedMode
- * @par
- * Sata IDE Controller set to Combined Mode
- * @li <b>0</b> - enable
- * @li <b>1</b> - disable
- */
-/** SATARefClkSel - Reserved */
- unsigned char SATARefClkSel:2; // 4:5
-/** SATARefDivSel - Reserved */
- unsigned char SATARefDivSel:2; // 6:7
-} SATAST;
-
-/** _USBST Controller structure
- *
- * Usb Ohci1 Contoller is define at BIT0
- * - 0:disable 1:enable
- * (Bus 0 Dev 18 Func0) *
- * Usb Ehci1 Contoller is define at BIT1
- * - 0:disable 1:enable
- * (Bus 0 Dev 18 Func2) *
- * Usb Ohci2 Contoller is define at BIT2
- * - 0:disable 1:enable
- * (Bus 0 Dev 19 Func0) *
- * Usb Ehci2 Contoller is define at BIT3
- * - 0:disable 1:enable
- * (Bus 0 Dev 19 Func2) *
- * Usb Ohci3 Contoller is define at BIT4
- * - 0:disable 1:enable
- * (Bus 0 Dev 22 Func0) *
- * Usb Ehci3 Contoller is define at BIT5
- * - 0:disable 1:enable
- * (Bus 0 Dev 22 Func2) *
- * Usb Ohci4 Contoller is define at BIT6
- * - 0:disable 1:enable
- * (Bus 0 Dev 20 Func5) *
- */
-typedef struct _USBST {
- unsigned char Ohci1:1; ///< Ohci0 controller - 0:disable, 1:enable
- unsigned char Ehci1:1; ///< Ehci1 controller - 0:disable, 1:enable
- unsigned char Ohci2:1; ///< Ohci2 controller - 0:disable, 1:enable
- unsigned char Ehci2:1; ///< Ehci2 controller - 0:disable, 1:enable
- unsigned char Ohci3:1; ///< Ohci3 controller - 0:disable, 1:enable
- unsigned char Ehci3:1; ///< Ehci3 controller - 0:disable, 1:enable
- unsigned char Ohci4:1; ///< Ohci4 controller - 0:disable, 1:enable
- unsigned char UTemp:1; ///< Reserved
-} USBST;
-
-/**
- * _AZALIAPIN - HID Azalia or GPIO define structure.
- *
- */
-typedef struct _AZALIAPIN {
- unsigned char AzaliaSdin0:2; /**< AzaliaSdin0
- * @par
- * SDIN0 is define at BIT0 & BIT1
- * @li <b>00</b> - GPIO PIN
- * @li <b>10</b> - As a Azalia SDIN pin
- */
- unsigned char AzaliaSdin1:2; /**< AzaliaSdin1
- * @par
- * SDIN0 is define at BIT2 & BIT3
- * @li <b>00</b> - GPIO PIN
- * @li <b>10</b> - As a Azalia SDIN pin
- */
- unsigned char AzaliaSdin2:2; /**< AzaliaSdin2
- * @par
- * SDIN0 is define at BIT4 & BIT5
- * @li <b>00</b> - GPIO PIN
- * @li <b>10</b> - As a Azalia SDIN pin
- */
- unsigned char AzaliaSdin3:2; /**< AzaliaSdin3
- * @par
- * SDIN0 is define at BIT6 & BIT7
- * @li <b>00</b> - GPIO PIN
- * @li <b>10</b> - As a Azalia SDIN pin
- */
-} AZALIAPIN;
-
-/** AMDSBCFG - Southbridge CIMx configuration structure (Main) */
-typedef struct _AMDSBCFG {
-/** StdHeader - Standard header for all AGESA/CIMx services. */
- AMD_CONFIG_PARAMS StdHeader;
-
-/** BuildParameters - The STATIC platform information for CIMx Module. */
- BUILDPARAM BuildParameters;
- //offset 90 bytes (32-121)
- //MsgXchgBiosCimx //offset 4 bytes (122-125)
- // SATA Configuration
-
- union /**< union - Reserved */
- { /**< SATAMODE - Sata Controller structure */
-/** SataModeReg - Reserved */
- unsigned char SataModeReg;
-/** SataMode - Reserved */
- SATAST SataMode;
- } SATAMODE;
-/** S3Resume - Flag of ACPI S3 Resume. */
- unsigned char S3Resume:1; // 8
-/** RebootRequired - Flag of Reboot system is required. */
- unsigned char RebootRequired:1; // 9
-/** SbSpiSpeedSupport - Reserved */
- unsigned char SbSpiSpeedSupport:1; // 10
-/**< SpreadSpectrum
- * @par
- * Spread Spectrum function
- * @li <b>0</b> - disable
- * @li <b>1</b> - enable
- */
- unsigned char SpreadSpectrum:1; // 11
-/** NbSbGen2 - Reserved */
- unsigned char NbSbGen2:1; // 12
- unsigned char GppGen2:1; // 13
- unsigned char GppMemWrImprove:1; // 14
-/** MsgXchgBiosCimxReserved - Reserved */
- unsigned char MsgXchgBiosCimxReserved:1; // 15 (BB USED)
-/**< SataClass - SATA Controller mode [16:18]
- * @par
- * @li <b>000</b> - Native IDE mode
- * @li <b>001</b> - RAID mode
- * @li <b>010</b> - AHCI mode
- * @li <b>011</b> - Legacy IDE mode
- * @li <b>100</b> - IDE->AHCI mode
- * @li <b>101</b> - AHCI mode as 4394 ID (AMD driver)
- * @li <b>110</b> - IDE->AHCI mode as 4394 ID (AMD driver)
- */
- unsigned short SataClass:3; // 16:18
-/**< Sata IDE Controller mode
- * @par
- * @li <b>0</b> - Legacy IDE mode
- * @li <b>1</b> - Native IDE mode
- */
- unsigned short SataIdeMode:1; // 19
-/**< SataEspPort - SATA port is external accessible on a signal only connector (eSATA:)
- * @par
- * @li <b> BIT0 </b> - PORT0 set as ESP port
- * @li <b> BIT1 </b> - PORT1 set as ESP port
- * @li <b> BIT2 </b> - PORT2 set as ESP port
- * @li <b> BIT3 </b> - PORT3 set as ESP port
- * @li <b> BIT4 </b> - PORT4 set as ESP port
- * @li <b> BIT5 </b> - PORT5 set as ESP port
- */
- unsigned short SataEspPort:6; // 20:25
-/** SataPortPower - Reserved */
- unsigned short SataPortPower:6; // 31:26
-
- // SATA Debug Option //offset 4 bytes (126-129)
-
-/**< SataPortMode - Force Each PORT to GEN1/GEN2 mode
- * @par
- * @li <b> 0 </b> Auto for each PORTs
- * @li <b> BIT0 = 1</b> - PORT0 set to GEN1
- * @li <b> BIT1 = 1</b> - PORT0 set to GEN2
- * @li <b> BIT2 = 1</b> - PORT1 set to GEN1
- * @li <b> BIT3 = 1</b> - PORT1 set to GEN2
- * @li <b> BIT4 = 1</b> - PORT2 set to GEN1
- * @li <b> BIT5 = 1</b> - PORT2 set to GEN2
- * @li <b> BIT6 = 1</b> - PORT3 set to GEN1
- * @li <b> BIT7 = 1</b> - PORT3 set to GEN2
- * @li <b> BIT8 = 1</b> - PORT4 set to GEN1
- * @li <b> BIT9 = 1</b> - PORT4 set to GEN2
- * @li <b> BIT10 = 1</b> - PORT5 set to GEN1
- * @li <b> BIT11 = 1</b> - PORT5 set to GEN2
- */
- unsigned int SataPortMode:12; //11:0
-/** SATAClkSelOpt - Reserved */
- unsigned int SATAClkSelOpt:4; // Removed from coding side
-/** SataAggrLinkPmCap - Reserved */
- unsigned int SataAggrLinkPmCap:1; //16, 0:OFF 1:ON
-/** SataPortMultCap - Reserved */
- unsigned int SataPortMultCap:1; //17, 0:OFF 1:ON
-/** SataClkAutoOff - Reserved */
- unsigned int SataClkAutoOff:1; //18, AutoClockOff 0:Disabled, 1:Enabled
-/** SataPscCap - Reserved */
- unsigned int SataPscCap:1; //19, 0:Enable PSC capability, 1:Disable PSC capability
-/** BIOSOSHandoff - Reserved */
- unsigned int BIOSOSHandoff:1; //20
-/** SataFisBasedSwitching - Reserved */
- unsigned int SataFisBasedSwitching:1; //21
-/** SataCccSupport - Reserved */
- unsigned int SataCccSupport:1; //22
-/** SataSscCap - Reserved */
- unsigned int SataSscCap:1; //23, 0:Enable SSC capability, 1:Disable SSC capability
-/** SataMsiCapability - Reserved */
- unsigned int SataMsiCapability:1; //24 0:Hidden 1:Visible. This feature is disabled per RPR, but remains the interface.
-/** SataForceRaid - Reserved */
- unsigned int SataForceRaid:1; //25 0:No function 1:Force RAID
-/** SataDebugDummy - Reserved */
- unsigned int SataDebugDummy:6; //31:26
-//
-// USB Configuration //offset 4 bytes (130-133)
-//
-
-/** USBDeviceConfig - USB Controller Configuration
- *
- * - Usb Ohci1 Contoller is define at BIT0
- * - 0:disable 1:enable
- * (Bus 0 Dev 18 Func0) *
- * - Usb Ehci1 Contoller is define at BIT1
- * - 0:disable 1:enable
- * (Bus 0 Dev 18 Func2) *
- * - Usb Ohci2 Contoller is define at BIT2
- * - 0:disable 1:enable
- * (Bus 0 Dev 19 Func0) *
- * - Usb Ehci2 Contoller is define at BIT3
- * - 0:disable 1:enable
- * (Bus 0 Dev 19 Func2) *
- * - Usb Ohci3 Contoller is define at BIT4
- * - 0:disable 1:enable
- * (Bus 0 Dev 22 Func0) *
- * - Usb Ehci3 Contoller is define at BIT5
- * - 0:disable 1:enable
- * (Bus 0 Dev 22 Func2) *
- * - Usb Ohci4 Contoller is define at BIT6
- * - 0:disable 1:enable
- * (Bus 0 Dev 20 Func5) *
- */
- union /**< union - Reserved */
- { /**< USBMODE - USB Controller structure */
-/** SataModeReg - Reserved */
- unsigned char UsbModeReg;
-/** SataMode - Reserved */
- USBST UsbMode;
- } USBMODE;
-/*!
- */
-
-/**< GecConfig
- * @par
- * InChip Gbit NIC
- * @li <b>1</b> - disable
- * @li <b>0</b> - enable
- */
- unsigned char GecConfig:1; //8
-
-/**< IrConfig
- * @par
- * Ir Controller setting
- * @li <b>00 </b> - disable
- * @li <b>01 </b> - Rx and Tx0
- * @li <b>10 </b> - Rx and Tx1
- * @li <b>11 </b> - Rx and both Tx0,Tx1
- */
- unsigned char IrConfig:2; //9:10
-
-/** GecDummy - Reserved */
- unsigned char GecDummy:5; //15:11
-
- //Azalia Configuration
-
-/**< AzaliaController - Azalia Controller Configuration
- * @par
- * Azalia Controller [0-1]
- * @li <b>0</b> - Auto : Detect Azalia controller automatically.
- * @li <b>1</b> - Diable : Disable Azalia controller.
- * @li <b>2</b> - Enable : Enable Azalia controller.
- */
- unsigned char AzaliaController:2; //17:16
-/**< AzaliaPinCfg - Azalia Controller SDIN pin Configuration
- * @par
- * @li <b>0</b> - disable
- * @li <b>1</b> - enable
- */
- unsigned char AzaliaPinCfg:1; //18
-/**< AzaliaFrontPanel - Azalia Controller Front Panel Configuration
- * @par
- * Support Front Panel configuration
- * @li <b>0</b> - Auto
- * @li <b>1</b> - disable
- * @li <b>2</b> - enable
- */
- unsigned char AzaliaFrontPanel:2; //20:19
-/**< FrontPanelDetected - Force Azalia Controller Front Panel Configuration
- * @par
- * Force Front Panel configuration
- * @li <b>0</b> - Not Detected
- * @li <b>1</b> - Detected
- */
- unsigned char FrontPanelDetected:1; //21
-/**< AzaliaSnoop - Azalia Controller Snoop feature Configuration
- * @par
- * Azalia Controller Snoop feature Configuration
- * @li <b>0</b> - disable
- * @li <b>1</b> - enable
- */
- unsigned char AzaliaSnoop:1; //22
-/** AzaliaDummy - Reserved */
- unsigned char AzaliaDummy:1; //23
-
- union
- {
-/**< AzaliaSdinPin - Azalia Controller SDIN pin Configuration
- *
- * SDIN0 is define at BIT0 & BIT1
- * - 00: GPIO PIN
- * - 01: Reserved
- * - 10: As a Azalia SDIN pin
- *
- * SDIN1 is define at BIT2 & BIT3
- * * Config same as SDIN0
- * SDIN2 is define at BIT4 & BIT5
- * * Config same as SDIN0
- * SDIN3 is define at BIT6 & BIT7
- * * Config same as SDIN0
- */
- unsigned char AzaliaSdinPin;
- AZALIAPIN AzaliaConfig;
- } AZALIACONFIG;
-
-/** AZOEMTBL - Azalia Controller OEM Codec Table Pointer
- *
- */
- union
- {
- PLACEHOLDER PlaceHolder;
- CODECTBLLIST* pAzaliaOemCodecTablePtr; //offset 4 bytes (134-137)
- } AZOEMTBL;
-
-/** AZOEMFPTBL - Azalia Controller Front Panel OEM Table Pointer
- *
- */
- union
- {
- PLACEHOLDER PlaceHolder;
- void* pAzaliaOemFpCodecTablePtr; //offset 4 bytes (138-141)
- } AZOEMFPTBL;
-
- //Miscellaneous Configuration //offset 4 bytes (142-145)
-/** AnyHT200MhzLink - Reserved */
- unsigned int AnyHT200MhzLink:1; //0
-/**< HpetTimer - South Bridge Hpet Timer Configuration
- * @par
- * @li <b>0</b> - disable
- * @li <b>1</b> - enable
- */
- unsigned int HpetTimer:1; //1
-/**< PciClks - PCI Slot Clock Control
- * @par
- * PCI SLOT 0 define at BIT0
- * - 00: disable
- * - 01: enable
- *
- * PCI SLOT 1 define at BIT1
- * * Config same as PCI SLOT0
- * PCI SLOT 2 define at BIT2
- * * Config same as PCI SLOT0
- * PCI SLOT 3 define at BIT3
- * * Config same as PCI SLOT0
- * PCI SLOT 4 define at BIT4
- * * Config same as PCI SLOT0
- */
- unsigned int PciClks:5; //2:6
-/** MiscReserved1 - Reserved */
- unsigned int MiscReserved1:4; //9:7, Reserved
-/** MobilePowerSavings - Debug function Reserved */
- unsigned int MobilePowerSavings:1; //11, 0:Disable, 1:Enable Power saving features especially for Mobile platform
-/** MiscDummy1 - Debug function Reserved */
- unsigned int MiscDummy1:1;
-/** NativePcieSupport - Debug function Reserved */
- unsigned int NativePcieSupport:1; //13, 0:Enable, 1:Disabled
-/** FlashPinConfig - Debug function Reserved */
- unsigned int FlashPinConfig:1; //14, 0:desktop mode 1:mobile mode
-/** UsbPhyPowerDown - Debug function Reserved */
- unsigned int UsbPhyPowerDown:1; //15
-/** PcibClkStopOverride - Debug function Reserved */
- unsigned int PcibClkStopOverride:10; //25:16
-/**< HpetMsiDis - South Bridge HPET MSI Configuration
- * @par
- * @li <b>1</b> - disable
- * @li <b>0</b> - enable
- */
- unsigned int HpetMsiDis:1; //26
-/**< ResetCpuOnSyncFlood - Rest CPU on Sync Flood
- * @par
- * @li <b>0</b> - disable
- * @li <b>1</b> - enable
- */
- unsigned int ResetCpuOnSyncFlood:1; //27
-/**< LdtStpDisable - LdtStp# output disable
- * @par
- * @li <b>0</b> - LdtStp# output enable
- * @li <b>1</b> - LdtStp# output disable
- */
- unsigned int LdtStpDisable:1; //28
-/**< MTC1e - Message Triggered C1e
- * @par
- * @li <b>0</b> - disable
- * @li <b>1</b> - enable
- */
- unsigned int MTC1e:1; //29
-/** MiscDummy - Reserved */
- unsigned int MiscDummy:2; //31:30
- unsigned int SioHwmPortEnable:1; // Enable SuperIO HWM access via LPC
-
- //DebugOptions //offset 4 bytes (146-149)
-/** PcibAutoClkCtrlLow - Debug function Reserved */
- unsigned int PcibAutoClkCtrlLow:16;
-/** PcibAutoClkCtrlHigh - Debug function Reserved */
- unsigned int PcibAutoClkCtrlHigh:16;
-
-/**< OEMPROGTBL - ACPI MMIO register setting table OEM override
- * @par
- * OEM table for customer override ACPI MMIO register in their code.
- */
- union
- {
- PLACEHOLDER OemProgrammingTablePtr; //offset 4 bytes (150-153)
- void *OemProgrammingTablePtr_Ptr;
- } OEMPROGTBL;
-
- //Gpp Configuration //offset 24 bytes total (154-177)
- union {
- unsigned int PORTCFG32;
- SBGPPPORTCONFIG PortCfg;
- } PORTCONFIG[MAX_GPP_PORTS]; //offset 16 bytes
-
- unsigned int GppLinkConfig; // GPP_LINK_CONFIG = PCIE_GPP_Enable[3:0]
- // 0000 - Port ABCD -> 4:0:0:0
- // 0001 - N/A
- // 0010 - Port ABCD -> 2:2:0:0
- // 0011 - Port ABCD -> 2:1:1:0
- // 0100 - Port ABCD -> 1:1:1:1
- //
- unsigned int GppFoundGfxDev:4; //3:0 If port A-D (mapped to bit [3:0]) has GFX EP detected
- unsigned int CoreGen2Enable:1; //4
- unsigned int GppFunctionEnable:1; //5
- unsigned int GppUnhidePorts:1; //6
- unsigned int AlinkPhyPllPowerDown:1; //7
- unsigned int GppConfigDummy1:2; //9:8
- unsigned int GppLaneReversal:1; //10
- unsigned int GppPhyPllPowerDown:1; //11
- unsigned int GppCompliance :1; //12
- unsigned int GppPortAspm:8; //20:13 ASPM state for GPP ports, 14:13 for port0, ..., 20:19 for port3
- // 00 - Disabled
- // 01 - L0s
- // 10 - L1
- // 11 - L0s + L1
- //
- unsigned int GppConfigDummy:11; //31:21
-
- //TempMMIO //offset 4 bytes (178-181)
- unsigned int TempMMIO;
-
- // DebugOption2
- unsigned int GecPhyStatus:1;
- unsigned int GecDebugOptionDummy:7;
- unsigned int SBGecPwr:2;
- unsigned int SBGecDebugBus:1;
- unsigned int DebugOption2Dummy1:1;
- unsigned int DebugOption2Dummy2:1;
- unsigned int SbPcieOrderRule:1;
- unsigned int SbUsbPll:1;
- unsigned int AcDcMsg:1;
- unsigned int TimerTickTrack:1;
- unsigned int ClockInterruptTag:1;
- unsigned int OhciTrafficHanding:1;
- unsigned int EhciTrafficHanding:1;
- unsigned int FusionMsgCMultiCore:1;
- unsigned int FusionMsgCStage:1;
-/**< UsbRxMode - CG PLL multiplier for USB Rx 1.1 mode
- * @par
- * @li <b>0</b> - disable
- * @li <b>1</b> - enable
- */
- unsigned int UsbRxMode:1;
- unsigned int DebugOption2Dummy3:9; //
-
- union
- {
- PLACEHOLDER DynamicGecRomAddressPtr; //offset 4 bytes (182-185)
- void *DynamicGecRomAddress_Ptr;
- } DYNAMICGECROM;
- EC_struct Pecstruct;
-} AMDSBCFG;
-
-/** SMMSERVICESTRUC- Southbridge SMI service structure */
-typedef struct _SMMSERVICESTRUC {
-/** enableRegNum - Reserved */
- unsigned char enableRegNum;
-/** enableBit - Reserved */
- unsigned char enableBit;
-/** statusRegNum - Reserved */
- unsigned char statusRegNum;
-/** statusBit - Reserved */
- unsigned char statusBit;
-/** *debugMessage- Reserved */
- signed char *debugMessage;
-/** serviceRoutine - Reserved */
- SMM_SERVICE_ROUTINE serviceRoutine;
-} SMMSERVICESTRUC;
-
-#ifndef _NB_REG8MASK_
-
-/**
- * - Byte Register R/W structure
- *
- */
- typedef struct _Reg8Mask {
-/** bRegIndex - Reserved */
- unsigned char bRegIndex;
-/** bANDMask - Reserved */
- unsigned char bANDMask;
-/** bORMask - Reserved */
- unsigned char bORMask;
- } REG8MASK;
-#endif
-
-/**
- * - SATA Phy setting structure
- *
- */
-typedef struct _SATAPHYSETTING {
-/** wPhyCoreControl - Reserved */
- unsigned short wPhyCoreControl;
-/** dwPhyFineTune - Reserved */
- unsigned int dwPhyFineTune;
-} SATAPHYSETTING;
-
-/**
- * _ABTblEntry - AB link register table R/W structure
- *
- */
-typedef struct _ABTblEntry {
- /** regType : AB Register Type (ABCFG, AXCFG and so on) */
- unsigned char regType;
- /** regIndex : AB Register Index */
- unsigned int regIndex;
- /** regMask : AB Register Mask */
- unsigned int regMask;
- /** regData : AB Register Data */
- unsigned int regData;
-} ABTBLENTRY;
-
-/**
- * _AcpiRegWrite - ACPI MMIO register R/W structure
- *
- */
-typedef struct _AcpiRegWrite {
- /** MmioBase : Index of Soubridge block (For instence GPIO_BASE:0x01 SMI_BASE:0x02) */
- unsigned char MmioBase;
- /** MmioReg : Register index */
- unsigned char MmioReg;
- /** DataANDMask : AND Register Data */
- unsigned char DataANDMask;
- /** DataOrMask : Or Register Data */
- unsigned char DataOrMask;
-} AcpiRegWrite;
-
-/**
- * PCI_ADDRESS - PCI access structure
- *
- */
-#define PCI_ADDRESS(bus, dev, func, reg) \
-(unsigned int) ( (((unsigned int)bus) << 24) + (((unsigned int)dev) << 19) + (((unsigned int)func) << 16) + ((unsigned int)reg) )
-
-/**
- * CIM_STATUS - CIMx module function return code
- */
-typedef unsigned int CIM_STATUS;
-/**
- * CIM_SUCCESS - Executed without error
- */
-#define CIM_SUCCESS 0x00000000
-/**
- * CIM_ERROR - call error
- */
-#define CIM_ERROR 0x80000000
-/**
- * CIM_UNSUPPORTED - function does not support
- */
-#define CIM_UNSUPPORTED 0x80000001
-
-#pragma pack (pop)
-
-/**
- * CIMX_OPTION_DISABLED - Define disable in module
- */
-#define CIMX_OPTION_DISABLED 0
-/**
- * CIMX_OPTION_ENABLED - Define enable in module
- */
-#define CIMX_OPTION_ENABLED 1
-
-/**
- * SATA_IDE_COMBINE_ENABLE -Define Enable Combined Mode
- */
-#define SATA_IDE_COMBINE_ENABLE 0
-
-/**
- * SATA_IDE_COMBINE_DISABLE -Define Disable Combined Mode
- */
-#define SATA_IDE_COMBINE_DISABLE 1
-
-// mov al, code
-// out 80h, al
-// jmp $
-
-/**
- * DBG_STOP - define a debug point
- */
-#define DBG_STOP __asm _emit 0xEB __asm _emit 0xFE
-
-/**
- * STOP_CODE - define a debug point
- * Warning: AL gets destroyed!
- */
-#define STOP_CODE (code) __asm __emit 0xB0 __asm __emit code __asm __emit 0xE6 \
- __asm __emit 0x80 __asm _emit 0xEB __asm _emit 0xFE
-
-#endif // _AMD_SBTYPE_H_
diff --git a/src/vendorcode/amd/cimx/sb800/SMM.c b/src/vendorcode/amd/cimx/sb800/SMM.c
deleted file mode 100644
index 894ec2a..0000000
--- a/src/vendorcode/amd/cimx/sb800/SMM.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/**
- * @file
- *
- * Southbridge SMM service function
- *
- * Prepare SMM service module for IBV call Southbridge SMI service routine.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: CIMx-SB
- * @e sub-project:
- * @e \$Revision:$ @e \$Date:$
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "SBPLATFORM.h"
-#include "cbtypes.h"
-
-//
-// Declaration of local functions
-//
-
-/**
- * Southbridge SMI service module
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-sbSmmService (
- IN AMDSBCFG* pConfig
- )
-{
- AMDSBCFG* pTmp; //lx-dummy for /W4 build
- pTmp = pConfig;
-}
-
-/**
- * softwareSMIservice - Software SMI service
- *
- * @param[in] VOID Southbridge software SMI service ID.
- *
- */
-VOID
-softwareSMIservice (
- IN VOID
- )
-{
-}
-
-
-
-
-
diff --git a/src/vendorcode/amd/cimx/sb800/Sata.c b/src/vendorcode/amd/cimx/sb800/Sata.c
new file mode 100644
index 0000000..c2f2162
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/Sata.c
@@ -0,0 +1,675 @@
+
+/**
+ * @file
+ *
+ * Config Southbridge SATA controller
+ *
+ * Init SATA features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$ @e \$Date:$
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "SBPLATFORM.h"
+#include "cbtypes.h"
+
+//
+// Declaration of local functions
+//
+VOID sataSetIrqIntResource (IN AMDSBCFG* pConfig);
+VOID sataBar5setting (IN AMDSBCFG* pConfig, IN UINT32 *pBar5);
+VOID shutdownUnconnectedSataPortClock (IN AMDSBCFG* pConfig, IN UINT32 ddBar5);
+VOID sataDriveDetection (IN AMDSBCFG* pConfig, IN UINT32 *pBar5);
+
+/**
+ * sataSetIrqIntResource - Config SATA IRQ/INT# resource
+ *
+ *
+ * - Private function
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+sataSetIrqIntResource (
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT8 dbValue;
+ // IRQ14/IRQ15 come from IDE or SATA
+ dbValue = 0x08;
+ WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue);
+ ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
+ dbValue = dbValue & 0x0F;
+ if (pConfig->SataClass == 3) {
+ dbValue = dbValue | 0x50;
+ } else {
+ if (pConfig->SataIdeMode == 1) {
+ // Both IDE & SATA set to Native mode
+ dbValue = dbValue | 0xF0;
+ }
+ }
+ WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
+}
+
+/**
+ * sataBar5setting - Config SATA BAR5
+ *
+ * - Private function
+ *
+ * @param[in] pConfig - Southbridge configuration structure pointer.
+ * @param[in] *pBar5 - SATA BAR5 buffer.
+ *
+ */
+VOID
+sataBar5setting (
+ IN AMDSBCFG* pConfig,
+ IN UINT32 *pBar5
+ )
+{
+ //Get BAR5 value
+ ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, pBar5);
+ //Assign temporary BAR if is not already assigned
+ if ( (*pBar5 == 0) || (*pBar5 == - 1) ) {
+ //assign temporary BAR5
+ if ( (pConfig->TempMMIO == 0) || (pConfig->TempMMIO == - 1) ) {
+ *pBar5 = 0xFEC01000;
+ } else {
+ *pBar5 = pConfig->TempMMIO;
+ }
+ WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, pBar5);
+ }
+ //Clear Bits 9:0
+ *pBar5 = *pBar5 & 0xFFFFFC00;
+}
+/**
+ * shutdownUnconnectedSataPortClock - Shutdown unconnected Sata port clock
+ *
+ * - Private function
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ * @param[in] ddBar5 Sata BAR5 base address.
+ *
+ */
+VOID
+shutdownUnconnectedSataPortClock (
+ IN AMDSBCFG* pConfig,
+ IN UINT32 ddBar5
+ )
+{
+ UINT8 dbPortNum;
+ UINT8 dbPortSataStatus;
+ UINT8 NumOfPorts;
+ UINT8 cimSataClkAutoOff;
+
+ cimSataClkAutoOff = (UINT8) pConfig->SataClkAutoOff;
+#if SB_CIMx_PARAMETER == 0
+ cimSataClkAutoOff = cimSataClkAutoOffDefault;
+#endif
+ NumOfPorts = 0;
+ if ( cimSataClkAutoOff == TRUE ) {
+ for ( dbPortNum = 0; dbPortNum < 6; dbPortNum++ ) {
+ ReadMEM (ddBar5 + SB_SATA_BAR5_REG128 + (dbPortNum * 0x80), AccWidthUint8, &dbPortSataStatus);
+ // Shutdown the clock for the port and do the necessary port reporting changes.
+ // ?? Error port status should be 1 not 3
+ if ( ((dbPortSataStatus & 0x0F) != 0x03) && (! ((pConfig->SataEspPort) & (1 << dbPortNum))) ) {
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, (1 << dbPortNum));
+ RWMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, ~(1 << dbPortNum), 00);
+ }
+ } //end of for (dbPortNum=0;dbPortNum<6;dbPortNum++)
+ ReadMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, &dbPortSataStatus);
+ //if all ports are in disabled state, report atleast one port
+ if ( (dbPortSataStatus & 0x3F) == 0) {
+ RWMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, (UINT32) ~(0x3F), 01);
+ }
+ ReadMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, &dbPortSataStatus);
+ for (dbPortNum = 0; dbPortNum < 6; dbPortNum ++) {
+ if (dbPortSataStatus & (1 << dbPortNum)) {
+ NumOfPorts++;
+ }
+ }
+ if ( NumOfPorts == 0) {
+ NumOfPorts = 0x01;
+ }
+ RWMEM (ddBar5 + SB_SATA_BAR5_REG00, AccWidthUint8, 0xE0, NumOfPorts - 1);
+ } //end of SataClkAuto Off option
+}
+
+/**
+ * Table for class code of SATA Controller in different modes
+ *
+ *
+ *
+ *
+ */
+const static UINT32 sataIfCodeTable[] =
+{
+ 0x01018F40, //sata class ID of IDE
+ 0x01040040, //sata class ID of RAID
+ 0x01060140, //sata class ID of AHCI
+ 0x01018A40, //sata class ID of Legacy IDE
+ 0x01018F40, //sata class ID of IDE to AHCI mode
+};
+
+/**
+ * Table for device id of SATA Controller in different modes
+ *
+ *
+ *
+ *
+ */
+const static UINT16 sataDeviceIDTable[] =
+{
+ 0x4390, //sata device ID of IDE
+ 0x4392, //sata device ID of RAID
+ 0x4391, //sata class ID of AHCI
+ 0x4390, //sata device ID of Legacy IDE
+ 0x4390, //sata device ID of IDE->AHCI mode
+};
+
+/**
+ * Table for Sata Phy Fine Setting
+ *
+ *
+ *
+ *
+ */
+const static SATAPHYSETTING sataPhyTable[] =
+{
+ {0x3006, 0x0056A607},
+ {0x2006, 0x00061400},
+ {0x1006, 0x00061302},
+
+ {0x3206, 0x0056A607},
+ {0x2206, 0x00061400},
+ {0x1206, 0x00061302},
+
+ {0x3406, 0x0056A607},
+ {0x2406, 0x00061402},
+ {0x1406, 0x00064300},
+
+ {0x3606, 0x0056A607},
+ {0x2606, 0x00061402},
+ {0x1606, 0x00064300},
+
+ {0x3806, 0x0056A700},
+ {0x2806, 0x00061502},
+ {0x1806, 0x00064302},
+
+ {0x3A06, 0x0056A700},
+ {0x2A06, 0x00061502},
+ {0x1A06, 0x00064302}
+};
+
+/**
+ * sataInitBeforePciEnum - Config SATA controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+sataInitBeforePciEnum (
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT32 ddTempVar;
+ UINT32 ddValue;
+ UINT32 *tempptr;
+ UINT16 *pDeviceIdptr;
+ UINT32 dwDeviceId;
+ UINT8 dbValue;
+ UINT8 pValue;
+ UINT16 i;
+ SATAPHYSETTING *pPhyTable;
+
+ ddTempVar = 0;
+ // BIT0 Enable write access to PCI header (reg 08h-0Bh) by setting SATA PCI register 40h
+ // BIT4: Disable fast boot
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0 + BIT2 + BIT4);
+ // BIT0 Enable write access to PCI header (reg 08h-0Bh) by setting IDE PCI register 40h
+ RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0);
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8 | S3_SAVE, 0, pConfig->SataPortPower);
+ dbValue = (UINT8)pConfig->SataClass;
+ if (dbValue == AHCI_MODE_4394) {
+ dbValue = AHCI_MODE;
+ }
+ if (dbValue == IDE_TO_AHCI_MODE_4394) {
+ dbValue = IDE_TO_AHCI_MODE;
+ }
+ // Disable PATA MSI
+ RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG34), AccWidthUint8 | S3_SAVE, 0x00, 0x00);
+ RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG06), AccWidthUint8 | S3_SAVE, 0xEF, 0x00);
+
+ // Get the appropriate class code from the table and write it to PCI register 08h-0Bh
+ // Set the appropriate SATA class based on the input parameters
+ // SATA IDE Controller Class ID & SSID
+ tempptr = (UINT32 *) FIXUP_PTR (&sataIfCodeTable[0]);
+ if ( (pConfig->SataIdeMode == 1) && (pConfig->SataClass != 3) ) {
+ ddValue = tempptr[0];
+ // Write the class code to IDE PCI register 08h-0Bh
+ RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG08), AccWidthUint32 | S3_SAVE, 0, ddValue);
+ }
+ ddValue = tempptr[dbValue];
+ // Write the class code to SATA PCI register 08h-0Bh
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, ddValue);
+ if ( pConfig->SataClass == LEGACY_IDE_MODE ) {
+ //Set PATA controller to native mode
+ RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F);
+ }
+ if (pConfig->BuildParameters.IdeSsid != 0 ) {
+ RWPCI ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.IdeSsid);
+ }
+ // SATA Controller Class ID & SSID
+ pDeviceIdptr = (UINT16 *) FIXUP_PTR (&sataDeviceIDTable[0]);
+ if ( pConfig->BuildParameters.SataIDESsid != 0 ) {
+ ddTempVar = pConfig->BuildParameters.SataIDESsid;
+ }
+ dwDeviceId = pDeviceIdptr[dbValue];
+ if ( pConfig->SataClass == RAID_MODE) {
+ if ( pConfig->BuildParameters.SataRAID5Ssid != 0 ) {
+ ddTempVar = pConfig->BuildParameters.SataRAID5Ssid;
+ }
+ dwDeviceId = V_SB_SATA_RAID5_DID;
+ pValue = SATA_EFUSE_LOCATION;
+ getEfuseStatus (&pValue);
+ if (( pValue & SATA_EFUSE_BIT ) || ( pConfig->SataForceRaid == 1 )) {
+ dwDeviceId = V_SB_SATA_RAID_DID;
+ if ( pConfig->BuildParameters.SataRAIDSsid != 0 ) {
+ ddTempVar = pConfig->BuildParameters.SataRAIDSsid;
+ }
+ }
+ }
+ if ( ((pConfig->SataClass) == AHCI_MODE) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE) ||
+ ((pConfig->SataClass) == AHCI_MODE_4394) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE_4394) ) {
+ if ( pConfig->BuildParameters.SataAHCISsid != 0 ) {
+ ddTempVar = pConfig->BuildParameters.SataAHCISsid;
+ }
+ }
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, dwDeviceId);
+ if ( ddTempVar != 0 ) {
+ RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG2C, AccWidthUint32 | S3_SAVE, 0x00, ddTempVar);
+ }
+ // SATA IRQ Resource
+ sataSetIrqIntResource (pConfig);
+
+ // 8.4 SATA PHY Programming Sequence
+ pPhyTable = (SATAPHYSETTING*)FIXUP_PTR (&sataPhyTable[0]);
+ for (i = 0; i < (sizeof (sataPhyTable) / sizeof (SATAPHYSETTING)); i++) {
+ RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG84, AccWidthUint16 | S3_SAVE, ~(BIT1 + BIT2 + BIT9 + BIT10 + BIT11 + BIT12 + BIT13 + BIT14), pPhyTable->wPhyCoreControl);
+ RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG94, AccWidthUint32 | S3_SAVE, 0x00, pPhyTable->dwPhyFineTune);
+ ++pPhyTable;
+ }
+
+// CallBackToOEM (SATA_PHY_PROGRAMMING, NULL, pConfig);
+
+ RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0);
+ // Disable write access to PCI header
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0);
+}
+
+/**
+ * sataInitAfterPciEnum - Config SATA controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+sataInitAfterPciEnum (
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT32 ddAndMask;
+ UINT32 ddOrMask;
+ UINT32 ddBar5;
+ UINT8 dbVar;
+ UINT8 dbPortNum;
+ UINT8 dbEfuse;
+ UINT8 dbPortMode;
+ UINT16 SataPortMode;
+ UINT8 cimSataAggrLinkPmCap;
+ UINT8 cimSataPortMultCap;
+ UINT8 cimSataPscCap;
+ UINT8 cimSataSscCap;
+ UINT8 cimSataFisBasedSwitching;
+ UINT8 cimSataCccSupport;
+
+ cimSataAggrLinkPmCap = (UINT8) pConfig->SataAggrLinkPmCap;
+ cimSataPortMultCap = (UINT8) pConfig->SataPortMultCap;
+ cimSataPscCap = (UINT8) pConfig->SataPscCap;
+ cimSataSscCap = (UINT8) pConfig->SataSscCap;
+ cimSataFisBasedSwitching = (UINT8) pConfig->SataFisBasedSwitching;
+ cimSataCccSupport = (UINT8) pConfig->SataCccSupport;
+
+#if SB_CIMx_PARAMETER == 0
+ cimSataAggrLinkPmCap = cimSataAggrLinkPmCapDefault;
+ cimSataPortMultCap = cimSataPortMultCapDefault;
+ cimSataPscCap = cimSataPscCapDefault;
+ cimSataSscCap = cimSataSscCapDefault;
+ cimSataFisBasedSwitching = cimSataFisBasedSwitchingDefault;
+ cimSataCccSupport = cimSataCccSupportDefault;
+#endif
+
+ ddAndMask = 0;
+ ddOrMask = 0;
+ ddBar5 = 0;
+ if ( pConfig->SATAMODE.SataMode.SataController == 0 ) {
+ return; //return if SATA controller is disabled.
+ }
+
+ //Enable write access to pci header, pm capabilities
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
+ //Disable AHCI Prefetch function
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8 | S3_SAVE, 0x7F, BIT7);
+
+ sataBar5setting (pConfig, &ddBar5);
+
+ ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8,0xFF, 0x03); //memory and io access enable
+ dbEfuse = SATA_FIS_BASE_EFUSE_LOC;
+ getEfuseStatus (&dbEfuse);
+
+ if ( !cimSataPortMultCap ) {
+ ddAndMask |= BIT12;
+ }
+ if ( cimSataAggrLinkPmCap ) {
+ ddOrMask |= BIT11;
+ } else {
+ ddAndMask |= BIT11;
+ }
+ if ( cimSataPscCap ) {
+ ddOrMask |= BIT1;
+ }
+ if ( cimSataSscCap ) {
+ ddOrMask |= BIT26;
+ }
+ if ( cimSataFisBasedSwitching ) {
+ if (dbEfuse & BIT1) {
+ ddAndMask |= BIT10;
+ } else {
+ ddOrMask |= BIT10;
+ }
+ } else {
+ ddAndMask |= BIT10;
+ }
+ // RPR 8.10 Disabling CCC (Command Completion Coalescing) support.
+ if ( cimSataCccSupport ) {
+ ddOrMask |= BIT19;
+ } else {
+ ddAndMask |= BIT19;
+ }
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint32 | S3_SAVE, ~ddAndMask, ddOrMask);
+
+
+ // SATA ESP port setting
+ // These config bits are set for SATA driver to identify which ports are external SATA ports and need to
+ // support hotplug. If a port is set as an external SATA port and need to support hotplug, then driver will
+ // not enable power management (HIPM & DIPM) for these ports.
+ if ( pConfig->SataEspPort != 0 ) {
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(pConfig->SataEspPort), 0);
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT12 + BIT13 + BIT14 + BIT15 + BIT16 + BIT17 + BIT5 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), (pConfig->SataEspPort << 12));
+ // RPR 8.7 External SATA Port Indication Registers
+ // If any of the ports was programmed as an external port, HCAP.SXS should also be set
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint32 | S3_SAVE, ~(BIT20), BIT20);
+ } else {
+ // RPR 8.7 External SATA Port Indication Registers
+ // If any of the ports was programmed as an external port, HCAP.SXS should also be set (Clear for no ESP port)
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT5 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), 0x00);
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint32 | S3_SAVE, ~(BIT20), 0x00);
+ }
+ if ( cimSataFisBasedSwitching ) {
+ if (dbEfuse & BIT1) {
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT22 + BIT23 + BIT24 + BIT25 + BIT26 + BIT27), 0x00);
+ } else {
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT22 + BIT23 + BIT24 + BIT25 + BIT26 + BIT27), (BIT22 + BIT23 + BIT24 + BIT25 + BIT26 + BIT27));
+ }
+ } else {
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT22 + BIT23 + BIT24 + BIT25 + BIT26 + BIT27), 0x00);
+ }
+
+ // Disabled SATA MSI and D3 Power State capability
+ // RPR 8.13 SATA MSI and D3 Power State Capability
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG34), AccWidthUint8 | S3_SAVE, 0, 0x70);
+
+ if (((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE)) {
+ // RAID or AHCI
+ if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == SATA_IDE_COMBINE_DISABLE) {
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REG00), AccWidthUint8 | S3_SAVE, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT0);
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0xC0, 0x3F);
+ // RPR 8.10 Disabling CCC (Command Completion Coalescing) support.
+ // 8 messages
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2 + BIT1);
+ } else {
+ // RPR 8.10 Disabling CCC (Command Completion Coalescing) support.
+ if ( pConfig->SataCccSupport ) {
+ // 8 messages
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2 + BIT1);
+ } else {
+ // 4 messages
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2);
+ }
+ }
+ }
+
+ if ( pConfig->BIOSOSHandoff == 1 ) {
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REG24), AccWidthUint8 | S3_SAVE, ~BIT0, BIT0);
+ } else {
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REG24), AccWidthUint8 | S3_SAVE, ~BIT0, 0x00);
+ }
+
+ SataPortMode = (UINT16)pConfig->SataPortMode;
+ dbPortNum = 0;
+ while ( dbPortNum < 6 ) {
+ dbPortMode = (UINT8) (SataPortMode & 3);
+ if ( (dbPortMode == BIT0) || (dbPortMode == BIT1) ) {
+ if ( dbPortMode == BIT0 ) {
+ // set GEN 1
+ RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0x0F, 0x10);
+ }
+ if ( dbPortMode == BIT1 ) {
+ // set GEN2 (default is GEN3)
+ RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0x0F, 0x20);
+ }
+ RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFF, 0x01);
+ }
+ SataPortMode >>= 2;
+ dbPortNum ++;
+ }
+ SbStall (1000);
+ SataPortMode = (UINT16)pConfig->SataPortMode;
+ dbPortNum = 0;
+ while ( dbPortNum < 6 ) {
+ dbPortMode = (UINT8) (SataPortMode & 3);
+ if ( (dbPortMode == BIT0) || (dbPortMode == BIT1) ) {
+ RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00);
+ }
+ dbPortNum ++;
+ SataPortMode >>= 2;
+ }
+ WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
+ //Disable write access to pci header, pm capabilities
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0);
+}
+
+
+/**
+ * sataInitMidPost - Config SATA controller in Middle POST.
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+sataInitMidPost (
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT32 ddBar5;
+ sataBar5setting (pConfig, &ddBar5);
+ //If this is not S3 resume and also if SATA set to one of IDE mode, then implement drive detection workaround.
+ if ( ! (pConfig->S3Resume) && ( ((pConfig->SataClass) != AHCI_MODE) && ((pConfig->SataClass) != RAID_MODE) ) ) {
+ sataDriveDetection (pConfig, &ddBar5);
+ }
+}
+
+/**
+ * sataDriveDetection - Sata drive detection
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ * @param[in] *pBar5 Sata BAR5 base address.
+ *
+ */
+VOID
+sataDriveDetection (
+ IN AMDSBCFG* pConfig,
+ IN UINT32 *pBar5
+ )
+{
+ UINT32 ddVar0;
+ UINT8 dbPortNum;
+ UINT8 dbVar0;
+ UINT16 dwIoBase;
+ UINT32 dwVar0;
+ if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) ) {
+ for ( dbPortNum = 0; dbPortNum < 4; dbPortNum++ ) {
+ ReadMEM (*pBar5 + SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint32, &ddVar0);
+ if ( ( ddVar0 & 0x0F ) == 0x03 ) {
+ if ( dbPortNum & BIT0 ) {
+ //this port belongs to secondary channel
+ ReadPCI (((UINT32) (SATA_BUS_DEV_FUN << 16) + SB_SATA_REG18), AccWidthUint16, &dwIoBase);
+ } else {
+ //this port belongs to primary channel
+ ReadPCI (((UINT32) (SATA_BUS_DEV_FUN << 16) + SB_SATA_REG10), AccWidthUint16, &dwIoBase);
+ }
+ //if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them
+ if ( pConfig->SataClass == LEGACY_IDE_MODE ) {
+ dwIoBase = ( (0x170) | ((UINT16) ( (~((UINT8) (dbPortNum & BIT0) << 7)) & 0x80 )) );
+ }
+ if ( dbPortNum & BIT1 ) {
+ //this port is slave
+ dbVar0 = 0xB0;
+ } else {
+ //this port is master
+ dbVar0 = 0xA0;
+ }
+ dwIoBase &= 0xFFF8;
+ WriteIO (dwIoBase + 6, AccWidthUint8, &dbVar0);
+ //Wait in loop for 30s for the drive to become ready
+ for ( dwVar0 = 0; dwVar0 < 300000; dwVar0++ ) {
+ ReadIO (dwIoBase + 7, AccWidthUint8, &dbVar0);
+ if ( (dbVar0 & 0x88) == 0 ) {
+ break;
+ }
+ SbStall (100);
+ }
+ } //end of if ( ( ddVar0 & 0x0F ) == 0x03)
+ } //for (dbPortNum = 0; dbPortNum < 4; dbPortNum++)
+ } //if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE))
+}
+
+/**
+ * sataInitLatePost - Prepare SATA controller to boot to OS.
+ *
+ * - Set class ID to AHCI (if set to AHCI * Mode)
+ * - Enable AHCI interrupt
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+sataInitLatePost (
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT32 ddBar5;
+ UINT8 dbVar;
+ UINT8 dbPortNum;
+
+ //Return immediately is sata controller is not enabled
+ if ( pConfig->SATAMODE.SataMode.SataController == 0 ) {
+ return;
+ }
+ //Enable write access to pci header, pm capabilities
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0);
+
+// if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == SATA_IDE_COMBINE_DISABLE) {
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 1), AccWidthUint8 | S3_SAVE, ~BIT7, BIT7);
+// }
+ sataBar5setting (pConfig, &ddBar5);
+
+ ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
+ //Enable memory and io access
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, 0xFF, 0x03);
+
+ shutdownUnconnectedSataPortClock (pConfig, ddBar5);
+
+ if (( pConfig->SataClass == IDE_TO_AHCI_MODE) || ( pConfig->SataClass == IDE_TO_AHCI_MODE_4394 )) {
+ //program the AHCI class code
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, 0x01060100);
+ //Set interrupt enable bit
+ RWMEM ((ddBar5 + 0x04), AccWidthUint8, (UINT32)~0, BIT1);
+ //program the correct device id for AHCI mode
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, 0x4391);
+ }
+
+ if (( pConfig->SataClass == AHCI_MODE_4394 ) || ( pConfig->SataClass == IDE_TO_AHCI_MODE_4394 )) {
+ //program the correct device id for AHCI 4394 mode
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, 0x4394);
+ }
+
+ //Clear error status ?? only 4 port
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REG130), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REG1B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REG230), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REG2B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REG330), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REG3B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
+ //Restore memory and io access bits
+ WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar );
+ //Disable write access to pci header and pm capabilities
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0);
+ for ( dbPortNum = 0; dbPortNum < 6; dbPortNum++ ) {
+ RWMEM ((ddBar5 + 0x110 + (dbPortNum * 0x80)), AccWidthUint32, 0xFFFFFFFF, 0x00);
+ }
+}
+
+
diff --git a/src/vendorcode/amd/cimx/sb800/SbCmn.c b/src/vendorcode/amd/cimx/sb800/SbCmn.c
new file mode 100644
index 0000000..8e9f0e2
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/SbCmn.c
@@ -0,0 +1,1066 @@
+/**
+ * @file
+ *
+ * Southbridge Initial routine
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$ @e \$Date:$
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "SBPLATFORM.h"
+#include "cbtypes.h"
+//
+// Declaration of local functions
+//
+
+VOID abcfgTbl (IN ABTBLENTRY* pABTbl);
+
+/**
+ * sbUsbPhySetting - USB Phy Calibration Adjustment
+ *
+ *
+ * @param[in] Value Controller PCI config address (bus# + device# + function#)
+ *
+ */
+VOID sbUsbPhySetting (IN UINT32 Value);
+
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page LegacyInterfaceCalls Legacy Interface Calls
+ * <TD>@subpage SB_POWERON_INIT_Page "SB_POWERON_INIT"</TD><TD></TD>
+ * <TD>@subpage SB_BEFORE_PCI_INIT_Page "SB_BEFORE_PCI_INIT"</TD><TD></TD>
+ * <TD>@subpage SB_AFTER_PCI_INIT_Page "SB_AFTER_PCI_INIT"</TD><TD></TD>
+ * <TD>@subpage SB_LATE_POST_INIT_Page "SB_LATE_POST_INIT"</TD><TD></TD>
+ * <TD>@subpage SB_BEFORE_PCI_RESTORE_INIT_Page "SB_BEFORE_PCI_RESTORE_INIT"</TD><TD></TD>
+ * <TD>@subpage SB_AFTER_PCI_RESTORE_INIT_Page "SB_AFTER_PCI_RESTORE_INIT"</TD><TD></TD>
+ * <TD>@subpage SB_SMM_SERVICE_Page "SB_SMM_SERVICE"</TD><TD></TD>
+ * <TD>@subpage SB_SMM_ACPION_Page "SB_SMM_ACPION"</TD><TD></TD>
+ *
+ * @page LegacyInterfaceCallOuts Legacy Interface CallOuts
+ * <TD>@subpage CB_SBGPP_RESET_ASSERT_Page CB_SBGPP_RESET_ASSERT
+ * <TD>@subpage CB_SBGPP_RESET_DEASSERT_Page CB_SBGPP_RESET_DEASSERT
+ *
+*/
+
+/**
+ * sbEarlyPostByteInitTable - PCI device registers initial during early POST.
+ *
+ */
+const static REG8MASK sbEarlyPostByteInitTable[] =
+{
+ // SMBUS Device (Bus 0, Dev 20, Func 0)
+ {0x00, SMBUS_BUS_DEV_FUN, 0},
+ {SB_CFG_REG10, 0X00, (SBCIMx_Version & 0xFF)}, //Program the version information
+ {SB_CFG_REG11, 0X00, (SBCIMx_Version >> 8)},
+ {0xFF, 0xFF, 0xFF},
+
+ // IDE Device (Bus 0, Dev 20, Func 1)
+ {0x00, IDE_BUS_DEV_FUN, 0},
+ {SB_IDE_REG62 + 1, ~BIT0, BIT5}, // Enabling IDE Explicit Pre-Fetch IDE PCI Config 0x62[8]=0
+ // Allow MSI capability of IDE controller to be visible. IDE PCI Config 0x62[13]=1
+ {0xFF, 0xFF, 0xFF},
+
+ // Azalia Device (Bus 0, Dev 20, Func 2)
+ {0x00, AZALIA_BUS_DEV_FUN, 0},
+ {SB_AZ_REG4C, ~BIT0, BIT0},
+ {0xFF, 0xFF, 0xFF},
+
+ // LPC Device (Bus 0, Dev 20, Func 3)
+ {0x00, LPC_BUS_DEV_FUN, 0},
+ {SB_LPC_REG40, ~BIT2, BIT2}, // RPR 1.1 Enabling LPC DMA Function 0x40[2]=1b 0x78[0]=0b
+ {SB_LPC_REG78, ~BIT0, 00}, // RPR 1.1 Enabling LPC DMA Function 0x40[2]=1b 0x78[0]=0b
+ {SB_LPC_REG78, ~BIT1, 00}, // Disables MSI capability
+ {SB_LPC_REGBB, ~BIT0, BIT0 + BIT3 + BIT4 + BIT5}, // Enabled SPI Prefetch from HOST.
+ {0xFF, 0xFF, 0xFF},
+
+ // PCIB Bridge (Bus 0, Dev 20, Func 4)
+ {0x00, PCIB_BUS_DEV_FUN, 0},
+ {SB_PCIB_REG40, 0xFF, BIT5}, // RPR PCI-bridge Subtractive Decode
+ {SB_PCIB_REG4B, 0xFF, BIT7}, //
+ {SB_PCIB_REG66, 0xFF, BIT4}, // RPR Enabling One-Prefetch-Channel Mode, PCIB_PCI_config 0x64 [20]
+ {SB_PCIB_REG65, 0xFF, BIT7}, // RPR proper operation of CLKRUN#.
+ {SB_PCIB_REG0D, 0x00, 0x40}, // Setting Latency Timers to 0x40, Enables the PCIB to retain ownership
+ {SB_PCIB_REG1B, 0x00, 0x40}, // of the bus on the Primary side and on the Secondary side when GNT# is deasserted.
+ {SB_PCIB_REG66 + 1, 0xFF, BIT1}, // RPR Enable PCI bus GNT3#..
+ {0xFF, 0xFF, 0xFF},
+
+ // SATA Device (Bus 0, Dev 17, Func 0)
+ {0x00, SATA_BUS_DEV_FUN, 0},
+ {SB_SATA_REG44, 0xff, BIT0}, // Enables the SATA watchdog timer register prior to the SATA BIOS post
+ {SB_SATA_REG44 + 2, 0, 0x20}, // RPR 8.12 SATA PCI Watchdog timer setting
+ // [SB01923] Set timer out to 0x20 to fix IDE to SATA Bridge dropping drive issue.
+ {0xFF, 0xFF, 0xFF},
+};
+
+
+/**
+ * sbPmioEPostInitTable - Southbridge ACPI MMIO initial during POST.
+ *
+ */
+const static AcpiRegWrite sbPmioEPostInitTable[] =
+{
+ // HPET workaround
+ {PMIO_BASE >> 8, SB_PMIOA_REG54 + 3, 0xFC, BIT0 + BIT1},
+ {PMIO_BASE >> 8, SB_PMIOA_REG54 + 2, 0x7F, BIT7},
+ {PMIO_BASE >> 8, SB_PMIOA_REG54 + 2, 0x7F, 0x00},
+ // End of HPET workaround
+ // Enable SB800 A12 ACPI bits at PMIO 0xC0 [30,10:3]
+ // ClrAllStsInThermalEvent 3 Set to 1 to allow ASF remote power down/power cycle, Thermal event, Fan slow event to clear all the Gevent status and enabled bits. The bit should be set to 1 all the time.
+ // UsbGoodClkDlyEn 4 Set to 1 to delay de-assertion of Usb clk by 6 Osc clk. The bit should be set to 1 all the time.
+ // ForceNBCPUPwr 5 Set to 1 to force CPU pwrGood to be toggled along with NB pwrGood.
+ // MergeUsbPerReq 6 Set to 1 to merge usb perdical traffic into usb request as one of break event.
+ // IMCWatchDogRstEn 7 Set to 1 to allow IMC watchdog timer to reset entire acpi block. The bit should be set to 1 when IMC is enabled.
+ // GeventStsFixEn 8 1: Gevent status is not reset by its enable bit. 0: Gevent status is reset by its enable bit.
+ // PmeTimerFixEn 9 Set to 1 to reset Pme Timer when going to sleep state.
+ // UserRst2EcEn 10 Set to 1 to route user reset event to Ec. The bit should be set to 1 when IMC is enabled.
+ // Smbus0ClkSEn 30 Set to 1 to enable SMBus0 controller clock stretch support.
+ {PMIO_BASE >> 8, SB_PMIOA_REGC4, ~(BIT2 + BIT4), BIT2 + BIT4},
+ {PMIO_BASE >> 8, SB_PMIOA_REGC0, 0, 0xF9},
+ // PM_reg xC1 [3] = 1b, per RPR 2.7 CPU PwrGood Setting
+ {PMIO_BASE >> 8, SB_PMIOA_REGC0 + 1, 0x04, 0x0B},
+ // RtcSts 19-17 RTC_STS set only in Sleep State.
+ // GppPme 20 Set to 1 to enable PME request from SB GPP.
+ // Pcireset 22 Set to 1 to allow SW to reset PCIe.
+ {PMIO_BASE >> 8, SB_PMIOA_REGC2, 0x20, 0x58},
+ {PMIO_BASE >> 8, SB_PMIOA_REGC2 + 1, 0, 0x40},
+
+ //Item Id: SB02037: RTC_STS should be set in S state
+ //set PMIO 0xC0 [19:16] Set to 1110 to allow RTC_STS to be set only in non_G0 state.
+ //{PMIO_BASE >> 8, SB_PMIOA_REGC2, (UINT8)~(0x0F), 0x0E},
+
+ //Item Id: SB02034
+ //Title: SB GPP NIC auto wake at second time sleep
+ //set PMIO 0xC4 bit 2 to 1 then set PMIO 0xC0 bit 20 to 1 to enable fix for SB02034
+
+ {PMIO_BASE >> 8, SB_PMIOA_REGC2, ~(BIT4), BIT4},
+
+ //{GPIO_BASE >> 8, SB_GPIO_REG62 , 0x00, 0x4E},
+ {PMIO_BASE >> 8, SB_PMIOA_REG74, 0x00, BIT0 + BIT1 + BIT2 + BIT4},
+ {PMIO_BASE >> 8, SB_PMIOA_REGDE + 1, ~(BIT0 + BIT1), BIT0 + BIT1},
+ {PMIO_BASE >> 8, SB_PMIOA_REGDE, ~BIT4, BIT4},
+ {PMIO_BASE >> 8, SB_PMIOA_REGBA, ~BIT3, BIT3},
+ {PMIO_BASE >> 8, SB_PMIOA_REGBA + 1, ~BIT6, BIT6},
+ {PMIO_BASE >> 8, SB_PMIOA_REGBC, ~BIT1, BIT1},
+ {PMIO_BASE >> 8, SB_PMIOA_REGED, ~(BIT0 + BIT1), 0},
+ //RPR Hiding Flash Controller PM_IO 0xDC[7] = 0x0 & PM_IO 0xDC [1:0]=0x01
+ {PMIO_BASE >> 8, SB_PMIOA_REGDC, 0x7C, BIT0},
+ // RPR Turning off FC clock
+ {MISC_BASE >> 8, SB_MISC_REG40 + 1, ~(BIT3 + BIT2), BIT3 + BIT2},
+ {MISC_BASE >> 8, SB_MISC_REG40 + 2, ~BIT0, BIT0},
+ {SMI_BASE >> 8, SB_SMI_Gevent0, 0, 29},
+ {SMI_BASE >> 8, SB_SMI_Gevent1, 0, 1},
+ {SMI_BASE >> 8, SB_SMI_Gevent2, 0, 29},
+ {SMI_BASE >> 8, SB_SMI_Gevent3, 0, 29},
+ {SMI_BASE >> 8, SB_SMI_Gevent4, 0, 4},
+ {SMI_BASE >> 8, SB_SMI_Gevent5, 0, 5},
+ {SMI_BASE >> 8, SB_SMI_Gevent6, 0, 6},
+ {SMI_BASE >> 8, SB_SMI_Gevent7, 0, 29},
+
+ {SMI_BASE >> 8, SB_SMI_Gevent9, 0, 29},
+ {SMI_BASE >> 8, SB_SMI_Gevent10, 0, 29},
+ {SMI_BASE >> 8, SB_SMI_Gevent11, 0, 29},
+ {SMI_BASE >> 8, SB_SMI_Gevent12, 0, 29},
+ {SMI_BASE >> 8, SB_SMI_Gevent13, 0, 29},
+ {SMI_BASE >> 8, SB_SMI_Gevent14, 0, 29},
+ {SMI_BASE >> 8, SB_SMI_Gevent15, 0, 29},
+ {SMI_BASE >> 8, SB_SMI_Gevent16, 0, 29},
+ {SMI_BASE >> 8, SB_SMI_Gevent17, 0, 29},
+ {SMI_BASE >> 8, SB_SMI_Gevent18, 0, 29},
+ {SMI_BASE >> 8, SB_SMI_Gevent19, 0, 29},
+ {SMI_BASE >> 8, SB_SMI_Gevent20, 0, 29},
+ {SMI_BASE >> 8, SB_SMI_Gevent21, 0, 29},
+ {SMI_BASE >> 8, SB_SMI_Gevent22, 0, 29},
+ {SMI_BASE >> 8, SB_SMI_Gevent23, 0, 29},
+//
+ {SMI_BASE >> 8, SB_SMI_Usbwakup0, 0, 11},
+ {SMI_BASE >> 8, SB_SMI_Usbwakup1, 0, 11},
+ {SMI_BASE >> 8, SB_SMI_Usbwakup2, 0, 11},
+ {SMI_BASE >> 8, SB_SMI_Usbwakup3, 0, 11},
+ {SMI_BASE >> 8, SB_SMI_IMCGevent0, 0, 12},
+ {SMI_BASE >> 8, SB_SMI_IMCGevent1, 0, 29},
+ {SMI_BASE >> 8, SB_SMI_FanThGevent, 0, 13},
+ {SMI_BASE >> 8, SB_SMI_SBGppPme0, 0, 15},
+ {SMI_BASE >> 8, SB_SMI_SBGppPme1, 0, 16},
+ {SMI_BASE >> 8, SB_SMI_SBGppPme2, 0, 17},
+ {SMI_BASE >> 8, SB_SMI_SBGppPme3, 0, 18},
+ {SMI_BASE >> 8, SB_SMI_SBGppHp0, 0, 29},
+ {SMI_BASE >> 8, SB_SMI_SBGppHp1, 0, 29},
+ {SMI_BASE >> 8, SB_SMI_SBGppHp2, 0, 29},
+ {SMI_BASE >> 8, SB_SMI_SBGppHp3, 0, 29},
+ {SMI_BASE >> 8, SB_SMI_GecPme, 0, 19},
+ {SMI_BASE >> 8, SB_SMI_CIRPme, 0, 23},
+ {SMI_BASE >> 8, SB_SMI_Gevent8, 0, 26},
+ {SMI_BASE >> 8, SB_SMI_AzaliaPme, 0, 27},
+ {SMI_BASE >> 8, SB_SMI_SataGevent0, 0, 30},
+ {SMI_BASE >> 8, SB_SMI_SataGevent1, 0, 31},
+
+ {SMI_BASE >> 8, SB_SMI_WakePinGevent, 0, 29},
+ {SMI_BASE >> 8, SB_SMI_ASFMasterIntr, 0, 29},
+ {SMI_BASE >> 8, SB_SMI_ASFSlaveIntr, 0, 29},
+
+// {SMI_BASE >> 8, SB_SMI_REG04, ~BIT4, BIT4},
+// {SMI_BASE >> 8, SB_SMI_REG04 + 1, ~BIT0, BIT0},
+// {SMI_BASE >> 8, SB_SMI_REG04 + 2, ~BIT3, BIT3},
+ {SMI_BASE >> 8, SB_SMI_REG08, ~BIT4, 0},
+ {SMI_BASE >> 8, SB_SMI_REG08+3, ~BIT2, 0},
+// {SMI_BASE >> 8, SB_SMI_REG0C, ~BIT4, BIT4},
+ {SMI_BASE >> 8, SB_SMI_REG0C + 2, ~BIT3, BIT3},
+ {SMI_BASE >> 8, SB_SMI_TWARN, 0, 9},
+ {SMI_BASE >> 8, SB_SMI_TMI, 0, 29},
+ {0xFF, 0xFF, 0xFF, 0xFF},
+};
+
+/**
+ * abTblEntry800 - AB-Link Configuration Table for SB800
+ *
+ */
+const static ABTBLENTRY abTblEntry800[] =
+{
+ // RPR Enable downstream posted transactions to pass non-posted transactions.
+ {ABCFG, SB_ABCFG_REG10090, BIT8 + BIT16, BIT8 + BIT16},
+
+ // RPR Enable SB800 to issue memory read/write requests in the upstream direction.
+ {AXCFG, SB_AB_REG04, BIT2, BIT2},
+
+ // RPR Enabling IDE/PCIB Prefetch for Performance Enhancement
+ // PCIB prefetch ABCFG 0x10060 [20] = 1 ABCFG 0x10064 [20] = 1
+ {ABCFG, SB_ABCFG_REG10060, BIT20, BIT20}, // PCIB prefetch enable
+ {ABCFG, SB_ABCFG_REG10064, BIT20, BIT20}, // PCIB prefetch enable
+
+ // RPR Controls the USB OHCI controller prefetch used for enhancing performance of ISO out devices.
+ // RPR Setting B-Link Prefetch Mode (ABCFG 0x80 [18:17] = 11)
+ {ABCFG, SB_ABCFG_REG80, BIT0 + BIT17 + BIT18, BIT0 + BIT17 + BIT18},
+
+ // RPR Enabled SMI ordering enhancement. ABCFG 0x90[21]
+ // RPR USB Delay A-Link Express L1 State. ABCFG 0x90[17]
+ {ABCFG, SB_ABCFG_REG90, BIT21 + BIT17, BIT21 + BIT17},
+
+ // RPR Disable the credit variable in the downstream arbitration equation
+ // RPR Register bit to qualify additional address bits into downstream register programming. (A12 BIT1 default is set)
+ {ABCFG, SB_ABCFG_REG9C, BIT0, BIT0},
+
+ // RPR Enabling Detection of Upstream Interrupts ABCFG 0x94 [20] = 1
+ // ABCFG 0x94 [19:0] = cpu interrupt delivery address [39:20]
+ {ABCFG, SB_ABCFG_REG94, BIT20, BIT20 + 0x00FEE},
+
+ // RPR Programming cycle delay for AB and BIF clock gating
+ // RPR Enable the AB and BIF clock-gating logic.
+ // RPR Enable the A-Link int_arbiter enhancement to allow the A-Link bandwidth to be used more efficiently
+ // RPR Enable the requester ID for upstream traffic. [16]: SB/NB link [17]: GPP
+ {ABCFG, SB_ABCFG_REG10054, 0x00FFFFFF, 0x010407FF},
+ {ABCFG, SB_ABCFG_REG98, 0xFFFF00FF, 0x00034700},
+ {ABCFG, SB_ABCFG_REG54, 0x00FF0000, 0x00040000},
+ // RPR Non-Posted Memory Write Support
+ {AX_INDXC, SB_AX_INDXC_REG10, BIT9, BIT9},
+ {ABCFG, 0, 0, (UINT8) 0xFF}, // This dummy entry is to clear ab index
+ { (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF},
+};
+
+/**
+ * SbPcieOrderRule - AB-Link Configuration Table for ablink Post Pass Np Downstream/Upstream Feature
+ *
+ */
+const static ABTBLENTRY SbPcieOrderRule[] =
+{
+// abPostPassNpDownStreamTbl
+ {ABCFG, SB_ABCFG_REG10060, BIT31, BIT31},
+ {ABCFG, SB_ABCFG_REG1009C, BIT4 + BIT5, BIT4 + BIT5},
+ {ABCFG, SB_ABCFG_REG9C, BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7, BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7},
+ {ABCFG, SB_ABCFG_REG90, BIT21 + BIT22 + BIT23, BIT21 + BIT22 + BIT23},
+ {ABCFG, SB_ABCFG_REGF0, BIT6 + BIT5, BIT6 + BIT5},
+ {AXINDC, SB_AX_INDXC_REG02, BIT9, BIT9},
+ {ABCFG, SB_ABCFG_REG10090, BIT9 + BIT10 + BIT11 + BIT12, BIT9 + BIT10 + BIT11 + BIT12},
+// abPostPassNpUpStreamTbl
+ {ABCFG, SB_ABCFG_REG58, BIT10, BIT10},
+ {ABCFG, SB_ABCFG_REGF0, BIT3 + BIT4, BIT3 + BIT4},
+ {ABCFG, SB_ABCFG_REG54, BIT1, BIT1},
+ { (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF},
+};
+
+/**
+ * commonInitEarlyBoot - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB.
+ *
+ * This settings should be done during S3 resume also
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+commonInitEarlyBoot (
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT32 abValue;
+ UINT16 dwTempVar;
+ CPUID_DATA CpuId;
+ UINT8 cimNativepciesupport;
+ UINT8 cimIrConfig;
+ UINT8 Data;
+
+ cimNativepciesupport = (UINT8) pConfig->NativePcieSupport;
+ cimIrConfig = (UINT8) pConfig->IrConfig;
+#if SB_CIMx_PARAMETER == 0
+ cimNativepciesupport = cimNativepciesupportDefault;
+ cimIrConfig = cimIrConfigDefault;
+#endif
+
+ //IR init Logical device 0x05
+ if ( cimIrConfig ) {
+ // Enable EC_PortActive
+ RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4), AccWidthUint16 | S3_SAVE, 0xFFFE, BIT0);
+ EnterEcConfig ();
+ RWEC8 (0x07, 0x00, 0x05); //Select logical device 05, IR controller
+ RWEC8 (0x60, 0x00, 0x05); //Set Base Address to 550h
+ RWEC8 (0x61, 0x00, 0x50);
+ RWEC8 (0x70, 0xF0, 0x05); //Set IRQ to 05h
+ RWEC8 (0x30, 0x00, 0x01); //Enable logical device 5, IR controller
+ Data = 0xAB;
+ WriteIO (0x550, AccWidthUint8, &Data);
+ ReadIO (0x551, AccWidthUint8, &Data);
+ Data = ((Data & 0xFC ) | cimIrConfig);
+ WriteIO (0x551, AccWidthUint8, &Data);
+ ExitEcConfig ();
+ Data = 0xA0; // EC APIC index
+ WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &Data);
+ Data = 0x05; // IRQ5
+ WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &Data);
+ } else {
+ EnterEcConfig ();
+ RWEC8 (0x07, 0x00, 0x05); //Select logical device 05, IR controller
+ RWEC8 (0x30, 0x00, 0x00); //Disable logical device 5, IR controller
+ ExitEcConfig ();
+ }
+
+
+ CpuidRead (0x01, &CpuId);
+
+ //
+ // SB CFG programming
+ //
+ //Make BAR registers of smbus visible.
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0);
+ //Early post initialization of pci config space
+ programPciByteTable ((REG8MASK*) FIXUP_PTR (&sbEarlyPostByteInitTable[0]), sizeof (sbEarlyPostByteInitTable) / sizeof (REG8MASK) );
+ if ( pConfig->BuildParameters.SmbusSsid != 0 ) {
+ RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.SmbusSsid);
+ }
+ //Make BAR registers of smbus invisible.
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, BIT6);
+
+ //
+ // LPC CFG programming
+ //
+ // SSID for LPC Controller
+ if (pConfig->BuildParameters.LpcSsid != 0 ) {
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.LpcSsid);
+ }
+ // LPC MSI
+ if ( pConfig->BuildParameters.LpcMsi) {
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG78, AccWidthUint32 | S3_SAVE, ~BIT1, BIT1);
+ }
+
+ //
+ // PCIB CFG programming
+ //
+ //Disable or Enable PCI Clks based on input
+ RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG42, AccWidthUint8 | S3_SAVE, ~(BIT5 + BIT4 + BIT3 + BIT2), ((pConfig->PciClks) & 0x0F) << 2 );
+ RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG4A, AccWidthUint8 | S3_SAVE, ~(BIT1 + BIT0), (pConfig->PciClks) >> 4 );
+ // PCIB MSI
+ if ( pConfig->BuildParameters.PcibMsi) {
+ RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG40, AccWidthUint8 | S3_SAVE, ~BIT3, BIT3);
+ }
+
+ //
+ // AB CFG programming
+ //
+ // Read Arbiter address, Arbiter address is in PMIO 6Ch
+ ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6C, AccWidthUint16, &dwTempVar);
+ RWIO (dwTempVar, AccWidthUint8, 0, 0); // Write 0 to enable the arbiter
+
+ abLinkInitBeforePciEnum (pConfig); // Set ABCFG registers
+ // AB MSI
+ if ( pConfig->BuildParameters.AbMsi) {
+ abValue = readAlink (SB_ABCFG_REG94 | (UINT32) (ABCFG << 29));
+ abValue = abValue | BIT20;
+ writeAlink (SB_ABCFG_REG94 | (UINT32) (ABCFG << 29), abValue);
+ }
+
+
+ //
+ // SB Specific Function programming
+ //
+
+ // PCIE Native setting
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGBA + 1, AccWidthUint8, ~BIT14, 0);
+ if ( pConfig->NativePcieSupport == 1) {
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG74 + 3, AccWidthUint8, ~(BIT3 + BIT1 + BIT0), BIT2 + BIT0);
+ } else {
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG74 + 3, AccWidthUint8, ~(BIT3 + BIT1 + BIT0), BIT2);
+ }
+
+#ifdef ACPI_SLEEP_TRAP
+ // Set SLP_TYPE as SMI event
+ RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB0, AccWidthUint8, ~(BIT2 + BIT3), BIT2);
+ // Disabled SLP function for S1/S3/S4/S5
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGBE, AccWidthUint8, ~BIT5, 0x00);
+ // Set S state transition disabled (BIT0) force ACPI to send SMI message when writing to SLP_TYP Acpi register. (BIT1)
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG08 + 3, AccWidthUint8, ~(BIT0 + BIT1), BIT1);
+ // Enabled Global Smi ( BIT7 clear as 0 to enable )
+ RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REG98 + 3 , AccWidthUint8, ~BIT7, 0x00);
+#endif
+ if ( pConfig->SbUsbPll == 0) {
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF3, AccWidthUint8, 0, 0x20);
+ }
+ // Set Stutter timer settings
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 1, AccWidthUint8, ~(BIT3 + BIT4), BIT3 + BIT4);
+ // Set LDTSTP# duration to 10us for HydraD CPU, or when HT link is 200MHz
+ if ((pConfig->AnyHT200MhzLink) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100080) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100090) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x1000A0)) {
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8, 0, 0x0A);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 3, AccWidthUint8 | S3_SAVE, 0xFE, 0x28);
+ } else {
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8, 0, 0x01);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 3, AccWidthUint8 | S3_SAVE, 0xFE, 0x20);
+ }
+
+ //PM_Reg 0x7A[15] (CountHaltMsgEn) should be set when C1e option is enabled
+ //PM_Reg 0x7A[3:0] (NumOfCpu) should be set to 1h when C1e option is enabled
+ //PM_Reg 0x80[13] has to set to 1 to enable Message C scheme.
+ if (pConfig->MTC1e) {
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7A, AccWidthUint16 | S3_SAVE, 0x7FF0, BIT15 + 1);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 1, AccWidthUint8 | S3_SAVE, ~BIT5, BIT5);
+ }
+
+ programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr));
+}
+
+/**
+ * abSpecialSetBeforePciEnum - Special setting ABCFG registers before PCI emulation.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+abSpecialSetBeforePciEnum (
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT32 abValue;
+ abValue = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29));
+ abValue &= 0xf0;
+ if ( pConfig->SbPcieOrderRule && abValue ) {
+ abValue = readAlink (SB_RCINDXC_REG02 | (UINT32) (RCINDXC << 29));
+ abValue = abValue | BIT9;
+ writeAlink (SB_RCINDXC_REG02 | (UINT32) (RCINDXC << 29), abValue);
+ }
+}
+
+VOID
+usbDesertPll (
+ IN AMDSBCFG* pConfig
+ )
+{
+ if ( pConfig->SbUsbPll == 0) {
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF3, AccWidthUint8, 0, 0x00);
+ }
+}
+
+/**
+ * commonInitEarlyPost - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB.
+ *
+ * This settings might not program during S3 resume
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+commonInitEarlyPost (
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT8 dbPortStatus;
+ UINT8 cimSpreadSpectrum;
+ UINT32 cimSpreadSpectrumType;
+ AMDSBCFG* pTmp;
+ pTmp = pConfig;
+
+ cimSpreadSpectrum = pConfig->SpreadSpectrum;
+ cimSpreadSpectrumType = pConfig->BuildParameters.SpreadSpectrumType;
+#if SB_CIMx_PARAMETER == 0
+ cimSpreadSpectrum = cimSpreadSpectrumDefault;
+ cimSpreadSpectrumType = cimSpreadSpectrumTypeDefault;
+#endif
+ programSbAcpiMmioTbl ((AcpiRegWrite*) FIXUP_PTR (&sbPmioEPostInitTable[0]));
+
+ // CallBackToOEM (PULL_UP_PULL_DOWN_SETTINGS, NULL, pConfig);
+
+ if ( cimSpreadSpectrum ) {
+ // Misc_Reg_40[25]=1 -> allow to change spread profile
+ // Misc_Reg19=83 -> new spread profile
+ // Misc_Reg[12:10]=9975be
+ // Misc_Reg0B=91
+ // Misc_Reg09=21
+ // Misc_Misc_Reg_08[0]=1 -> enable spread
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x43, AccWidthUint8, ~BIT1, BIT1);
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x19, AccWidthUint8, 0, 0x83);
+ getChipSysMode (&dbPortStatus);
+ if ( ((dbPortStatus & ChipSysIntClkGen) != ChipSysIntClkGen) ) {
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1A, AccWidthUint8, ~(BIT5 + BIT6 + BIT7), 0x80);
+ }
+
+ if ( cimSpreadSpectrumType == 0 ) {
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x12, AccWidthUint8, 0, 0x99);
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x11, AccWidthUint8, 0, 0x75);
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccWidthUint8, 0, 0xBE);
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x0B, AccWidthUint8, 0, 0x91);
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x09, AccWidthUint8, 0, 0x21);
+ } else { // Spread profile for Ontario CPU related platform
+ // This spread profile setting is for Ontario HDMI & DVI output from DP with -0.425%
+ // Misc_Reg[12:10]=828FA8
+ // Misc_Reg0B=11
+ // Misc_Reg09=21
+ // Misc_Reg10[25:24]=01b
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x12, AccWidthUint8, 0, 0x82);
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x11, AccWidthUint8, 0, 0x8F);
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccWidthUint8, 0, 0xA8);
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x0B, AccWidthUint8, 0, 0x11);
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x09, AccWidthUint8, 0, 0x21);
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x13, AccWidthUint8, 0xFC, 0x1);
+ }
+
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG08, AccWidthUint8, 0xFE, 0x01);
+ } else {
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG08, AccWidthUint8, 0xFE, 0x00);
+ }
+
+ // RPR PLL 100Mhz Reference Clock Buffer setting for internal clock generator mode
+ getChipSysMode (&dbPortStatus);
+ if ( ((dbPortStatus & ChipSysIntClkGen) == ChipSysIntClkGen) ) {
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG04 + 1, AccWidthUint8, ~BIT5, BIT5);
+ }
+
+ // Set ASF SMBUS master function enabled here (temporary)
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG28, AccWidthUint16 | S3_SAVE, ~(BIT0 + BIT2), BIT0 + BIT2);
+
+ programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr));
+#ifndef NO_EC_SUPPORT
+ // Software IMC enable
+ if (((pConfig->BuildParameters.ImcEnableOverWrite == 1) && ((dbPortStatus & ChipSysEcEnable) == 0)) || ((pConfig->BuildParameters.ImcEnableOverWrite == 2) && ((dbPortStatus & ChipSysEcEnable) == ChipSysEcEnable))) {
+ if (validateImcFirmware (pConfig)) {
+ softwareToggleImcStrapping (pConfig);
+ } else {
+ CallBackToOEM (IMC_FIRMWARE_FAIL, 0, pConfig);
+ }
+ }
+#endif
+
+}
+/**
+ * abLinkInitBeforePciEnum - Set ABCFG registers before PCI emulation.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+abLinkInitBeforePciEnum (
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT32 cimResetCpuOnSyncFlood;
+ ABTBLENTRY *pAbTblPtr;
+ AMDSBCFG* Temp;
+
+ cimResetCpuOnSyncFlood = pConfig->ResetCpuOnSyncFlood;
+#if SB_CIMx_PARAMETER == 0
+ cimResetCpuOnSyncFlood = cimResetCpuOnSyncFloodDefault;
+#endif
+ Temp = pConfig;
+ if ( pConfig->SbPcieOrderRule ) {
+ pAbTblPtr = (ABTBLENTRY *) FIXUP_PTR (&SbPcieOrderRule[0]);
+ abcfgTbl (pAbTblPtr);
+ }
+ pAbTblPtr = (ABTBLENTRY *) FIXUP_PTR (&abTblEntry800[0]);
+ abcfgTbl (pAbTblPtr);
+ if ( cimResetCpuOnSyncFlood ) {
+ rwAlink (SB_ABCFG_REG10050 | (UINT32) (ABCFG << 29), ~BIT2, BIT2);
+ }
+}
+
+/**
+ * abcfgTbl - Program ABCFG by input table.
+ *
+ *
+ * @param[in] pABTbl ABCFG config table.
+ *
+ */
+VOID
+abcfgTbl (
+ IN ABTBLENTRY* pABTbl
+ )
+{
+ UINT32 ddValue;
+
+ while ( (pABTbl->regType) != 0xFF ) {
+ if ( pABTbl->regType > AXINDC ) {
+ ddValue = pABTbl->regIndex | (pABTbl->regType << 29);
+ writeAlink (ddValue, ((readAlink (ddValue)) & (0xFFFFFFFF^ (pABTbl->regMask))) | pABTbl->regData);
+ } else {
+ ddValue = 0x30 | (pABTbl->regType << 29);
+ writeAlink (ddValue, pABTbl->regIndex);
+ ddValue = 0x34 | (pABTbl->regType << 29);
+ writeAlink (ddValue, ((readAlink (ddValue)) & (0xFFFFFFFF^ (pABTbl->regMask))) | pABTbl->regData);
+ }
+ ++pABTbl;
+ }
+
+ //Clear ALink Access Index
+ ddValue = 0;
+ WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &ddValue);
+}
+
+/**
+ * commonInitLateBoot - Prepare Southbridge register setting to boot to OS.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+commonInitLateBoot (
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT8 dbValue;
+ UINT32 ddVar;
+ // We need to do the following setting in late post also because some bios core pci enumeration changes these values
+ // programmed during early post.
+ // RPR 4.5 Master Latency Timer
+
+ dbValue = 0x40;
+ WritePCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG0D, AccWidthUint8, &dbValue);
+ WritePCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG1B, AccWidthUint8, &dbValue);
+
+ //SB P2P AutoClock control settings.
+ ddVar = (pConfig->PcibAutoClkCtrlHigh << 16) | (pConfig->PcibAutoClkCtrlLow);
+ WritePCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG4C, AccWidthUint32, &ddVar);
+ ddVar = (pConfig->PcibClkStopOverride);
+ RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG50, AccWidthUint16, 0x3F, (UINT16) (ddVar << 6));
+
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBB, AccWidthUint8, 0xBF | S3_SAVE, BIT3 + BIT4 + BIT5);
+
+ // USB Phy Calibration Adjustment
+ ddVar = (USB1_EHCI_BUS_DEV_FUN << 16);
+ sbUsbPhySetting (ddVar);
+ ddVar = (USB2_EHCI_BUS_DEV_FUN << 16);
+ sbUsbPhySetting (ddVar);
+ ddVar = (USB3_EHCI_BUS_DEV_FUN << 16);
+ sbUsbPhySetting (ddVar);
+
+ c3PopupSetting (pConfig);
+ FusionRelatedSetting (pConfig);
+}
+
+/**
+ * sbUsbPhySetting - USB Phy Calibration Adjustment
+ *
+ *
+ * @param[in] Value Controller PCI config address (bus# + device# + function#)
+ *
+ */
+VOID
+sbUsbPhySetting (
+ IN UINT32 Value
+ )
+{
+ UINT32 ddBarAddress;
+ UINT32 ddPhyStatus03;
+ UINT32 ddPhyStatus4;
+ UINT8 dbRevId;
+ //Get BAR address
+ ReadPCI ((UINT32) Value + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress);
+ if ( (ddBarAddress != - 1) && (ddBarAddress != 0) ) {
+ ReadMEM ( ddBarAddress + SB_EHCI_BAR_REGA8, AccWidthUint32, &ddPhyStatus03);
+ ReadMEM ( ddBarAddress + SB_EHCI_BAR_REGAC, AccWidthUint32, &ddPhyStatus4);
+ ddPhyStatus03 &= 0x07070707;
+ ddPhyStatus4 &= 0x00000007;
+ if ( (ddPhyStatus03 != 0x00) | (ddPhyStatus4 != 0x00) ) {
+ // RPR 7.7 USB 2.0 Ports Driving Strength step 1
+ //Make BAR registers of smbus visible.
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0);
+ ReadPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG08, AccWidthUint8, &dbRevId);
+ //Make BAR registers of smbus invisible.
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, BIT6);
+ if (dbRevId == 0x41) { // A12
+ RWMEM (ddBarAddress + SB_EHCI_BAR_REGC0, AccWidthUint32, 0xFFFF00FF, 0x1500);
+ RWMEM (ddBarAddress + SB_EHCI_BAR_REGC4, AccWidthUint32, 0xFFFFF0FF, 0);
+ } else if (dbRevId == 0x42) { // A13
+ RWMEM (ddBarAddress + SB_EHCI_BAR_REGC0, AccWidthUint32, 0xFFFF00FF, 0x0F00);
+ RWMEM (ddBarAddress + SB_EHCI_BAR_REGC4, AccWidthUint32, 0xFFFFF0FF, 0x0100);
+ }
+ }
+ }
+}
+
+/**
+ * hpetInit - Program Southbridge HPET function
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ * @param[in] pStaticOptions Platform build configuration table.
+ *
+ */
+VOID
+hpetInit (
+ IN AMDSBCFG* pConfig,
+ IN BUILDPARAM *pStaticOptions
+ )
+{
+ DESCRIPTION_HEADER* pHpetTable;
+ UINT8 cimHpetTimer;
+ UINT8 cimHpetMsiDis;
+
+ cimHpetTimer = (UINT8) pConfig->HpetTimer;
+ cimHpetMsiDis = (UINT8) pConfig->HpetMsiDis;
+#if SB_CIMx_PARAMETER == 0
+ cimHpetTimer = cimHpetTimerDefault;
+ cimHpetMsiDis = cimHpetMsiDisDefault;
+#endif
+ pHpetTable = NULL;
+ if ( cimHpetTimer == TRUE ) {
+ //Program the HPET BAR address
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, pStaticOptions->HpetBase);
+ //Enabling decoding of HPET MMIO
+ //Enable HPET MSI support
+ //Enable High Precision Event Timer (also called Multimedia Timer) interrupt
+ if ( cimHpetMsiDis == FALSE ) {
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, BIT0 + BIT1 + BIT2 + BIT3 + BIT4);
+ } else {
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, BIT0 + BIT1);
+ }
+
+ } else {
+ if ( ! (pConfig->S3Resume) ) {
+ pHpetTable = (DESCRIPTION_HEADER*) ACPI_LocateTable (Int32FromChar('H', 'P', 'E', 'T'));
+ }
+ if ( pHpetTable != NULL ) {
+ pHpetTable->Signature = Int32FromChar('T', 'E', 'P', 'H');
+ }
+ }
+}
+
+/**
+ * c3PopupSetting - Program Southbridge C state function
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+c3PopupSetting (
+ IN AMDSBCFG* pConfig
+ )
+{
+ AMDSBCFG* Temp;
+ UINT8 dbValue;
+ Temp = pConfig;
+ //RPR C-State and VID/FID Change
+ dbValue = getNumberOfCpuCores ();
+ if (dbValue > 1) {
+ //PM 0x80[2]=1, For system with dual core CPU, set this bit to 1 to automatically clear BM_STS when the C3 state is being initiated.
+ //PM 0x80[1]=1, For system with dual core CPU, set this bit to 1 and BM_STS will cause C3 to wakeup regardless of BM_RLD
+ //PM 0x7E[6]=1, Enable pop-up for C3. For internal bus mastering or BmReq# from the NB, the SB will de-assert
+ //LDTSTP# (pop-up) to allow DMA traffic, then assert LDTSTP# again after some idle time.
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint8 | S3_SAVE, ~(BIT1 + BIT2), (BIT1 + BIT2));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7E, AccWidthUint8 | S3_SAVE, ~BIT6, BIT6);
+ }
+ //SB800 needs to changed for RD790 support
+ //PM 0x80 [8] = 0 for system with RS780
+ //Note: RS690 north bridge has AllowLdtStop built for both display and PCIE traffic to wake up the HT link.
+ //BmReq# needs to be ignored otherwise may cause LDTSTP# not to toggle.
+ //PM_IO 0x80[3]=1, Ignore BM_STS_SET message from NB
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint16 | S3_SAVE, ~(BIT9 + BIT8 + BIT7 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), 0x21F);
+ //LdtStartTime = 10h for minimum LDTSTP# de-assertion duration of 16us in StutterMode. This is to guarantee that
+ //the HT link has been safely reconnected before it can be disconnected again. If C3 pop-up is enabled, the 16us also
+ //serves as the minimum idle time before LDTSTP# can be asserted again. This allows DMA to finish before the HT
+ //link is disconnected.
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94 + 2, AccWidthUint8, 0, 0x10);
+
+ //This setting provides 16us delay before the assertion of LDTSTOP# when C3 is entered. The
+ //delay will allow USB DMA to go on in a continuous manner
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG98 + 1, AccWidthUint8, 0, 0x10);
+ // Not in the RPR so far, it's hand writing from ASIC
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7C, AccWidthUint8 | S3_SAVE, 0, 0x85);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7C + 1, AccWidthUint8 | S3_SAVE, 0, 0x01);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7E + 1, AccWidthUint8 | S3_SAVE, ~(BIT7 + BIT5), BIT7 + BIT5);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88 + 1, AccWidthUint8 | S3_SAVE, ~BIT4, BIT4);
+ // RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8, 0, 0x10);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG98 + 3, AccWidthUint8, 0, 0x10);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGB4 + 1, AccWidthUint8, 0, 0x0B);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8 | S3_SAVE, 0xFF, BIT4);
+ if (pConfig->LdtStpDisable) {
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8 | S3_SAVE, ~BIT5, 0);
+ }
+}
+
+/**
+ * FusionRelatedSetting - Program Fusion C related function
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+FusionRelatedSetting (
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT8 cimAcDcMsg;
+ UINT8 cimTimerTickTrack;
+ UINT8 cimClockInterruptTag;
+ UINT8 cimOhciTrafficHanding;
+ UINT8 cimEhciTrafficHanding;
+ UINT8 cimFusionMsgCMultiCore;
+ UINT8 cimFusionMsgCStage;
+ UINT32 ddValue;
+
+ cimAcDcMsg = (UINT8) pConfig->AcDcMsg;
+ cimTimerTickTrack = (UINT8) pConfig->TimerTickTrack;
+ cimClockInterruptTag = (UINT8) pConfig->ClockInterruptTag;
+ cimOhciTrafficHanding = (UINT8) pConfig->OhciTrafficHanding;
+ cimEhciTrafficHanding = (UINT8) pConfig->EhciTrafficHanding;
+ cimFusionMsgCMultiCore = (UINT8) pConfig->FusionMsgCMultiCore;
+ cimFusionMsgCStage = (UINT8) pConfig->FusionMsgCStage;
+#if SB_CIMx_PARAMETER == 0
+ cimAcDcMsg = cimAcDcMsgDefault;
+ cimTimerTickTrack = cimTimerTickTrackDefault;
+ cimClockInterruptTag = cimClockInterruptTagDefault;
+ cimOhciTrafficHanding = cimOhciTrafficHandingDefault;
+ cimEhciTrafficHanding = cimEhciTrafficHandingDefault;
+ cimFusionMsgCMultiCore = cimFusionMsgCMultiCoreDefault;
+ cimFusionMsgCStage = cimFusionMsgCStageDefault;
+#endif
+ ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGA0, AccWidthUint32 | S3_SAVE, &ddValue);
+ ddValue = ddValue & 0xC07F00A0;
+ if ( cimAcDcMsg ) {
+ ddValue = ddValue | BIT0;
+ }
+ if ( cimTimerTickTrack ) {
+ ddValue = ddValue | BIT1;
+ }
+ if ( cimClockInterruptTag ) {
+ ddValue = ddValue | BIT10;
+ }
+ if ( cimOhciTrafficHanding ) {
+ ddValue = ddValue | BIT13;
+ }
+ if ( cimEhciTrafficHanding ) {
+ ddValue = ddValue | BIT15;
+ }
+ if ( cimFusionMsgCMultiCore ) {
+ ddValue = ddValue | BIT23;
+ }
+ if ( cimFusionMsgCStage ) {
+ ddValue = (ddValue | (BIT6 + BIT4 + BIT3 + BIT2));
+ }
+ WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGA0, AccWidthUint32 | S3_SAVE, &ddValue);
+}
+#ifndef NO_EC_SUPPORT
+/**
+ * validateImcFirmware - Validate IMC Firmware.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ * @retval TRUE Pass
+ * @retval FALSE Failed
+ */
+BOOLEAN
+validateImcFirmware (
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT32 ImcSig;
+ UINT32 ImcSigAddr;
+ UINT32 ImcAddr;
+ UINT32 CurAddr;
+ UINT32 ImcBinSig0;
+ UINT32 ImcBinSig1;
+ UINT16 ImcBinSig2;
+ UINT8 dbIMCChecksume;
+ UINT8 dbIMC;
+ ImcAddr = 0;
+
+ // Software IMC enable
+ ImcSigAddr = 0x80000; // start from 512k to 64M
+ ImcSig = 0x0; //
+ while ( ( ImcSig != 0x55aa55aa ) && ( ImcSigAddr <= 0x4000000 ) ) {
+ CurAddr = 0xffffffff - ImcSigAddr + 0x20001;
+ ReadMEM (CurAddr, AccWidthUint32, &ImcSig);
+ ReadMEM ((CurAddr + 4), AccWidthUint32, &ImcAddr);
+ ImcSigAddr <<= 1;
+ }
+
+ dbIMCChecksume = 0xff;
+ if ( ImcSig == 0x55aa55aa ) {
+ // "_AMD_IMC_C" at offset 0x2000 of the binary
+ ReadMEM ((ImcAddr + 0x2000), AccWidthUint32, &ImcBinSig0);
+ ReadMEM ((ImcAddr + 0x2004), AccWidthUint32, &ImcBinSig1);
+ ReadMEM ((ImcAddr + 0x2008), AccWidthUint16, &ImcBinSig2);
+ if ((ImcBinSig0 == 0x444D415F) && (ImcBinSig1 == 0x434D495F) && (ImcBinSig2 == 0x435F) ) {
+ dbIMCChecksume = 0;
+ for ( CurAddr = ImcAddr; CurAddr < ImcAddr + 0x10000; CurAddr++ ) {
+ ReadMEM (CurAddr, AccWidthUint8, &dbIMC);
+ dbIMCChecksume = dbIMCChecksume + dbIMC;
+ }
+ }
+ }
+ if ( dbIMCChecksume ) {
+ return FALSE;
+ } else {
+ return TRUE;
+ }
+}
+
+/**
+ * softwareToggleImcStrapping - Software Toggle IMC Firmware Strapping.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+softwareToggleImcStrapping (
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT8 dbValue;
+ UINT8 dbPortStatus;
+ UINT32 abValue;
+ UINT32 abValue1;
+
+ getChipSysMode (&dbPortStatus);
+
+ ReadPMIO (SB_PMIOA_REGBF, AccWidthUint8, &dbValue);
+ //if ( (dbValue & (BIT6 + BIT7)) != 0xC0 ) { // PwrGoodOut =1, PwrGoodEnB=1
+ //The strapStatus register is not mapped into StrapOveride not in the same bit position. The following is difference.
+
+ //StrapStatus StrapOverride
+ // bit4 bit17
+ // bit6 bit12
+ // bit12 bit15
+ // bit15 bit16
+ // bit16 bit18
+ ReadMEM ((ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80), AccWidthUint32, &abValue);
+ abValue1 = abValue;
+ if (abValue & BIT4) {
+ abValue1 = (abValue1 & ~BIT4) | BIT17;
+ }
+ if (abValue & BIT6) {
+ abValue1 = (abValue1 & ~BIT6) | BIT12;
+ }
+ if (abValue & BIT12) {
+ abValue1 = (abValue1 & ~BIT12) | BIT15;
+ }
+ if (abValue & BIT15) {
+ abValue1 = (abValue1 & ~BIT15) | BIT16;
+ }
+ if (abValue & BIT16) {
+ abValue1 = (abValue1 & ~BIT16) | BIT18;
+ }
+ abValue1 |= BIT31; // Overwrite enable
+ if ((dbPortStatus & ChipSysEcEnable) == 0) {
+ abValue1 |= BIT2; // bit2- EcEnableStrap
+ } else {
+ abValue1 &= ~BIT2; // bit2=0 EcEnableStrap
+ }
+ WriteMEM ((ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG84), AccWidthUint32, &abValue1);
+ dbValue |= BIT6; // PwrGoodOut =1
+ dbValue &= ~BIT7; // PwrGoodEnB =0
+ WritePMIO (SB_PMIOA_REGBF, AccWidthUint8, &dbValue);
+
+ dbValue = 06;
+ WriteIO (0xcf9, AccWidthUint8, &dbValue);
+ SbStall (0xffffffff);
+}
+#endif
+
+#ifndef NO_HWM_SUPPORT
+/**
+ * validateImcFirmware - Validate IMC Firmware.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+hwmInit (
+ IN AMDSBCFG* pConfig
+ )
+{
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xB2, AccWidthUint8 | S3_SAVE, 0, 0x55);
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xB3, AccWidthUint8 | S3_SAVE, 0, 0x55);
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x91, AccWidthUint8 | S3_SAVE, 0, 0x55);
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x92, AccWidthUint8 | S3_SAVE, 0, 0x55);
+
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x00, AccWidthUint8 | S3_SAVE, 0, 0x06);
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x10, AccWidthUint8 | S3_SAVE, 0, 0x06);
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x20, AccWidthUint8 | S3_SAVE, 0, 0x06);
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x30, AccWidthUint8 | S3_SAVE, 0, 0x06);
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x40, AccWidthUint8 | S3_SAVE, 0, 0x06);
+
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x66, AccWidthUint8 | S3_SAVE, 0, 0x01);
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x6B, AccWidthUint8 | S3_SAVE, 0, 0x01);
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x70, AccWidthUint8 | S3_SAVE, 0, 0x01);
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x75, AccWidthUint8 | S3_SAVE, 0, 0x01);
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x7A, AccWidthUint8 | S3_SAVE, 0, 0x01);
+
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xF8, AccWidthUint8 | S3_SAVE, 0, 0x05);
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xF9, AccWidthUint8 | S3_SAVE, 0, 0x06);
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xFF, AccWidthUint8 | S3_SAVE, 0, 0x42);
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xE9, AccWidthUint8 | S3_SAVE, 0, 0xFF);
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xEB, AccWidthUint8 | S3_SAVE, 0, 0x1F);
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xEF, AccWidthUint8 | S3_SAVE, 0, 0x04);
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xFB, AccWidthUint8 | S3_SAVE, 0, 0x00);
+}
+#endif
diff --git a/src/vendorcode/amd/cimx/sb800/SbDef.h b/src/vendorcode/amd/cimx/sb800/SbDef.h
new file mode 100644
index 0000000..79310fd
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/SbDef.h
@@ -0,0 +1,261 @@
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+
+//AMD Library Routines (AMDLIB.C)
+unsigned char getNumberOfCpuCores (OUT void);
+unsigned int readAlink (IN unsigned int Index);
+void writeAlink (IN unsigned int Index, IN unsigned int Data);
+void rwAlink (IN unsigned int Index, IN unsigned int AndMask, IN unsigned int OrMask);
+
+//AMD Library Routines (LEGACY.C)
+unsigned int GetFixUp (OUT void);
+
+//AMD Library Routines (IOLIB.C)
+void ReadIO (IN unsigned short Address, IN unsigned char OpFlag, IN void *Value);
+void WriteIO (IN unsigned short Address, IN unsigned char OpFlag, IN void *Value);
+void RWIO (IN unsigned short Address, IN unsigned char OpFlag, IN unsigned int Mask, IN unsigned int Data);
+
+
+
+//AMD Library Routines (MEMLIB.C)
+void ReadMEM (IN unsigned int Address, IN unsigned char OpFlag, IN void* Value);
+void WriteMEM (IN unsigned int Address, IN unsigned char OpFlag, IN void* Value);
+void RWMEM (IN unsigned int Address, IN unsigned char OpFlag, IN unsigned int Mask, IN unsigned int Data);
+
+//AMD Library Routines (PCILIB.C)
+void ReadPCI (IN unsigned int Address, IN unsigned char OpFlag, IN void *Value);
+void WritePCI (IN unsigned int Address, IN unsigned char OpFlag, IN void *Value);
+void RWPCI (IN unsigned int Address, IN unsigned char OpFlag, IN unsigned int Mask, IN unsigned int Data);
+
+//AMD Library Routines (SBPELIB.C)
+/**
+ * Read Southbridge Revision ID cie Base
+ *
+ *
+ * @retval 0xXXXXXXXX Revision ID
+ *
+ */
+unsigned char getRevisionID (OUT void);
+
+/**
+ * programPciByteTable - Program PCI register by table (8 bits data)
+ *
+ *
+ *
+ * @param[in] pPciByteTable - Table data pointer
+ * @param[in] dwTableSize - Table length
+ *
+ */
+void programPciByteTable (IN REG8MASK* pPciByteTable, IN unsigned short dwTableSize);
+
+/**
+ * programSbAcpiMmioTbl - Program SB ACPI MMIO register by table (8 bits data)
+ *
+ *
+ *
+ * @param[in] pAcpiTbl - Table data pointer
+ *
+ */
+void programSbAcpiMmioTbl (IN AcpiRegWrite *pAcpiTbl);
+
+/**
+ * getChipSysMode - Get Chip status
+ *
+ *
+ * @param[in] Value - Return Chip strap status
+ * StrapStatus [15.0] - SB800 chip Strap Status
+ * @li <b>0001</b> - Not USED FWH
+ * @li <b>0002</b> - Not USED LPC ROM
+ * @li <b>0004</b> - EC enabled
+ * @li <b>0008</b> - Reserved
+ * @li <b>0010</b> - Internal Clock mode
+ *
+ */
+void getChipSysMode (IN void* Value);
+
+/**
+ * Read Southbridge CIMx configuration structure pointer
+ *
+ *
+ *
+ * @retval 0xXXXXXXXX CIMx configuration structure pointer.
+ *
+ */
+AMDSBCFG* getConfigPointer (OUT void);
+
+//AMD Library Routines (PMIOLIB.C)
+/**
+ * Read PMIO
+ *
+ *
+ *
+ * @param[in] Address - PMIO Offset value
+ * @param[in] OpFlag - Access sizes
+ * @param[in] Value - Read Data Buffer
+ *
+ */
+void ReadPMIO (IN unsigned char Address, IN unsigned char OpFlag, IN void* Value);
+
+/**
+ * Write PMIO
+ *
+ *
+ *
+ * @param[in] Address - PMIO Offset value
+ * @param[in] OpFlag - Access sizes
+ * @param[in] Value - Write Data Buffer
+ *
+ */
+void WritePMIO (IN unsigned char Address, IN unsigned char OpFlag, IN void* Value);
+
+/**
+ * RWPMIO - Read/Write PMIO
+ *
+ *
+ *
+ * @param[in] Address - PMIO Offset value
+ * @param[in] OpFlag - Access sizes
+ * @param[in] AndMask - Data And Mask 32 bits
+ * @param[in] OrMask - Data OR Mask 32 bits
+ *
+ */
+void RWPMIO (IN unsigned char Address, IN unsigned char OpFlag, IN unsigned int AndMask, IN unsigned int OrMask);
+
+//AMD Library Routines (PMIO2LIB.C)
+
+/**
+ * Read PMIO2
+ *
+ *
+ *
+ * @param[in] Address - PMIO2 Offset value
+ * @param[in] OpFlag - Access sizes
+ * @param[in] Value - Read Data Buffer
+ *
+ */
+void ReadPMIO2 (IN unsigned char Address, IN unsigned char OpFlag, IN void* Value);
+
+/**
+ * Write PMIO 2
+ *
+ *
+ *
+ * @param[in] Address - PMIO2 Offset value
+ * @param[in] OpFlag - Access sizes
+ * @param[in] Value - Write Data Buffer
+ *
+ */
+void WritePMIO2 (IN unsigned char Address, IN unsigned char OpFlag, IN void* Value);
+
+/**
+ * RWPMIO2 - Read/Write PMIO2
+ *
+ *
+ *
+ * @param[in] Address - PMIO2 Offset value
+ * @param[in] OpFlag - Access sizes
+ * @param[in] AndMask - Data And Mask 32 bits
+ * @param[in] OrMask - Data OR Mask 32 bits
+ *
+ */
+void RWPMIO2 (IN unsigned char Address, IN unsigned char OpFlag, IN unsigned int AndMask, IN unsigned int OrMask);
+//AMD Library Routines (ECLIB.C)
+// ECLIB Routines
+
+// #ifndef NO_EC_SUPPORT
+
+/**
+ * EnterEcConfig - Force EC into Config mode
+ *
+ *
+ *
+ *
+ */
+void EnterEcConfig (void);
+
+/**
+ * ExitEcConfig - Force EC exit Config mode
+ *
+ *
+ *
+ *
+ */
+void ExitEcConfig (void);
+
+/**
+ * ReadEC8 - Read EC register data
+ *
+ *
+ *
+ * @param[in] Address - EC Register Offset Value
+ * @param[in] Value - Read Data Buffer
+ *
+ */
+void ReadEC8 (IN unsigned char Address, IN unsigned char* Value);
+
+/**
+ * WriteEC8 - Write date into EC register
+ *
+ *
+ *
+ * @param[in] Address - EC Register Offset Value
+ * @param[in] Value - Write Data Buffer
+ *
+ */
+void WriteEC8 (IN unsigned char Address, IN unsigned char* Value);
+
+/**
+ * RWEC8 - Read/Write EC register
+ *
+ *
+ *
+ * @param[in] Address - EC Register Offset Value
+ * @param[in] AndMask - Data And Mask 8 bits
+ * @param[in] OrMask - Data OR Mask 8 bits
+ *
+ */
+void RWEC8 (IN unsigned char Address, IN unsigned char AndMask, IN unsigned char OrMask);
+
+/**
+ * IsZoneFuncEnable - check every zone support function with BitMap from user define
+ *
+ */
+unsigned char IsZoneFuncEnable ( unsigned short Flag, unsigned char func, unsigned char Zone);
+
+void sbECfancontrolservice (IN AMDSBCFG* pConfig);
+void SBIMCFanInitializeS3 (void);
+void GetSbAcpiMmioBase (OUT unsigned int* AcpiMmioBase);
+void GetSbAcpiPmBase (OUT unsigned short* AcpiPmBase);
+
+// #endif
+
diff --git a/src/vendorcode/amd/cimx/sb800/SbMain.c b/src/vendorcode/amd/cimx/sb800/SbMain.c
new file mode 100644
index 0000000..a494d30
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/SbMain.c
@@ -0,0 +1,258 @@
+/**
+ * @file
+ *
+ * SB Initialization.
+ *
+ * Init IOAPIC/IOMMU/Misc NB features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$ @e \$Date:$
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "SBPLATFORM.h"
+#include "cbtypes.h"
+
+#ifndef B1_IMAGE
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * sbBeforePciInit - Config Southbridge before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+
+VOID
+sbBeforePciInit (
+ IN AMDSBCFG* pConfig
+ )
+{
+ commonInitEarlyBoot (pConfig);
+ commonInitEarlyPost (pConfig);
+#ifndef NO_EC_SUPPORT
+ ecInitBeforePciEnum (pConfig);
+#endif
+ usbInitBeforePciEnum (pConfig); // USB POST TIME Only
+ sataInitBeforePciEnum (pConfig); // Init SATA class code and PHY
+ gecInitBeforePciEnum (pConfig); // Init GEC
+ azaliaInitBeforePciEnum (pConfig); // Detect and configure High Definition Audio
+ sbPcieGppEarlyInit (pConfig); // Gpp port init
+ abSpecialSetBeforePciEnum (pConfig);
+ usbDesertPll (pConfig);
+}
+
+/**
+ * sbAfterPciInit - Config Southbridge after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+sbAfterPciInit (
+ IN AMDSBCFG* pConfig
+ )
+{
+ usbInitAfterPciInit (pConfig); // Init USB MMIO
+ sataInitAfterPciEnum (pConfig); // SATA port enumeration
+ gecInitAfterPciEnum (pConfig);
+ azaliaInitAfterPciEnum (pConfig); // Detect and configure High Definition Audio
+
+#ifndef NO_HWM_SUPPORT
+ hwmInit (pConfig);
+#endif
+}
+
+/**
+ * sbMidPostInit - Config Southbridge during middle of POST
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+sbMidPostInit (
+ IN AMDSBCFG* pConfig
+ )
+{
+ sataInitMidPost (pConfig);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * sbLatePost - Prepare Southbridge to boot to OS.
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+sbLatePost (
+ IN AMDSBCFG* pConfig
+ )
+{
+// UINT16 dwVar;
+ BUILDPARAM *pStaticOptions;
+ pStaticOptions = &(pConfig->BuildParameters);
+ commonInitLateBoot (pConfig);
+ sataInitLatePost (pConfig);
+ gecInitLatePost (pConfig);
+ hpetInit (pConfig, pStaticOptions); // SB Configure HPET base and enable bit
+#ifndef NO_EC_SUPPORT
+ ecInitLatePost (pConfig);
+#endif
+ sbPcieGppLateInit (pConfig);
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * sbBeforePciRestoreInit - Config Southbridge before ACPI S3 resume PCI config device restore
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+
+VOID
+sbBeforePciRestoreInit (
+ IN AMDSBCFG* pConfig
+ )
+{
+ pConfig->S3Resume = 1;
+ commonInitEarlyBoot (pConfig); // set /SMBUS/ACPI/IDE/LPC/PCIB
+ abLinkInitBeforePciEnum (pConfig); // Set ABCFG registers
+ usbInitBeforePciEnum (pConfig); // USB POST TIME Only
+ sataInitBeforePciEnum (pConfig);
+ gecInitBeforePciEnum (pConfig); // Init GEC
+ azaliaInitBeforePciEnum (pConfig); // Detect and configure High Definition Audio
+ sbPcieGppEarlyInit (pConfig); // Gpp port init
+ abSpecialSetBeforePciEnum (pConfig);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * sbAfterPciRestoreInit - Config Southbridge after ACPI S3 resume PCI config device restore
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+
+VOID
+sbAfterPciRestoreInit (
+ IN AMDSBCFG* pConfig
+ )
+{
+ BUILDPARAM *pStaticOptions;
+
+ pConfig->S3Resume = 1;
+
+ usbSetPllDuringS3 (pConfig);
+ pStaticOptions = &(pConfig->BuildParameters);
+ commonInitLateBoot (pConfig);
+ sataInitAfterPciEnum (pConfig);
+ gecInitAfterPciEnum (pConfig);
+ azaliaInitAfterPciEnum (pConfig); // Detect and configure High Definition Audio
+ hpetInit (pConfig, pStaticOptions); // SB Configure HPET base and enable bit
+ sataInitLatePost (pConfig);
+ c3PopupSetting (pConfig);
+
+#ifndef NO_HWM_SUPPORT
+ SBIMCFanInitializeS3 ();
+#endif
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * sbSmmAcpiOn - Config Southbridge during ACPI_ON
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+sbSmmAcpiOn (
+ IN AMDSBCFG* pConfig
+ )
+{
+ // Commented the following code since we need to leave the IRQ1/12 filtering enabled always as per latest
+ // recommendation in RPR. This is required to fix the keyboard stuck issue when playing games under Windows
+ AMDSBCFG* pTmp; //lx-dummy for /W4 build
+ pTmp = pConfig;
+
+ // Disable Power Button SMI
+ RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB2, AccWidthUint8, ~(BIT4 + BIT5), 0);
+ RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGAC, AccWidthUint8, ~(BIT6 + BIT7), 0);
+}
+
+#endif
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Call Back routine.
+ *
+ *
+ *
+ * @param[in] Func Callback ID.
+ * @param[in] Data Callback specific data.
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ */
+UINT32
+CallBackToOEM (
+ IN UINT32 Func,
+ IN UINT32 Data,
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT32 Result;
+ Result = 0;
+ if ( pConfig->StdHeader.CALLBACK.CalloutPtr == NULL ) return Result;
+ Result = (pConfig->StdHeader.CALLBACK.CalloutPtr) ( Func, Data, pConfig);
+
+ return Result;
+}
+
+
diff --git a/src/vendorcode/amd/cimx/sb800/SbPeLib.c b/src/vendorcode/amd/cimx/sb800/SbPeLib.c
new file mode 100644
index 0000000..403f21f
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/SbPeLib.c
@@ -0,0 +1,198 @@
+/**
+ * @file
+ *
+ * Southbridge IO access common routine
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$ @e \$Date:$
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "SBPLATFORM.h"
+#include "cbtypes.h"
+
+/**
+ * Read Southbridge Revision ID cie Base
+ *
+ *
+ * @retval 0xXXXXXXXX Revision ID
+ *
+ */
+UINT8
+getRevisionID (
+ OUT VOID
+ )
+{
+ UINT8 dbVar0;
+ ReadPCI (((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG08), AccWidthUint8, &dbVar0);
+ return dbVar0;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * programPciByteTable - Program PCI register by table (8 bits data)
+ *
+ *
+ *
+ * @param[in] pPciByteTable - Table data pointer
+ * @param[in] dwTableSize - Table length
+ *
+ */
+VOID
+programPciByteTable (
+ IN REG8MASK* pPciByteTable,
+ IN UINT16 dwTableSize
+ )
+{
+ UINT8 i;
+ UINT8 dbBusNo;
+ UINT8 dbDevFnNo;
+ UINT32 ddBDFR;
+
+ dbBusNo = pPciByteTable->bRegIndex;
+ dbDevFnNo = pPciByteTable->bANDMask;
+ pPciByteTable++;
+
+ for ( i = 1; i < dwTableSize; i++ ) {
+ if ( (pPciByteTable->bRegIndex == 0xFF) && (pPciByteTable->bANDMask == 0xFF) && (pPciByteTable->bORMask == 0xFF) ) {
+ pPciByteTable++;
+ dbBusNo = pPciByteTable->bRegIndex;
+ dbDevFnNo = pPciByteTable->bANDMask;
+ pPciByteTable++;
+ i++;
+ } else {
+ ddBDFR = (dbBusNo << 24) + (dbDevFnNo << 16) + (pPciByteTable->bRegIndex) ;
+ RWPCI (ddBDFR, AccWidthUint8 | S3_SAVE, pPciByteTable->bANDMask, pPciByteTable->bORMask);
+ pPciByteTable++;
+ }
+ }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * programSbAcpiMmioTbl - Program SB ACPI MMIO register by table (8 bits data)
+ *
+ *
+ *
+ * @param[in] pAcpiTbl - Table data pointer
+ *
+ */
+VOID
+programSbAcpiMmioTbl (
+ IN AcpiRegWrite *pAcpiTbl
+ )
+{
+ UINT8 i;
+ UINT32 ddtempVar;
+ if (pAcpiTbl != NULL) {
+ for ( i = 1; pAcpiTbl->MmioBase < 0xf0; i++ ) {
+ ddtempVar = 0xFED80000 | (pAcpiTbl->MmioBase) << 8 | pAcpiTbl->MmioReg;
+ RWMEM (ddtempVar, AccWidthUint8, ((pAcpiTbl->DataANDMask) | 0xFFFFFF00), pAcpiTbl->DataOrMask);
+ pAcpiTbl++;
+ }
+ }
+}
+
+/**
+ * getChipSysMode - Get Chip status
+ *
+ *
+ * @param[in] Value - Return Chip strap status
+ * StrapStatus [15.0] - SB800 chip Strap Status
+ * @li <b>0001</b> - Not USED FWH
+ * @li <b>0002</b> - Not USED LPC ROM
+ * @li <b>0004</b> - EC enabled
+ * @li <b>0008</b> - Reserved
+ * @li <b>0010</b> - Internal Clock mode
+ *
+ */
+VOID
+getChipSysMode (
+ IN VOID* Value
+ )
+{
+ ReadMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80, AccWidthUint8, Value);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read Southbridge CIMx configuration structure pointer
+ *
+ *
+ *
+ * @retval 0xXXXXXXXX CIMx configuration structure pointer.
+ *
+ */
+AMDSBCFG*
+getConfigPointer (
+ OUT VOID
+ )
+{
+ UINT8 dbReg;
+ UINT8 dbValue;
+ UINT8 i;
+ UINT32 ddValue;
+ ddValue = 0;
+ dbReg = SB_ECMOS_REG08;
+
+ for ( i = 0; i <= 3; i++ ) {
+ WriteIO (SB_IOMAP_REG72, AccWidthUint8, &dbReg);
+ ReadIO (SB_IOMAP_REG73, AccWidthUint8, &dbValue);
+ ddValue |= (dbValue << (i * 8));
+ dbReg++;
+ }
+ return ( (AMDSBCFG*) (UINTN)ddValue);
+}
+
+/**
+ * getEfuseStatue - Get Efuse status
+ *
+ *
+ * @param[in] Value - Return Chip strap status
+ *
+ */
+VOID
+getEfuseStatus (
+ IN VOID* Value
+ )
+{
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, ~BIT5, BIT5);
+ WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, Value);
+ ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8 + 1, AccWidthUint8, Value);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, ~BIT5, 0);
+}
diff --git a/src/vendorcode/amd/cimx/sb800/SbPort.c b/src/vendorcode/amd/cimx/sb800/SbPort.c
new file mode 100644
index 0000000..048850d
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/SbPort.c
@@ -0,0 +1,366 @@
+
+/**
+ * @file
+ *
+ * Southbridge Init during POWER-ON
+ *
+ * Prepare Southbridge environment during power on stage.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$ @e \$Date:$
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "SBPLATFORM.h"
+#include "cbtypes.h"
+/**
+ * sbPorInitPciTable - PCI device registers initial during the power on stage.
+ */
+const static REG8MASK sbPorInitPciTable[] =
+{
+ // SATA device
+ {0x00, SATA_BUS_DEV_FUN, 0},
+ {SB_SATA_REG84 + 3, ~BIT2, 0},
+ {SB_SATA_REG84 + 1, ~(BIT4 + BIT5), BIT4 + BIT5},
+ {SB_SATA_REGA0, ~(BIT2 + BIT3 + BIT4 + BIT5 + BIT6), BIT2 + BIT3 + BIT4 + BIT5},
+ {0xFF, 0xFF, 0xFF},
+ // LPC Device (Bus 0, Dev 20, Func 3)
+ {0x00, LPC_BUS_DEV_FUN, 0},
+ {SB_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2},
+ {SB_LPC_REG7C, 0x00, BIT0 + BIT2},
+ {SB_LPC_REGBB, 0xFF, BIT3 + BIT4 + BIT5},
+ // A12 set 0xBB [5:3] = 111 to improve SPI timing margin.
+ // A12 Set 0xBA [6:5] = 11 improve SPI timing margin. (SPI Prefetch enhancement)
+ {SB_LPC_REGBB, 0xBE, BIT0 + BIT3 + BIT4 + BIT5},
+ {SB_LPC_REGBA, 0x9F, BIT5 + BIT6},
+ {0xFF, 0xFF, 0xFF},
+ // P2P Bridge (Bus 0, Dev 20, Func 4)
+ {0x00, PCIB_BUS_DEV_FUN, 0},
+ {SB_PCIB_REG4B, 0xFF, BIT6 + BIT7 + BIT4},
+ // Enable IO but not allocate any IO range. This is for post code display on debug port behind P2P bridge.
+ {SB_PCIB_REG1C, 0x00, 0xF0},
+ {SB_PCIB_REG1D, 0x00, 0x00},
+ {SB_PCIB_REG04, 0x00, 0x21},
+ {SB_PCIB_REG40, 0xDF, 0x20},
+ {SB_PCIB_REG50, 0x02, 0x01},
+ {0xFF, 0xFF, 0xFF},
+};
+
+/**
+ * sbPmioPorInitTable - Southbridge ACPI MMIO initial during the power on stage.
+ */
+const static AcpiRegWrite sbPmioPorInitTable[] =
+{
+ {PMIO_BASE >> 8, SB_PMIOA_REG5D, 0x00, BIT0},
+ {PMIO_BASE >> 8, SB_PMIOA_REGD2, 0xCF, BIT4 + BIT5},
+ {SMBUS_BASE >> 8, SB_SMBUS_REG12, 0x00, BIT0},
+ {PMIO_BASE >> 8, SB_PMIOA_REG28, 0xFF, BIT0},
+ {PMIO_BASE >> 8, SB_PMIOA_REG44 + 3, 0x7F, BIT7},
+ {PMIO_BASE >> 8, SB_PMIOA_REG48, 0xFF, BIT0},
+ {PMIO_BASE >> 8, SB_PMIOA_REG00, 0xFF, 0x0E},
+ {PMIO_BASE >> 8, SB_PMIOA_REG00 + 2, 0xFF, 0x40},
+ {PMIO_BASE >> 8, SB_PMIOA_REG00 + 3, 0xFF, 0x08},
+ {PMIO_BASE >> 8, SB_PMIOA_REG34, 0xEF, BIT0 + BIT1},
+ {PMIO_BASE >> 8, SB_PMIOA_REGEC, 0xFD, BIT1},
+ {PMIO_BASE >> 8, SB_PMIOA_REG5B, 0xF9, BIT1 + BIT2},
+ {PMIO_BASE >> 8, SB_PMIOA_REG08, 0xFE, BIT2 + BIT4},
+ {PMIO_BASE >> 8, SB_PMIOA_REG08 + 1, 0xFF, BIT0},
+ {PMIO_BASE >> 8, SB_PMIOA_REG54, 0x00, BIT4 + BIT7},
+ {PMIO_BASE >> 8, SB_PMIOA_REG04 + 3, 0xFD, BIT1},
+ {PMIO_BASE >> 8, SB_PMIOA_REG74, 0xF6, BIT0 + BIT3},
+ {PMIO_BASE >> 8, SB_PMIOA_REGF0, ~BIT2, 0x00},
+ // RPR GEC I/O Termination Setting
+ // PM_Reg 0xF6 = Power-on default setting
+ // PM_Reg 0xF7 = Power-on default setting
+ // PM_Reg 0xF8 = 0x6C
+ // PM_Reg 0xF9 = 0x21
+ // PM_Reg 0xFA = 0x00 SB800 A12 GEC I/O Pad settings for 3.3V CMOS
+ {PMIO_BASE >> 8, SB_PMIOA_REGF8, 0x00, 0x6C},
+ {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 1, 0x00, 0x27},
+ {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 2, 0x00, 0x00},
+ {PMIO_BASE >> 8, SB_PMIOA_REGC4, 0xFE, 0x14},
+ {PMIO_BASE >> 8, SB_PMIOA_REGC0 + 2, 0xBF, 0x40},
+
+ {PMIO_BASE >> 8, SB_PMIOA_REGBE, 0xDF, BIT5},//ENH210907 SB800: request to no longer clear kb_pcirst_en (bit 1) of PM_Reg BEh per the RPR
+
+ {0xFF, 0xFF, 0xFF, 0xFF},
+};
+
+/**
+ * sbPowerOnInit - Config Southbridge during power on stage.
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+sbPowerOnInit (
+ IN AMDSBCFG* pConfig
+ )
+{
+
+ UINT8 dbPortStatus;
+ UINT8 dbSysConfig;
+ UINT32 abValue;
+ UINT8 dbValue;
+ UINT8 dbEfuse;
+ UINT8 dbCg2WR;
+ UINT8 dbCg1Pll;
+ UINT8 cimNbSbGen2;
+ UINT8 cimSataMode;
+ UINT8 cimSpiFastReadEnable;
+ UINT8 cimSpiFastReadSpeed;
+ UINT8 cimSioHwmPortEnable;
+ UINT8 SataPortNum;
+
+ cimNbSbGen2 = pConfig->NbSbGen2;
+ cimSataMode = pConfig->SATAMODE.SataModeReg;
+// Adding Fast Read Function support
+ if (pConfig->BuildParameters.SpiFastReadEnable != 0 ) {
+ cimSpiFastReadEnable = (UINT8) pConfig->BuildParameters.SpiFastReadEnable;
+ } else {
+ cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
+ }
+ cimSpiFastReadSpeed = (UINT8) pConfig->BuildParameters.SpiFastReadSpeed;
+ cimSioHwmPortEnable = pConfig->SioHwmPortEnable;
+#if SB_CIMx_PARAMETER == 0
+ cimNbSbGen2 = cimNbSbGen2Default;
+ cimSataMode = (UINT8) ((cimSataMode & 0xFB) | cimSataSetMaxGen2Default);
+ cimSataMode = (UINT8) ((cimSataMode & 0x0F) | (cimSATARefClkSelDefault + cimSATARefDivSelDefault));
+ cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
+ cimSpiFastReadSpeed = cimSpiFastReadSpeedDefault;
+ cimSioHwmPortEnable = cimSioHwmPortEnableDefault;
+#endif
+
+// SB800 Only Enabled (Mmio_mem_enablr) // Default value is correct
+ RWPMIO (SB_PMIOA_REG24, AccWidthUint8, 0xFF, BIT0);
+
+// Set A-Link bridge access address. This address is set at device 14h, function 0,
+// register 0f0h. This is an I/O address. The I/O address must be on 16-byte boundary.
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGE0, AccWidthUint32, 00, ALINK_ACCESS_INDEX);
+ writeAlink (0x80000004, 0x04); // RPR 4.2 Enable SB800 to issue memory read/write requests in the upstream direction
+ abValue = readAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29)); // RPR 4.5 Disable the credit variable in the downstream arbitration equation
+ abValue = abValue | BIT0;
+ writeAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29), abValue);
+ writeAlink (0x30, 0x10); // AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform.
+ writeAlink (0x34, readAlink (0x34) | BIT9);
+
+ dbEfuse = FUSE_ID_EFUSE_LOC;
+ getEfuseStatus (&dbEfuse);
+ if ( dbEfuse == M1_D1_FUSE_ID ) {
+ dbEfuse = MINOR_ID_EFUSE_LOC;
+ getEfuseStatus (&dbEfuse);
+ if ( dbEfuse == M1_MINOR_ID ) {
+ // Limit ALink speed to 2.5G if Hudson-M1
+ cimNbSbGen2 = 0;
+ }
+ }
+// Step 1:
+// AXINDP_Reg 0xA4[0] = 0x1
+// Step 2:
+// AXCFG_Reg 0x88[3:0] = 0x2
+// Step3:
+// AXINDP_Reg 0xA4[18] = 0x1
+ if ( cimNbSbGen2 == TRUE ) {
+ rwAlink (SB_AX_INDXP_REGA4, 0xFFFFFFFF, BIT0);
+ rwAlink ((UINT32)SB_AX_CFG_REG88, 0xFFFFFFF0, 0x2);
+ rwAlink (SB_AX_INDXP_REGA4, 0xFFFFFFFF, BIT18);
+ }
+
+// Set Build option into SB
+ WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioPmeBaseAddress));
+ if (cimSioHwmPortEnable) {
+ // Use Wide IO Port 1 to provide access to the superio HWM registers.
+ WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG66 , AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioHwmBaseAddress));
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG48 + 3, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); // Wide IO Port 1: enable
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG74 , AccWidthUint8 | S3_SAVE, 0xFF, BIT2); // set width 0:512, 1:16 bytes
+ }
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F, (pConfig->BuildParameters.SpiRomBaseAddress));
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint32 | S3_SAVE, 0, (pConfig->BuildParameters.GecShadowRomBase + 1));
+// Enabled SMBUS0/SMBUS1 (ASF) Base Address
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2C, AccWidthUint16, 06, (pConfig->BuildParameters.Smbus0BaseAddress) + BIT0); //protect BIT[2:1]
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG28, AccWidthUint16, 00, (pConfig->BuildParameters.Smbus1BaseAddress));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG60, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1EvtBlkAddr));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG62, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1CntBlkAddr));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmTmrBlkAddr));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG66, AccWidthUint16, 00, (pConfig->BuildParameters.CpuControlBlkAddr));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG68, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiGpe0BlkAddr));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6A, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6C, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmaCntBlkAddr));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6E, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr) + 8);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG48, AccWidthUint32, 00, (pConfig->BuildParameters.WatchDogTimerBase));
+
+ dbEfuse = SATA_FIS_BASE_EFUSE_LOC;
+ getEfuseStatus (&dbEfuse);
+
+ programSbAcpiMmioTbl ((AcpiRegWrite*) FIXUP_PTR (&sbPmioPorInitTable[0]));
+
+
+ SataPortNum = 0;
+ for ( SataPortNum = 0; SataPortNum < 0x06; SataPortNum++ ) {
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, 1 << SataPortNum);
+ SbStall (2);
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, (0xFF ^ (1 << SataPortNum)) , 0x00);
+ SbStall (2);
+ }
+
+
+ //The following bits must be set before enabling SPI prefetch.
+ // Set SPI MMio bit offset 00h[19] to 1 and offset 00h[26:24] to 111, offset 0ch[21:16] to 1, Set LPC cfg BBh[6] to 0 ( by default it is 0).
+ // if Ec is enable
+ // Maximum spi speed that can be supported by SB is 22M (SPI Mmio offset 0ch[13:12] to 10) if the rom can run at the speed.
+ // else
+ // Maximum spi speed that can be supported by SB is 33M (SPI Mmio offset 0ch[13:12] to 01 in normal mode or offset 0ch[15:14] in fast mode) if the rom can run at
+ // the speed.
+ getChipSysMode (&dbSysConfig);
+ if (pConfig->BuildParameters.SpiSpeed < 0x02) {
+ pConfig->BuildParameters.SpiSpeed = 0x01;
+ if (dbSysConfig & ChipSysEcEnable) pConfig->BuildParameters.SpiSpeed = 0x02;
+ }
+
+ if (pConfig->SbSpiSpeedSupport) {
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, (BIT19 + BIT24 + BIT25 + BIT26));
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, 0xFFC0FFFF, 1 << 16 );
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT13 + BIT12), (pConfig->BuildParameters.SpiSpeed << 12));
+ }
+ // SPI Fast Read Function
+ if ( cimSpiFastReadEnable ) {
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFBFFFF, BIT18);
+ } else {
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFBFFFF, 0x00);
+ }
+
+ if ( cimSpiFastReadSpeed ) {
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT15 + BIT14), ( cimSpiFastReadSpeed << 14));
+ }
+ //Program power on pci init table
+ programPciByteTable ( (REG8MASK*) FIXUP_PTR (&sbPorInitPciTable[0]), sizeof (sbPorInitPciTable) / sizeof (REG8MASK) );
+
+ programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr));
+
+ dbValue = 0x0A;
+ WriteIO (SB_IOMAP_REG70, AccWidthUint8, &dbValue);
+ ReadIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
+ dbValue &= 0xEF;
+ WriteIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
+
+// Change the CG PLL multiplier to x1.1
+ if ( pConfig->UsbRxMode !=0 ) {
+ dbCg2WR = 0x00;
+ dbCg1Pll = 0x3A;
+ ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, &dbCg2WR);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, 0, 0x3A);
+ ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD9, AccWidthUint8, &dbCg1Pll);
+ dbCg2WR &= BIT4;
+ if (( dbCg2WR == 0x00 ) && ( dbCg1Pll !=0x10 ))
+ {
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x18, AccWidthUint8, 0xE1, 0x10);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, 0, 0x3A);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD9, AccWidthUint8, 0, USB_PLL_Voltage);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, 0xEF, 0x10);
+ dbValue = 0x06;
+ WriteIO (0xCF9, AccWidthUint8, &dbValue);
+ } else {
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, 0xEF, 0x00);
+ }
+ }
+
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint32 | S3_SAVE, ~(pConfig->BuildParameters.BiosSize << 4), 0);
+
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0, (pConfig->SATAMODE.SataModeReg) & 0xFD );
+
+ if (dbEfuse & BIT0) {
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0xFB, 0x04);
+ }
+
+ ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, &dbPortStatus);
+ if ( ((dbPortStatus & 0xF0) == 0x10) ) {
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_PMIOA_REG08, AccWidthUint8, 0, BIT5);
+ }
+
+ if ( pConfig->BuildParameters.LegacyFree ) {
+ RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000);
+ } else {
+ RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5);
+ }
+
+ dbValue = 0x09;
+ WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue);
+ ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
+ if ( !pConfig->BuildParameters.EcKbd ) {
+ // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
+ dbValue = dbValue & 0xF9;
+ }
+ if ( pConfig->BuildParameters.LegacyFree ) {
+ // Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation.
+ dbValue = dbValue & 0x9F;
+ }
+ // Enabled IRQ input
+ dbValue = dbValue | BIT4;
+ WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
+
+#ifndef NO_EC_SUPPORT
+ getChipSysMode (&dbPortStatus);
+ if ( ((dbPortStatus & ChipSysEcEnable) == 0x00) ) {
+ // EC is disabled by jumper setting or board config
+ RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4), AccWidthUint16 | S3_SAVE, 0xFFFE, BIT0);
+ } else {
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xF7, 0x08);
+ ecPowerOnInit ( pConfig);
+ }
+#endif
+
+ ReadMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80, AccWidthUint8, &dbValue);
+ if (dbValue & ChipSysIntClkGen) {
+ ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, &dbValue);
+ if (dbValue & BIT2) {
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC0 + 2, AccWidthUint8, 0xDF, 0x20);
+ } else {
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xFB, 0x40);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC0 + 2, AccWidthUint8, 0xDF, 0x20);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xFB, 0x00);
+ }
+ }
+
+ // Restore GPP clock to on as it may be off during last POST when some device was disabled;
+ // the device can't be detected if enabled again as the values retain on S5 and warm reset.
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG00, AccWidthUint32, 0xFFFFFFFF, 0xFFFFFFFF);
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG04, AccWidthUint8, 0xFF, 0xFF);
+
+ // Set PMx88[5]to enable LdtStp# output to do the C3 or FidVid transation
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8, 0xFF, BIT5);
+}
diff --git a/src/vendorcode/amd/cimx/sb800/SbSubFun.h b/src/vendorcode/amd/cimx/sb800/SbSubFun.h
new file mode 100644
index 0000000..6b8c8d4
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/SbSubFun.h
@@ -0,0 +1,523 @@
+/**
+ * @file
+ *
+ * Southbridge CIMx Function Support Define (All)
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$ @e \$Date:$
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+// Southbridge SBMAIN Routines
+
+/**
+ * Southbridge Main Function Public Function
+ *
+ */
+
+/**
+ * sbBeforePciInit - Config Southbridge before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbBeforePciInit (IN AMDSBCFG* pConfig);
+
+
+/**
+ * sbAfterPciInit - Config Southbridge after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbAfterPciInit (IN AMDSBCFG* pConfig);
+
+/**
+ * sbMidPostInit - Config Southbridge during middle of POST
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbMidPostInit (IN AMDSBCFG* pConfig);
+
+/**
+ * sbLatePost - Prepare Southbridge to boot to OS.
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbLatePost (IN AMDSBCFG* pConfig);
+
+/**
+ * sbBeforePciRestoreInit - Config Southbridge before ACPI S3 resume PCI config device restore
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbBeforePciRestoreInit (IN AMDSBCFG* pConfig);
+
+/**
+ * sbAfterPciRestoreInit - Config Southbridge after ACPI S3 resume PCI config device restore
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbAfterPciRestoreInit (IN AMDSBCFG* pConfig);
+
+/**
+ * sbSmmAcpiOn - Config Southbridge during ACPI_ON
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbSmmAcpiOn (IN AMDSBCFG* pConfig);
+
+/**
+ * CallBackToOEM - Call Back routine.
+ *
+ *
+ *
+ * @param[in] Func Callback ID.
+ * @param[in] Data Callback specific data.
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ */
+unsigned int CallBackToOEM (IN unsigned int Func, IN unsigned int Data, IN AMDSBCFG* pConfig);
+
+
+// Southbridge SBPOR Routines
+
+/**
+ * Southbridge power-on initial Public Function
+ *
+ */
+
+/**
+ * sbPowerOnInit - Config Southbridge during power on stage.
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbPowerOnInit (IN AMDSBCFG* pConfig);
+
+
+// Southbridge Common Routines
+
+/**
+ * Southbridge Common Public Function
+ *
+ */
+
+/**
+ * commonInitEarlyBoot - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB.
+ *
+ * This settings should be done during S3 resume also
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void commonInitEarlyBoot (IN AMDSBCFG* pConfig);
+
+/**
+ * commonInitEarlyPost - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB.
+ *
+ * This settings might not program during S3 resume
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void commonInitEarlyPost (IN AMDSBCFG* pConfig);
+
+/**
+ * commonInitLateBoot - Prepare Southbridge register setting to boot to OS.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void commonInitLateBoot (IN AMDSBCFG* pConfig);
+
+/**
+ * abSpecialSetBeforePciEnum - Special setting ABCFG registers before PCI emulation.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void abSpecialSetBeforePciEnum (IN AMDSBCFG* pConfig);
+
+void usbSetPllDuringS3 (IN AMDSBCFG* pConfig);
+void usbDesertPll (IN AMDSBCFG* pConfig);
+
+/**
+ * hpetInit - Program Southbridge HPET function
+ *
+ * ** Eric
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ * @param[in] pStaticOptions Platform build configuration table.
+ *
+ */
+void hpetInit (IN AMDSBCFG* pConfig, IN BUILDPARAM *pStaticOptions);
+
+/**
+ * c3PopupSetting - Program Southbridge C state function
+ *
+ * ** Eric
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void c3PopupSetting (IN AMDSBCFG* pConfig);
+
+/**
+ * FusionRelatedSetting - Program Fusion C related function
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void FusionRelatedSetting (IN AMDSBCFG* pConfig);
+
+/**
+ * Southbridge Common Private Function
+ *
+ */
+
+/**
+ * abLinkInitBeforePciEnum - Set ABCFG registers before PCI emulation.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void abLinkInitBeforePciEnum (IN AMDSBCFG* pConfig);
+
+// Southbridge SATA Routines
+
+/**
+ * Southbridge SATA Controller Public Function
+ *
+ */
+
+/**
+ * sataInitMidPost - Config SATA controller in Middle POST.
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sataInitMidPost (IN AMDSBCFG* pConfig);
+
+/**
+ * sataInitAfterPciEnum - Config SATA controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sataInitAfterPciEnum (IN AMDSBCFG* pConfig);
+
+/**
+ * sataInitBeforePciEnum - Config SATA controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sataInitBeforePciEnum (IN AMDSBCFG* pConfig);
+
+/**
+ * sataInitLatePost - Prepare SATA controller to boot to OS.
+ *
+ * - Set class ID to AHCI (if set to AHCI * Mode)
+ * - Enable AHCI interrupt
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sataInitLatePost (IN AMDSBCFG* pConfig);
+
+// Southbridge GEC Routines
+
+/**
+ * Southbridge GEC Controller Public Function
+ *
+ */
+
+/**
+ * gecInitBeforePciEnum - Config GEC controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void gecInitBeforePciEnum (IN AMDSBCFG* pConfig);
+
+/**
+ * gecInitAfterPciEnum - Config GEC controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void gecInitAfterPciEnum (IN AMDSBCFG* pConfig);
+
+/**
+ * gecInitLatePost - Prepare GEC controller to boot to OS.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void gecInitLatePost (IN AMDSBCFG* pConfig);
+
+// Southbridge USB Routines
+
+/**
+ * Southbridge USB Controller Public Function
+ *
+ */
+
+/**
+ * Config USB controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void usbInitBeforePciEnum (IN AMDSBCFG* pConfig);
+
+/**
+ * Config USB controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void usbInitAfterPciInit (IN AMDSBCFG* pConfig);
+
+/**
+ * Config USB1 EHCI controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void usb1EhciInitAfterPciInit (IN AMDSBCFG* pConfig);
+void usb2EhciInitAfterPciInit (IN AMDSBCFG* pConfig);
+void usb3EhciInitAfterPciInit (IN AMDSBCFG* pConfig);
+void usb1OhciInitAfterPciInit (IN AMDSBCFG* pConfig);
+void usb2OhciInitAfterPciInit (IN AMDSBCFG* pConfig);
+void usb3OhciInitAfterPciInit (IN AMDSBCFG* pConfig);
+void usb4OhciInitAfterPciInit (IN AMDSBCFG* pConfig);
+
+// Southbridge SMI Service Routines (SMM.C)
+
+/**
+ * Southbridge SMI Service Routines Public Function
+ *
+ */
+
+/**
+ * Southbridge SMI service module
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbSmmService (IN AMDSBCFG* pConfig);
+
+/**
+ * softwareSMIservice - Software SMI service
+ *
+ * ** Eric
+ *
+ * @param[in] void Southbridge software SMI service ID.
+ *
+ */
+void softwareSMIservice (IN void);
+
+// Southbridge GPP Controller Routines
+
+/**
+ * Southbridge GPP Controller Routines Public Function
+ *
+ */
+
+/**
+ * GPP early programming and link training. On exit all populated EPs should be fully operational.
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbPcieGppEarlyInit (IN AMDSBCFG* pConfig);
+
+/**
+ * sbPcieGppLateInit - Late PCIE initialization for SB800 GPP component
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbPcieGppLateInit (IN AMDSBCFG* pConfig);
+
+// Southbridge HD Controller Routines (AZALIA.C)
+
+/**
+ * Southbridge HD Controller Routines (AZALIA.C) Public Function
+ *
+ */
+
+/**
+ * Config HD Audio Before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void azaliaInitBeforePciEnum (IN AMDSBCFG* pConfig);
+
+/**
+ * Config HD Audio after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void azaliaInitAfterPciEnum (IN AMDSBCFG* pConfig);
+
+
+// Southbridge EC Routines
+
+#ifndef NO_EC_SUPPORT
+/**
+ * Southbridge EC Controller Public Function
+ *
+ */
+
+/**
+ * Config EC controller during power-on
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+ void ecPowerOnInit (IN AMDSBCFG* pConfig);
+
+/**
+ * Config EC controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+ void ecInitBeforePciEnum (IN AMDSBCFG* pConfig);
+
+/**
+ * Prepare EC controller to boot to OS.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+ void ecInitLatePost (IN AMDSBCFG* pConfig);
+
+/**
+ * validateImcFirmware - Validate IMC Firmware.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ * @retval TRUE Pass
+ * @retval FALSE Failed
+ */
+ unsigned char validateImcFirmware (IN AMDSBCFG* pConfig);
+
+/**
+ * validateImcFirmware - Validate IMC Firmware.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+ void softwareToggleImcStrapping (IN AMDSBCFG* pConfig);
+#endif
+
+#ifndef NO_HWM_SUPPORT
+/**
+ * validateImcFirmware - Validate IMC Firmware.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+ void hwmInit (IN AMDSBCFG* pConfig);
+#endif
+
diff --git a/src/vendorcode/amd/cimx/sb800/SbType.h b/src/vendorcode/amd/cimx/sb800/SbType.h
new file mode 100644
index 0000000..b897950
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/SbType.h
@@ -0,0 +1,1135 @@
+
+/**
+ * @file
+ *
+ * Southbridge CIMx configuration structure define
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$ @e \$Date:$
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _AMD_SBTYPE_H_
+#define _AMD_SBTYPE_H_
+
+#pragma pack (push, 1)
+
+/**
+ * Entry point of Southbridge CIMx
+ *
+ *
+ * @param[in] Param1 Southbridge CIMx Function ID.
+ * @param[in] Param2 Southbridge Input Data.
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+typedef unsigned int (*SBCIM_HOOK_ENTRY) (unsigned int Param1, unsigned int Param2, void* pConfig);
+/**
+ * SMM_SERVICE_ROUTINE - Southbridge SMI service routine
+ *
+ */
+typedef void (*SMM_SERVICE_ROUTINE) (void);
+
+
+/**
+ * The STATIC platform information for CIMx Module.
+ *
+ */
+typedef struct _BUILDPARAM {
+ unsigned int BiosSize:3; /**< BiosSize
+ * @par
+ * BIOSSize [2.0] - BIOS Image Size
+ * @li <b>0</b> - 1M
+ * @li <b>1</b> - 2M
+ * @li <b>3</b> - 4M
+ * @li <b>7</b> - 8M
+ * In SB800, default ROM size is 1M Bytes, if your platform ROM bigger then 1M
+ * you have to set the ROM size outside CIMx module and before AGESA module get call
+ *
+ */
+ unsigned int LegacyFree:1; /**< LegacyFree
+ * @par
+ * Config Southbridge CIMx module for Legacy Free Mode
+ */
+ unsigned int SpiSpeed:2; /**< SpiSpeed
+ * @par
+ * SPI Speed [1.0] - the clock speed for non-fast read command
+ * @li <b>00</b> - 66Mhz
+ * @li <b>01</b> - 33Mhz
+ * @li <b>10</b> - 22Mhz
+ * @li <b>11</b> - 16.5Mhz
+ *
+ */
+ unsigned int ImcEnableOverWrite:2; /**< ImcEnableOverWrite
+ * @par
+ * Imc Enable OverWrite
+ * @li <b>00</b> - by default strapping
+ * @li <b>01</b> - On
+ * @li <b>10</b> - Off
+ *
+ */
+ unsigned int SpiFastReadEnable:1; /**< SpiFastReadEnable
+ * @par
+ * @li <b>00</b> - Disable SPI Fast Read Function
+ * @li <b>01</b> - Enable SPI Fast Read Function
+ */
+ unsigned int SpiFastReadSpeed:2; /**< SpiFastReadSpeed
+ * @par
+ * @li <b>00</b> - 66Mhz
+ * @li <b>01</b> - 33Mhz
+ * @li <b>10</b> - 22Mhz
+ * @li <b>11</b> - 16.5Mhz
+ */
+ unsigned int SpreadSpectrumType:1; /**< SpreadSpectrumType
+ * @par
+ * @li <b>0</b> - Spread Spectrum for normal platform
+ * @li <b>1</b> - Spread Spectrum for Ontario platform
+ */
+/** Dummy0 - Reserved */
+ unsigned int Dummy0:4;
+ unsigned int EcKbd:1; /**< EcKbd
+ * @par
+ * EcKbd [16] - Platform use EC (as SIO) or SIO chip for PS/2 Keyboard and Mouse
+ * @li <b>0</b> - Use SIO PS/2 function.
+ * @li <b>1</b> - Use EC PS/2 function instead of SIO PS/2 function. **
+ * @li <b>**</b> When set 1, EC function have to enable, otherwise, CIMx treat as legacy-free system.
+ */
+/** EcChannel0 - Reserved */
+ unsigned int EcChannel0:1;
+/** UsbMsi - Reserved */
+ unsigned int UsbMsi:1;
+/** HdAudioMsi - Reserved */
+ unsigned int HdAudioMsi:1;
+/** LpcMsi - Reserved */
+ unsigned int LpcMsi:1;
+/** PcibMsi - Reserved */
+ unsigned int PcibMsi:1;
+/** AbMsi - Reserved */
+ unsigned int AbMsi:1;
+/** Dummy1 - Reserved */
+ unsigned int Dummy1:9;
+
+ unsigned int Smbus0BaseAddress; /**< Smbus0BaseAddress
+ * @par
+ * Smbus BASE Address
+ */
+ unsigned int Smbus1BaseAddress; /**< Smbus1BaseAddress
+ * @par
+ * Smbus1 (ASF) BASE Address
+ */
+ unsigned int SioPmeBaseAddress; /**< SioPmeBaseAddress
+ * @par
+ * SIO PME BASE Address
+ */
+ unsigned int SioHwmBaseAddress; /**< SioHwmBaseAddress
+ * @par
+ * SIO HWM BASE Address
+ */
+ unsigned int WatchDogTimerBase; /**< WatchDogTimerBase
+ * @par
+ * Watch Dog Timer Address
+ */
+ unsigned int GecShadowRomBase; /**< GecShadowRomBase
+ * @par
+ * GEC (NIC) SHADOWROM BASE Address
+ */
+ unsigned int SpiRomBaseAddress; /**< SpiRomBaseAddress
+ * @par
+ * SPI ROM BASE Address
+ */
+ unsigned short AcpiPm1EvtBlkAddr; /**< AcpiPm1EvtBlkAddr
+ * @par
+ * ACPI PM1 event block Address
+ */
+ unsigned short AcpiPm1CntBlkAddr; /**< AcpiPm1CntBlkAddr
+ * @par
+ * ACPI PM1 Control block Address
+ */
+ unsigned short AcpiPmTmrBlkAddr; /**< AcpiPmTmrBlkAddr
+ * @par
+ * ACPI PM timer block Address
+ */
+ unsigned short CpuControlBlkAddr; /**< CpuControlBlkAddr
+ * @par
+ * ACPI CPU control block Address
+ */
+ unsigned short AcpiGpe0BlkAddr; /**< AcpiGpe0BlkAddr
+ * @par
+ * ACPI GPE0 block Address
+ */
+ unsigned short SmiCmdPortAddr; /**< SmiCmdPortAddr
+ * @par
+ * SMI command port Address
+ */
+ unsigned short AcpiPmaCntBlkAddr; /**< AcpiPmaCntBlkAddr
+ * @par
+ * ACPI PMA Control block Address
+ */
+ unsigned int HpetBase; /**< HpetBase
+ * @par
+ * HPET Base address
+ */
+ unsigned int SataIDESsid; /**< SataIDESsid
+ * @par
+ * SATA IDE mode SSID
+ */
+ unsigned int SataRAIDSsid; /**< SataRAIDSsid
+ * @par
+ * SATA RAID mode SSID
+ */
+ unsigned int SataRAID5Ssid; /**< SataRAID5Ssid
+ * @par
+ * SATA RAID5 mode SSID
+ */
+ unsigned int SataAHCISsid; /**< SataAHCISsid
+ * @par
+ * SATA AHCI mode SSID
+ */
+ unsigned int OhciSsid; /**< OhciSsid
+ * @par
+ * OHCI Controller SSID
+ */
+ unsigned int EhciSsid; /**< EhciSsid
+ * @par
+ * EHCI Controller SSID
+ */
+ unsigned int Ohci4Ssid; /**< Ohci4Ssid
+ * @par
+ * OHCI4 Controller SSID (Force USB 1.1 mode)
+ */
+ unsigned int SmbusSsid; /**< SmbusSsid
+ * @par
+ * SMBUS controller SSID
+ */
+ unsigned int IdeSsid; /**< IdeSsid
+ * @par
+ * IDE (Sata) controller SSID
+ */
+ unsigned int AzaliaSsid; /**< AzaliaSsid
+ * @par
+ * HD Audio controller SSID
+ */
+ unsigned int LpcSsid; /**< LpcSsid
+ * @par
+ * LPC controller SSID
+ */
+ unsigned int PCIBSsid; /**< PCIBSsid
+ * @par
+ * PCIB controller SSID
+ */
+} BUILDPARAM;
+
+/**
+ * The EC fan MSGREG struct for CIMx Module. *
+ */
+typedef struct _EC_struct {
+ unsigned char MSGFun81zone0MSGREG0; ///<Thermal zone
+ unsigned char MSGFun81zone0MSGREG1; ///<Thermal zone
+ unsigned char MSGFun81zone0MSGREG2; ///<Thermal zone control byte 1
+ unsigned char MSGFun81zone0MSGREG3; ///<Thermal zone control byte 2
+ unsigned char MSGFun81zone0MSGREG4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
+ unsigned char MSGFun81zone0MSGREG5; ///<Hysteresis inforamtion
+ unsigned char MSGFun81zone0MSGREG6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
+ unsigned char MSGFun81zone0MSGREG7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
+ unsigned char MSGFun81zone0MSGREG8; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
+ unsigned char MSGFun81zone0MSGREG9; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
+
+ //EC LDN9 funtion 81 zone 1
+ unsigned char MSGFun81zone1MSGREG0; ///<Thermal zone
+ unsigned char MSGFun81zone1MSGREG1; ///<Thermal zone
+ unsigned char MSGFun81zone1MSGREG2; ///<Thermal zone control byte 1
+ unsigned char MSGFun81zone1MSGREG3; ///<Thermal zone control byte 2
+ unsigned char MSGFun81zone1MSGREG4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
+ unsigned char MSGFun81zone1MSGREG5; ///<Hysteresis inforamtion
+ unsigned char MSGFun81zone1MSGREG6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
+ unsigned char MSGFun81zone1MSGREG7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
+ unsigned char MSGFun81zone1MSGREG8; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
+ unsigned char MSGFun81zone1MSGREG9; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
+
+ //EC LDN9 funtion 81 zone 2
+ unsigned char MSGFun81zone2MSGREG0; ///<Thermal zone
+ unsigned char MSGFun81zone2MSGREG1; ///<Thermal zone
+ unsigned char MSGFun81zone2MSGREG2; ///<Thermal zone control byte 1
+ unsigned char MSGFun81zone2MSGREG3; ///<Thermal zone control byte 2
+ unsigned char MSGFun81zone2MSGREG4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
+ unsigned char MSGFun81zone2MSGREG5; ///<Hysteresis inforamtion
+ unsigned char MSGFun81zone2MSGREG6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
+ unsigned char MSGFun81zone2MSGREG7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
+ unsigned char MSGFun81zone2MSGREG8; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
+ unsigned char MSGFun81zone2MSGREG9; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
+
+ //EC LDN9 funtion 81 zone 3
+ unsigned char MSGFun81zone3MSGREG0; ///<Thermal zone
+ unsigned char MSGFun81zone3MSGREG1; ///<Thermal zone
+ unsigned char MSGFun81zone3MSGREG2; ///<Thermal zone control byte 1
+ unsigned char MSGFun81zone3MSGREG3; ///<Thermal zone control byte 2
+ unsigned char MSGFun81zone3MSGREG4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
+ unsigned char MSGFun81zone3MSGREG5; ///<Hysteresis inforamtion
+ unsigned char MSGFun81zone3MSGREG6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
+ unsigned char MSGFun81zone3MSGREG7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
+ unsigned char MSGFun81zone3MSGREG8; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
+ unsigned char MSGFun81zone3MSGREG9; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
+
+ //EC LDN9 funtion 83 zone 0
+ unsigned char MSGFun83zone0MSGREG0; ///<Thermal zone
+ unsigned char MSGFun83zone0MSGREG1; ///<Thermal zone
+ unsigned char MSGFun83zone0MSGREG2; ///<_AC0
+ unsigned char MSGFun83zone0MSGREG3; ///<_AC1
+ unsigned char MSGFun83zone0MSGREG4; ///<_AC2
+ unsigned char MSGFun83zone0MSGREG5; ///<_AC3
+ unsigned char MSGFun83zone0MSGREG6; ///<_AC4
+ unsigned char MSGFun83zone0MSGREG7; ///<_AC5
+ unsigned char MSGFun83zone0MSGREG8; ///<_AC6
+ unsigned char MSGFun83zone0MSGREG9; ///<_AC7
+ unsigned char MSGFun83zone0MSGREGA; ///<_CRT
+ unsigned char MSGFun83zone0MSGREGB; ///<_PSV
+
+ //EC LDN9 funtion 83 zone 1
+ unsigned char MSGFun83zone1MSGREG0; ///<Thermal zone
+ unsigned char MSGFun83zone1MSGREG1; ///<Thermal zone
+ unsigned char MSGFun83zone1MSGREG2; ///<_AC0
+ unsigned char MSGFun83zone1MSGREG3; ///<_AC1
+ unsigned char MSGFun83zone1MSGREG4; ///<_AC2
+ unsigned char MSGFun83zone1MSGREG5; ///<_AC3
+ unsigned char MSGFun83zone1MSGREG6; ///<_AC4
+ unsigned char MSGFun83zone1MSGREG7; ///<_AC5
+ unsigned char MSGFun83zone1MSGREG8; ///<_AC6
+ unsigned char MSGFun83zone1MSGREG9; ///<_AC7
+ unsigned char MSGFun83zone1MSGREGA; ///<_CRT
+ unsigned char MSGFun83zone1MSGREGB; ///<_PSV
+
+ //EC LDN9 funtion 83 zone 2
+ unsigned char MSGFun83zone2MSGREG0; ///<Thermal zone
+ unsigned char MSGFun83zone2MSGREG1; ///<Thermal zone
+ unsigned char MSGFun83zone2MSGREG2; ///<_AC0
+ unsigned char MSGFun83zone2MSGREG3; ///<_AC1
+ unsigned char MSGFun83zone2MSGREG4; ///<_AC2
+ unsigned char MSGFun83zone2MSGREG5; ///<_AC3
+ unsigned char MSGFun83zone2MSGREG6; ///<_AC4
+ unsigned char MSGFun83zone2MSGREG7; ///<_AC5
+ unsigned char MSGFun83zone2MSGREG8; ///<_AC6
+ unsigned char MSGFun83zone2MSGREG9; ///<_AC7
+ unsigned char MSGFun83zone2MSGREGA; ///<_CRT
+ unsigned char MSGFun83zone2MSGREGB; ///<_PSV
+
+ //EC LDN9 funtion 83 zone 3
+ unsigned char MSGFun83zone3MSGREG0; ///<Thermal zone
+ unsigned char MSGFun83zone3MSGREG1; ///<Thermal zone
+ unsigned char MSGFun83zone3MSGREG2; ///<_AC0
+ unsigned char MSGFun83zone3MSGREG3; ///<_AC1
+ unsigned char MSGFun83zone3MSGREG4; ///<_AC2
+ unsigned char MSGFun83zone3MSGREG5; ///<_AC3
+ unsigned char MSGFun83zone3MSGREG6; ///<_AC4
+ unsigned char MSGFun83zone3MSGREG7; ///<_AC5
+ unsigned char MSGFun83zone3MSGREG8; ///<_AC6
+ unsigned char MSGFun83zone3MSGREG9; ///<_AC7
+ unsigned char MSGFun83zone3MSGREGA; ///<_CRT
+ unsigned char MSGFun83zone3MSGREGB; ///<_PSV
+
+ //EC LDN9 funtion 85 zone 0
+ unsigned char MSGFun85zone0MSGREG0; ///<Thermal zone
+ unsigned char MSGFun85zone0MSGREG1; ///<Thermal zone
+ unsigned char MSGFun85zone0MSGREG2; ///<AL0 PWM level in percentage (0 - 100%)
+ unsigned char MSGFun85zone0MSGREG3; ///<AL1 PWM level in percentage (0 - 100%)
+ unsigned char MSGFun85zone0MSGREG4; ///<AL2 PWM level in percentage (0 - 100%)
+ unsigned char MSGFun85zone0MSGREG5; ///<AL3 PWM level in percentage (0 - 100%)
+ unsigned char MSGFun85zone0MSGREG6; ///<AL4 PWM level in percentage (0 - 100%)
+ unsigned char MSGFun85zone0MSGREG7; ///<AL5 PWM level in percentage (0 - 100%)
+ unsigned char MSGFun85zone0MSGREG8; ///<AL6 PWM level in percentage (0 - 100%)
+ unsigned char MSGFun85zone0MSGREG9; ///<AL7 PWM level in percentage (0 - 100%)
+
+ //EC LDN9 funtion 85 zone 1
+ unsigned char MSGFun85zone1MSGREG0; ///<Thermal zone
+ unsigned char MSGFun85zone1MSGREG1; ///<Thermal zone
+ unsigned char MSGFun85zone1MSGREG2; ///<AL0 PWM level in percentage (0 - 100%)
+ unsigned char MSGFun85zone1MSGREG3; ///<AL1 PWM level in percentage (0 - 100%)
+ unsigned char MSGFun85zone1MSGREG4; ///<AL2 PWM level in percentage (0 - 100%)
+ unsigned char MSGFun85zone1MSGREG5; ///<AL3 PWM level in percentage (0 - 100%)
+ unsigned char MSGFun85zone1MSGREG6; ///<AL4 PWM level in percentage (0 - 100%)
+ unsigned char MSGFun85zone1MSGREG7; ///<AL5 PWM level in percentage (0 - 100%)
+ unsigned char MSGFun85zone1MSGREG8; ///<AL6 PWM level in percentage (0 - 100%)
+ unsigned char MSGFun85zone1MSGREG9; ///<AL7 PWM level in percentage (0 - 100%)
+
+ //EC LDN9 funtion 85 zone 2
+ unsigned char MSGFun85zone2MSGREG0; ///<Thermal zone
+ unsigned char MSGFun85zone2MSGREG1; ///<Thermal zone
+ unsigned char MSGFun85zone2MSGREG2; ///<AL0 PWM level in percentage (0 - 100%)
+ unsigned char MSGFun85zone2MSGREG3; ///<AL1 PWM level in percentage (0 - 100%)
+ unsigned char MSGFun85zone2MSGREG4; ///<AL2 PWM level in percentage (0 - 100%)
+ unsigned char MSGFun85zone2MSGREG5; ///<AL3 PWM level in percentage (0 - 100%)
+ unsigned char MSGFun85zone2MSGREG6; ///<AL4 PWM level in percentage (0 - 100%)
+ unsigned char MSGFun85zone2MSGREG7; ///<AL5 PWM level in percentage (0 - 100%)
+ unsigned char MSGFun85zone2MSGREG8; ///<AL6 PWM level in percentage (0 - 100%)
+ unsigned char MSGFun85zone2MSGREG9; ///<AL7 PWM level in percentage (0 - 100%)
+
+ //EC LDN9 funtion 85 zone 3
+ unsigned char MSGFun85zone3MSGREG0; ///<Thermal zone
+ unsigned char MSGFun85zone3MSGREG1; ///<Thermal zone
+ unsigned char MSGFun85zone3MSGREG2; ///<AL0 PWM level in percentage (0 - 100%)
+ unsigned char MSGFun85zone3MSGREG3; ///<AL1 PWM level in percentage (0 - 100%)
+ unsigned char MSGFun85zone3MSGREG4; ///<AL2 PWM level in percentage (0 - 100%)
+ unsigned char MSGFun85zone3MSGREG5; ///<AL3 PWM level in percentage (0 - 100%)
+ unsigned char MSGFun85zone3MSGREG6; ///<AL4 PWM level in percentage (0 - 100%)
+ unsigned char MSGFun85zone3MSGREG7; ///<AL5 PWM level in percentage (0 - 100%)
+ unsigned char MSGFun85zone3MSGREG8; ///<AL6 PWM level in percentage (0 - 100%)
+ unsigned char MSGFun85zone3MSGREG9; ///<AL7 PWM level in percentage (0 - 100%)
+
+ //EC LDN9 funtion 89 TEMPIN channel 0
+ unsigned char MSGFun89zone0MSGREG0; ///<Thermal zone
+ unsigned char MSGFun89zone0MSGREG1; ///<Thermal zone
+ unsigned char MSGFun89zone0MSGREG2; ///<At DWORD bit 0-7
+ unsigned char MSGFun89zone0MSGREG3; ///<At DWORD bit 15-8
+ unsigned char MSGFun89zone0MSGREG4; ///<At DWORD bit 23-16
+ unsigned char MSGFun89zone0MSGREG5; ///<At DWORD bit 31-24
+ unsigned char MSGFun89zone0MSGREG6; ///<Ct DWORD bit 0-7
+ unsigned char MSGFun89zone0MSGREG7; ///<Ct DWORD bit 15-8
+ unsigned char MSGFun89zone0MSGREG8; ///<Ct DWORD bit 23-16
+ unsigned char MSGFun89zone0MSGREG9; ///<Ct DWORD bit 31-24
+ unsigned char MSGFun89zone0MSGREGA; ///<Mode bit 0-7
+
+ //EC LDN9 funtion 89 TEMPIN channel 1
+ unsigned char MSGFun89zone1MSGREG0; ///<Thermal zone
+ unsigned char MSGFun89zone1MSGREG1; ///<Thermal zone
+ unsigned char MSGFun89zone1MSGREG2; ///<At DWORD bit 0-7
+ unsigned char MSGFun89zone1MSGREG3; ///<At DWORD bit 15-8
+ unsigned char MSGFun89zone1MSGREG4; ///<At DWORD bit 23-16
+ unsigned char MSGFun89zone1MSGREG5; ///<At DWORD bit 31-24
+ unsigned char MSGFun89zone1MSGREG6; ///<Ct DWORD bit 0-7
+ unsigned char MSGFun89zone1MSGREG7; ///<Ct DWORD bit 15-8
+ unsigned char MSGFun89zone1MSGREG8; ///<Ct DWORD bit 23-16
+ unsigned char MSGFun89zone1MSGREG9; ///<Ct DWORD bit 31-24
+ unsigned char MSGFun89zone1MSGREGA; ///<Mode bit 0-7
+
+ //EC LDN9 funtion 89 TEMPIN channel 2
+ unsigned char MSGFun89zone2MSGREG0; ///<Thermal zone
+ unsigned char MSGFun89zone2MSGREG1; ///<Thermal zone
+ unsigned char MSGFun89zone2MSGREG2; ///<At DWORD bit 0-7
+ unsigned char MSGFun89zone2MSGREG3; ///<At DWORD bit 15-8
+ unsigned char MSGFun89zone2MSGREG4; ///<At DWORD bit 23-16
+ unsigned char MSGFun89zone2MSGREG5; ///<At DWORD bit 31-24
+ unsigned char MSGFun89zone2MSGREG6; ///<Ct DWORD bit 0-7
+ unsigned char MSGFun89zone2MSGREG7; ///<Ct DWORD bit 15-8
+ unsigned char MSGFun89zone2MSGREG8; ///<Ct DWORD bit 23-16
+ unsigned char MSGFun89zone2MSGREG9; ///<Ct DWORD bit 31-24
+ unsigned char MSGFun89zone2MSGREGA; ///<Mode bit 0-7
+
+ //EC LDN9 funtion 89 TEMPIN channel 3
+ unsigned char MSGFun89zone3MSGREG0; ///<Thermal zone
+ unsigned char MSGFun89zone3MSGREG1; ///<Thermal zone
+ unsigned char MSGFun89zone3MSGREG2; ///<At DWORD bit 0-7
+ unsigned char MSGFun89zone3MSGREG3; ///<At DWORD bit 15-8
+ unsigned char MSGFun89zone3MSGREG4; ///<At DWORD bit 23-16
+ unsigned char MSGFun89zone3MSGREG5; ///<At DWORD bit 31-24
+ unsigned char MSGFun89zone3MSGREG6; ///<Ct DWORD bit 0-7
+ unsigned char MSGFun89zone3MSGREG7; ///<Ct DWORD bit 15-8
+ unsigned char MSGFun89zone3MSGREG8; ///<Ct DWORD bit 23-16
+ unsigned char MSGFun89zone3MSGREG9; ///<Ct DWORD bit 31-24
+ unsigned char MSGFun89zone3MSGREGA; ///<Mode bit 0-7
+
+ // FLAG for Fun83/85/89 support
+ unsigned short IMCFUNSupportBitMap; /// Bit0=81FunZone0 support(1=On;0=Off); bit1-3=81FunZone1-Zone3;Bit4-7=83FunZone0-Zone3;Bit8-11=85FunZone0-Zone3;Bit11-15=89FunZone0-Zone3;
+} EC_struct;
+/** SBGPPPORTCONFIG - Southbridge GPP port config structure */
+typedef struct {
+ unsigned int PortPresent:1; /**< Port connection
+ * @par
+ * @li <b>0</b> - Port doesn't have slot. No need to train the link
+ * @li <b>1</b> - Port connection defined and needs to be trained
+ */
+ unsigned int PortDetected:1; /**< Link training status
+ * @par
+ * @li <b>0</b> - EP not detected
+ * @li <b>1</b> - EP detected
+ */
+ unsigned int PortIsGen2:2; /**< Port link speed configuration
+ * @par
+ * @li <b>00</b> - Auto
+ * @li <b>01</b> - Forced GEN1
+ * @li <b>10</b> - Forced GEN2
+ * @li <b>11</b> - Reserved
+ */
+
+ unsigned int PortHotPlug:1; /**< Support hot plug?
+ * @par
+ * @li <b>0</b> - No support
+ * @li <b>1</b> - support
+ */
+/** PortMisc - Reserved */
+ unsigned int PortMisc:27;
+} SBGPPPORTCONFIG;
+
+/** CODECENTRY - Southbridge HD Audio OEM Codec structure */
+typedef struct _CODECENTRY {
+/** Nid - Reserved ?? */
+ unsigned char Nid;
+/** Byte40 - Reserved ?? */
+ unsigned int Byte40;
+} CODECENTRY;
+
+/** CODECTBLLIST - Southbridge HD Audio Codec table list */
+typedef struct _CODECTBLLIST {
+/** CodecID - Codec ID */
+ unsigned int CodecID;
+/** CodecTablePtr - Codec table pointer */
+ CODECENTRY* CodecTablePtr;
+} CODECTBLLIST;
+
+/** Sata Controller structure */
+typedef struct _SATAST {
+ unsigned char SataController:1; /**< SataController
+ * @par
+ * Sata Controller
+ * @li <b>0</b> - disable
+ * @li <b>1</b> - enable
+ */
+ unsigned char SataIdeCombMdPriSecOpt:1; /**< SataIdeCombMdPriSecOpt - Reserved */
+ unsigned char SataSetMaxGen2:1; /**< SataSetMaxGen2
+ * @par
+ * Sata Controller Set to Max Gen2 mode
+ * @li <b>0</b> - disable
+ * @li <b>1</b> - enable
+ */
+ unsigned char SataIdeCombinedMode:1; /**< SataIdeCombinedMode
+ * @par
+ * Sata IDE Controller set to Combined Mode
+ * @li <b>0</b> - enable
+ * @li <b>1</b> - disable
+ */
+/** SATARefClkSel - Reserved */
+ unsigned char SATARefClkSel:2; // 4:5
+/** SATARefDivSel - Reserved */
+ unsigned char SATARefDivSel:2; // 6:7
+} SATAST;
+
+/** _USBST Controller structure
+ *
+ * Usb Ohci1 Contoller is define at BIT0
+ * - 0:disable 1:enable
+ * (Bus 0 Dev 18 Func0) *
+ * Usb Ehci1 Contoller is define at BIT1
+ * - 0:disable 1:enable
+ * (Bus 0 Dev 18 Func2) *
+ * Usb Ohci2 Contoller is define at BIT2
+ * - 0:disable 1:enable
+ * (Bus 0 Dev 19 Func0) *
+ * Usb Ehci2 Contoller is define at BIT3
+ * - 0:disable 1:enable
+ * (Bus 0 Dev 19 Func2) *
+ * Usb Ohci3 Contoller is define at BIT4
+ * - 0:disable 1:enable
+ * (Bus 0 Dev 22 Func0) *
+ * Usb Ehci3 Contoller is define at BIT5
+ * - 0:disable 1:enable
+ * (Bus 0 Dev 22 Func2) *
+ * Usb Ohci4 Contoller is define at BIT6
+ * - 0:disable 1:enable
+ * (Bus 0 Dev 20 Func5) *
+ */
+typedef struct _USBST {
+ unsigned char Ohci1:1; ///< Ohci0 controller - 0:disable, 1:enable
+ unsigned char Ehci1:1; ///< Ehci1 controller - 0:disable, 1:enable
+ unsigned char Ohci2:1; ///< Ohci2 controller - 0:disable, 1:enable
+ unsigned char Ehci2:1; ///< Ehci2 controller - 0:disable, 1:enable
+ unsigned char Ohci3:1; ///< Ohci3 controller - 0:disable, 1:enable
+ unsigned char Ehci3:1; ///< Ehci3 controller - 0:disable, 1:enable
+ unsigned char Ohci4:1; ///< Ohci4 controller - 0:disable, 1:enable
+ unsigned char UTemp:1; ///< Reserved
+} USBST;
+
+/**
+ * _AZALIAPIN - HID Azalia or GPIO define structure.
+ *
+ */
+typedef struct _AZALIAPIN {
+ unsigned char AzaliaSdin0:2; /**< AzaliaSdin0
+ * @par
+ * SDIN0 is define at BIT0 & BIT1
+ * @li <b>00</b> - GPIO PIN
+ * @li <b>10</b> - As a Azalia SDIN pin
+ */
+ unsigned char AzaliaSdin1:2; /**< AzaliaSdin1
+ * @par
+ * SDIN0 is define at BIT2 & BIT3
+ * @li <b>00</b> - GPIO PIN
+ * @li <b>10</b> - As a Azalia SDIN pin
+ */
+ unsigned char AzaliaSdin2:2; /**< AzaliaSdin2
+ * @par
+ * SDIN0 is define at BIT4 & BIT5
+ * @li <b>00</b> - GPIO PIN
+ * @li <b>10</b> - As a Azalia SDIN pin
+ */
+ unsigned char AzaliaSdin3:2; /**< AzaliaSdin3
+ * @par
+ * SDIN0 is define at BIT6 & BIT7
+ * @li <b>00</b> - GPIO PIN
+ * @li <b>10</b> - As a Azalia SDIN pin
+ */
+} AZALIAPIN;
+
+/** AMDSBCFG - Southbridge CIMx configuration structure (Main) */
+typedef struct _AMDSBCFG {
+/** StdHeader - Standard header for all AGESA/CIMx services. */
+ AMD_CONFIG_PARAMS StdHeader;
+
+/** BuildParameters - The STATIC platform information for CIMx Module. */
+ BUILDPARAM BuildParameters;
+ //offset 90 bytes (32-121)
+ //MsgXchgBiosCimx //offset 4 bytes (122-125)
+ // SATA Configuration
+
+ union /**< union - Reserved */
+ { /**< SATAMODE - Sata Controller structure */
+/** SataModeReg - Reserved */
+ unsigned char SataModeReg;
+/** SataMode - Reserved */
+ SATAST SataMode;
+ } SATAMODE;
+/** S3Resume - Flag of ACPI S3 Resume. */
+ unsigned char S3Resume:1; // 8
+/** RebootRequired - Flag of Reboot system is required. */
+ unsigned char RebootRequired:1; // 9
+/** SbSpiSpeedSupport - Reserved */
+ unsigned char SbSpiSpeedSupport:1; // 10
+/**< SpreadSpectrum
+ * @par
+ * Spread Spectrum function
+ * @li <b>0</b> - disable
+ * @li <b>1</b> - enable
+ */
+ unsigned char SpreadSpectrum:1; // 11
+/** NbSbGen2 - Reserved */
+ unsigned char NbSbGen2:1; // 12
+ unsigned char GppGen2:1; // 13
+ unsigned char GppMemWrImprove:1; // 14
+/** MsgXchgBiosCimxReserved - Reserved */
+ unsigned char MsgXchgBiosCimxReserved:1; // 15 (BB USED)
+/**< SataClass - SATA Controller mode [16:18]
+ * @par
+ * @li <b>000</b> - Native IDE mode
+ * @li <b>001</b> - RAID mode
+ * @li <b>010</b> - AHCI mode
+ * @li <b>011</b> - Legacy IDE mode
+ * @li <b>100</b> - IDE->AHCI mode
+ * @li <b>101</b> - AHCI mode as 4394 ID (AMD driver)
+ * @li <b>110</b> - IDE->AHCI mode as 4394 ID (AMD driver)
+ */
+ unsigned short SataClass:3; // 16:18
+/**< Sata IDE Controller mode
+ * @par
+ * @li <b>0</b> - Legacy IDE mode
+ * @li <b>1</b> - Native IDE mode
+ */
+ unsigned short SataIdeMode:1; // 19
+/**< SataEspPort - SATA port is external accessible on a signal only connector (eSATA:)
+ * @par
+ * @li <b> BIT0 </b> - PORT0 set as ESP port
+ * @li <b> BIT1 </b> - PORT1 set as ESP port
+ * @li <b> BIT2 </b> - PORT2 set as ESP port
+ * @li <b> BIT3 </b> - PORT3 set as ESP port
+ * @li <b> BIT4 </b> - PORT4 set as ESP port
+ * @li <b> BIT5 </b> - PORT5 set as ESP port
+ */
+ unsigned short SataEspPort:6; // 20:25
+/** SataPortPower - Reserved */
+ unsigned short SataPortPower:6; // 31:26
+
+ // SATA Debug Option //offset 4 bytes (126-129)
+
+/**< SataPortMode - Force Each PORT to GEN1/GEN2 mode
+ * @par
+ * @li <b> 0 </b> Auto for each PORTs
+ * @li <b> BIT0 = 1</b> - PORT0 set to GEN1
+ * @li <b> BIT1 = 1</b> - PORT0 set to GEN2
+ * @li <b> BIT2 = 1</b> - PORT1 set to GEN1
+ * @li <b> BIT3 = 1</b> - PORT1 set to GEN2
+ * @li <b> BIT4 = 1</b> - PORT2 set to GEN1
+ * @li <b> BIT5 = 1</b> - PORT2 set to GEN2
+ * @li <b> BIT6 = 1</b> - PORT3 set to GEN1
+ * @li <b> BIT7 = 1</b> - PORT3 set to GEN2
+ * @li <b> BIT8 = 1</b> - PORT4 set to GEN1
+ * @li <b> BIT9 = 1</b> - PORT4 set to GEN2
+ * @li <b> BIT10 = 1</b> - PORT5 set to GEN1
+ * @li <b> BIT11 = 1</b> - PORT5 set to GEN2
+ */
+ unsigned int SataPortMode:12; //11:0
+/** SATAClkSelOpt - Reserved */
+ unsigned int SATAClkSelOpt:4; // Removed from coding side
+/** SataAggrLinkPmCap - Reserved */
+ unsigned int SataAggrLinkPmCap:1; //16, 0:OFF 1:ON
+/** SataPortMultCap - Reserved */
+ unsigned int SataPortMultCap:1; //17, 0:OFF 1:ON
+/** SataClkAutoOff - Reserved */
+ unsigned int SataClkAutoOff:1; //18, AutoClockOff 0:Disabled, 1:Enabled
+/** SataPscCap - Reserved */
+ unsigned int SataPscCap:1; //19, 0:Enable PSC capability, 1:Disable PSC capability
+/** BIOSOSHandoff - Reserved */
+ unsigned int BIOSOSHandoff:1; //20
+/** SataFisBasedSwitching - Reserved */
+ unsigned int SataFisBasedSwitching:1; //21
+/** SataCccSupport - Reserved */
+ unsigned int SataCccSupport:1; //22
+/** SataSscCap - Reserved */
+ unsigned int SataSscCap:1; //23, 0:Enable SSC capability, 1:Disable SSC capability
+/** SataMsiCapability - Reserved */
+ unsigned int SataMsiCapability:1; //24 0:Hidden 1:Visible. This feature is disabled per RPR, but remains the interface.
+/** SataForceRaid - Reserved */
+ unsigned int SataForceRaid:1; //25 0:No function 1:Force RAID
+/** SataDebugDummy - Reserved */
+ unsigned int SataDebugDummy:6; //31:26
+//
+// USB Configuration //offset 4 bytes (130-133)
+//
+
+/** USBDeviceConfig - USB Controller Configuration
+ *
+ * - Usb Ohci1 Contoller is define at BIT0
+ * - 0:disable 1:enable
+ * (Bus 0 Dev 18 Func0) *
+ * - Usb Ehci1 Contoller is define at BIT1
+ * - 0:disable 1:enable
+ * (Bus 0 Dev 18 Func2) *
+ * - Usb Ohci2 Contoller is define at BIT2
+ * - 0:disable 1:enable
+ * (Bus 0 Dev 19 Func0) *
+ * - Usb Ehci2 Contoller is define at BIT3
+ * - 0:disable 1:enable
+ * (Bus 0 Dev 19 Func2) *
+ * - Usb Ohci3 Contoller is define at BIT4
+ * - 0:disable 1:enable
+ * (Bus 0 Dev 22 Func0) *
+ * - Usb Ehci3 Contoller is define at BIT5
+ * - 0:disable 1:enable
+ * (Bus 0 Dev 22 Func2) *
+ * - Usb Ohci4 Contoller is define at BIT6
+ * - 0:disable 1:enable
+ * (Bus 0 Dev 20 Func5) *
+ */
+ union /**< union - Reserved */
+ { /**< USBMODE - USB Controller structure */
+/** SataModeReg - Reserved */
+ unsigned char UsbModeReg;
+/** SataMode - Reserved */
+ USBST UsbMode;
+ } USBMODE;
+/*!
+ */
+
+/**< GecConfig
+ * @par
+ * InChip Gbit NIC
+ * @li <b>1</b> - disable
+ * @li <b>0</b> - enable
+ */
+ unsigned char GecConfig:1; //8
+
+/**< IrConfig
+ * @par
+ * Ir Controller setting
+ * @li <b>00 </b> - disable
+ * @li <b>01 </b> - Rx and Tx0
+ * @li <b>10 </b> - Rx and Tx1
+ * @li <b>11 </b> - Rx and both Tx0,Tx1
+ */
+ unsigned char IrConfig:2; //9:10
+
+/** GecDummy - Reserved */
+ unsigned char GecDummy:5; //15:11
+
+ //Azalia Configuration
+
+/**< AzaliaController - Azalia Controller Configuration
+ * @par
+ * Azalia Controller [0-1]
+ * @li <b>0</b> - Auto : Detect Azalia controller automatically.
+ * @li <b>1</b> - Diable : Disable Azalia controller.
+ * @li <b>2</b> - Enable : Enable Azalia controller.
+ */
+ unsigned char AzaliaController:2; //17:16
+/**< AzaliaPinCfg - Azalia Controller SDIN pin Configuration
+ * @par
+ * @li <b>0</b> - disable
+ * @li <b>1</b> - enable
+ */
+ unsigned char AzaliaPinCfg:1; //18
+/**< AzaliaFrontPanel - Azalia Controller Front Panel Configuration
+ * @par
+ * Support Front Panel configuration
+ * @li <b>0</b> - Auto
+ * @li <b>1</b> - disable
+ * @li <b>2</b> - enable
+ */
+ unsigned char AzaliaFrontPanel:2; //20:19
+/**< FrontPanelDetected - Force Azalia Controller Front Panel Configuration
+ * @par
+ * Force Front Panel configuration
+ * @li <b>0</b> - Not Detected
+ * @li <b>1</b> - Detected
+ */
+ unsigned char FrontPanelDetected:1; //21
+/**< AzaliaSnoop - Azalia Controller Snoop feature Configuration
+ * @par
+ * Azalia Controller Snoop feature Configuration
+ * @li <b>0</b> - disable
+ * @li <b>1</b> - enable
+ */
+ unsigned char AzaliaSnoop:1; //22
+/** AzaliaDummy - Reserved */
+ unsigned char AzaliaDummy:1; //23
+
+ union
+ {
+/**< AzaliaSdinPin - Azalia Controller SDIN pin Configuration
+ *
+ * SDIN0 is define at BIT0 & BIT1
+ * - 00: GPIO PIN
+ * - 01: Reserved
+ * - 10: As a Azalia SDIN pin
+ *
+ * SDIN1 is define at BIT2 & BIT3
+ * * Config same as SDIN0
+ * SDIN2 is define at BIT4 & BIT5
+ * * Config same as SDIN0
+ * SDIN3 is define at BIT6 & BIT7
+ * * Config same as SDIN0
+ */
+ unsigned char AzaliaSdinPin;
+ AZALIAPIN AzaliaConfig;
+ } AZALIACONFIG;
+
+/** AZOEMTBL - Azalia Controller OEM Codec Table Pointer
+ *
+ */
+ union
+ {
+ PLACEHOLDER PlaceHolder;
+ CODECTBLLIST* pAzaliaOemCodecTablePtr; //offset 4 bytes (134-137)
+ } AZOEMTBL;
+
+/** AZOEMFPTBL - Azalia Controller Front Panel OEM Table Pointer
+ *
+ */
+ union
+ {
+ PLACEHOLDER PlaceHolder;
+ void* pAzaliaOemFpCodecTablePtr; //offset 4 bytes (138-141)
+ } AZOEMFPTBL;
+
+ //Miscellaneous Configuration //offset 4 bytes (142-145)
+/** AnyHT200MhzLink - Reserved */
+ unsigned int AnyHT200MhzLink:1; //0
+/**< HpetTimer - South Bridge Hpet Timer Configuration
+ * @par
+ * @li <b>0</b> - disable
+ * @li <b>1</b> - enable
+ */
+ unsigned int HpetTimer:1; //1
+/**< PciClks - PCI Slot Clock Control
+ * @par
+ * PCI SLOT 0 define at BIT0
+ * - 00: disable
+ * - 01: enable
+ *
+ * PCI SLOT 1 define at BIT1
+ * * Config same as PCI SLOT0
+ * PCI SLOT 2 define at BIT2
+ * * Config same as PCI SLOT0
+ * PCI SLOT 3 define at BIT3
+ * * Config same as PCI SLOT0
+ * PCI SLOT 4 define at BIT4
+ * * Config same as PCI SLOT0
+ */
+ unsigned int PciClks:5; //2:6
+/** MiscReserved1 - Reserved */
+ unsigned int MiscReserved1:4; //9:7, Reserved
+/** MobilePowerSavings - Debug function Reserved */
+ unsigned int MobilePowerSavings:1; //11, 0:Disable, 1:Enable Power saving features especially for Mobile platform
+/** MiscDummy1 - Debug function Reserved */
+ unsigned int MiscDummy1:1;
+/** NativePcieSupport - Debug function Reserved */
+ unsigned int NativePcieSupport:1; //13, 0:Enable, 1:Disabled
+/** FlashPinConfig - Debug function Reserved */
+ unsigned int FlashPinConfig:1; //14, 0:desktop mode 1:mobile mode
+/** UsbPhyPowerDown - Debug function Reserved */
+ unsigned int UsbPhyPowerDown:1; //15
+/** PcibClkStopOverride - Debug function Reserved */
+ unsigned int PcibClkStopOverride:10; //25:16
+/**< HpetMsiDis - South Bridge HPET MSI Configuration
+ * @par
+ * @li <b>1</b> - disable
+ * @li <b>0</b> - enable
+ */
+ unsigned int HpetMsiDis:1; //26
+/**< ResetCpuOnSyncFlood - Rest CPU on Sync Flood
+ * @par
+ * @li <b>0</b> - disable
+ * @li <b>1</b> - enable
+ */
+ unsigned int ResetCpuOnSyncFlood:1; //27
+/**< LdtStpDisable - LdtStp# output disable
+ * @par
+ * @li <b>0</b> - LdtStp# output enable
+ * @li <b>1</b> - LdtStp# output disable
+ */
+ unsigned int LdtStpDisable:1; //28
+/**< MTC1e - Message Triggered C1e
+ * @par
+ * @li <b>0</b> - disable
+ * @li <b>1</b> - enable
+ */
+ unsigned int MTC1e:1; //29
+/** MiscDummy - Reserved */
+ unsigned int MiscDummy:2; //31:30
+ unsigned int SioHwmPortEnable:1; // Enable SuperIO HWM access via LPC
+
+ //DebugOptions //offset 4 bytes (146-149)
+/** PcibAutoClkCtrlLow - Debug function Reserved */
+ unsigned int PcibAutoClkCtrlLow:16;
+/** PcibAutoClkCtrlHigh - Debug function Reserved */
+ unsigned int PcibAutoClkCtrlHigh:16;
+
+/**< OEMPROGTBL - ACPI MMIO register setting table OEM override
+ * @par
+ * OEM table for customer override ACPI MMIO register in their code.
+ */
+ union
+ {
+ PLACEHOLDER OemProgrammingTablePtr; //offset 4 bytes (150-153)
+ void *OemProgrammingTablePtr_Ptr;
+ } OEMPROGTBL;
+
+ //Gpp Configuration //offset 24 bytes total (154-177)
+ union {
+ unsigned int PORTCFG32;
+ SBGPPPORTCONFIG PortCfg;
+ } PORTCONFIG[MAX_GPP_PORTS]; //offset 16 bytes
+
+ unsigned int GppLinkConfig; // GPP_LINK_CONFIG = PCIE_GPP_Enable[3:0]
+ // 0000 - Port ABCD -> 4:0:0:0
+ // 0001 - N/A
+ // 0010 - Port ABCD -> 2:2:0:0
+ // 0011 - Port ABCD -> 2:1:1:0
+ // 0100 - Port ABCD -> 1:1:1:1
+ //
+ unsigned int GppFoundGfxDev:4; //3:0 If port A-D (mapped to bit [3:0]) has GFX EP detected
+ unsigned int CoreGen2Enable:1; //4
+ unsigned int GppFunctionEnable:1; //5
+ unsigned int GppUnhidePorts:1; //6
+ unsigned int AlinkPhyPllPowerDown:1; //7
+ unsigned int GppConfigDummy1:2; //9:8
+ unsigned int GppLaneReversal:1; //10
+ unsigned int GppPhyPllPowerDown:1; //11
+ unsigned int GppCompliance :1; //12
+ unsigned int GppPortAspm:8; //20:13 ASPM state for GPP ports, 14:13 for port0, ..., 20:19 for port3
+ // 00 - Disabled
+ // 01 - L0s
+ // 10 - L1
+ // 11 - L0s + L1
+ //
+ unsigned int GppConfigDummy:11; //31:21
+
+ //TempMMIO //offset 4 bytes (178-181)
+ unsigned int TempMMIO;
+
+ // DebugOption2
+ unsigned int GecPhyStatus:1;
+ unsigned int GecDebugOptionDummy:7;
+ unsigned int SBGecPwr:2;
+ unsigned int SBGecDebugBus:1;
+ unsigned int DebugOption2Dummy1:1;
+ unsigned int DebugOption2Dummy2:1;
+ unsigned int SbPcieOrderRule:1;
+ unsigned int SbUsbPll:1;
+ unsigned int AcDcMsg:1;
+ unsigned int TimerTickTrack:1;
+ unsigned int ClockInterruptTag:1;
+ unsigned int OhciTrafficHanding:1;
+ unsigned int EhciTrafficHanding:1;
+ unsigned int FusionMsgCMultiCore:1;
+ unsigned int FusionMsgCStage:1;
+/**< UsbRxMode - CG PLL multiplier for USB Rx 1.1 mode
+ * @par
+ * @li <b>0</b> - disable
+ * @li <b>1</b> - enable
+ */
+ unsigned int UsbRxMode:1;
+ unsigned int DebugOption2Dummy3:9; //
+
+ union
+ {
+ PLACEHOLDER DynamicGecRomAddressPtr; //offset 4 bytes (182-185)
+ void *DynamicGecRomAddress_Ptr;
+ } DYNAMICGECROM;
+ EC_struct Pecstruct;
+} AMDSBCFG;
+
+/** SMMSERVICESTRUC- Southbridge SMI service structure */
+typedef struct _SMMSERVICESTRUC {
+/** enableRegNum - Reserved */
+ unsigned char enableRegNum;
+/** enableBit - Reserved */
+ unsigned char enableBit;
+/** statusRegNum - Reserved */
+ unsigned char statusRegNum;
+/** statusBit - Reserved */
+ unsigned char statusBit;
+/** *debugMessage- Reserved */
+ signed char *debugMessage;
+/** serviceRoutine - Reserved */
+ SMM_SERVICE_ROUTINE serviceRoutine;
+} SMMSERVICESTRUC;
+
+#ifndef _NB_REG8MASK_
+
+/**
+ * - Byte Register R/W structure
+ *
+ */
+ typedef struct _Reg8Mask {
+/** bRegIndex - Reserved */
+ unsigned char bRegIndex;
+/** bANDMask - Reserved */
+ unsigned char bANDMask;
+/** bORMask - Reserved */
+ unsigned char bORMask;
+ } REG8MASK;
+#endif
+
+/**
+ * - SATA Phy setting structure
+ *
+ */
+typedef struct _SATAPHYSETTING {
+/** wPhyCoreControl - Reserved */
+ unsigned short wPhyCoreControl;
+/** dwPhyFineTune - Reserved */
+ unsigned int dwPhyFineTune;
+} SATAPHYSETTING;
+
+/**
+ * _ABTblEntry - AB link register table R/W structure
+ *
+ */
+typedef struct _ABTblEntry {
+ /** regType : AB Register Type (ABCFG, AXCFG and so on) */
+ unsigned char regType;
+ /** regIndex : AB Register Index */
+ unsigned int regIndex;
+ /** regMask : AB Register Mask */
+ unsigned int regMask;
+ /** regData : AB Register Data */
+ unsigned int regData;
+} ABTBLENTRY;
+
+/**
+ * _AcpiRegWrite - ACPI MMIO register R/W structure
+ *
+ */
+typedef struct _AcpiRegWrite {
+ /** MmioBase : Index of Soubridge block (For instence GPIO_BASE:0x01 SMI_BASE:0x02) */
+ unsigned char MmioBase;
+ /** MmioReg : Register index */
+ unsigned char MmioReg;
+ /** DataANDMask : AND Register Data */
+ unsigned char DataANDMask;
+ /** DataOrMask : Or Register Data */
+ unsigned char DataOrMask;
+} AcpiRegWrite;
+
+/**
+ * PCI_ADDRESS - PCI access structure
+ *
+ */
+#define PCI_ADDRESS(bus, dev, func, reg) \
+(unsigned int) ( (((unsigned int)bus) << 24) + (((unsigned int)dev) << 19) + (((unsigned int)func) << 16) + ((unsigned int)reg) )
+
+/**
+ * CIM_STATUS - CIMx module function return code
+ */
+typedef unsigned int CIM_STATUS;
+/**
+ * CIM_SUCCESS - Executed without error
+ */
+#define CIM_SUCCESS 0x00000000
+/**
+ * CIM_ERROR - call error
+ */
+#define CIM_ERROR 0x80000000
+/**
+ * CIM_UNSUPPORTED - function does not support
+ */
+#define CIM_UNSUPPORTED 0x80000001
+
+#pragma pack (pop)
+
+/**
+ * CIMX_OPTION_DISABLED - Define disable in module
+ */
+#define CIMX_OPTION_DISABLED 0
+/**
+ * CIMX_OPTION_ENABLED - Define enable in module
+ */
+#define CIMX_OPTION_ENABLED 1
+
+/**
+ * SATA_IDE_COMBINE_ENABLE -Define Enable Combined Mode
+ */
+#define SATA_IDE_COMBINE_ENABLE 0
+
+/**
+ * SATA_IDE_COMBINE_DISABLE -Define Disable Combined Mode
+ */
+#define SATA_IDE_COMBINE_DISABLE 1
+
+// mov al, code
+// out 80h, al
+// jmp $
+
+/**
+ * DBG_STOP - define a debug point
+ */
+#define DBG_STOP __asm _emit 0xEB __asm _emit 0xFE
+
+/**
+ * STOP_CODE - define a debug point
+ * Warning: AL gets destroyed!
+ */
+#define STOP_CODE (code) __asm __emit 0xB0 __asm __emit code __asm __emit 0xE6 \
+ __asm __emit 0x80 __asm _emit 0xEB __asm _emit 0xFE
+
+#endif // _AMD_SBTYPE_H_
diff --git a/src/vendorcode/amd/cimx/sb800/Smm.c b/src/vendorcode/amd/cimx/sb800/Smm.c
new file mode 100644
index 0000000..894ec2a
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/Smm.c
@@ -0,0 +1,86 @@
+/**
+ * @file
+ *
+ * Southbridge SMM service function
+ *
+ * Prepare SMM service module for IBV call Southbridge SMI service routine.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$ @e \$Date:$
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "SBPLATFORM.h"
+#include "cbtypes.h"
+
+//
+// Declaration of local functions
+//
+
+/**
+ * Southbridge SMI service module
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+sbSmmService (
+ IN AMDSBCFG* pConfig
+ )
+{
+ AMDSBCFG* pTmp; //lx-dummy for /W4 build
+ pTmp = pConfig;
+}
+
+/**
+ * softwareSMIservice - Software SMI service
+ *
+ * @param[in] VOID Southbridge software SMI service ID.
+ *
+ */
+VOID
+softwareSMIservice (
+ IN VOID
+ )
+{
+}
+
+
+
+
+
diff --git a/src/vendorcode/amd/cimx/sb800/USB.c b/src/vendorcode/amd/cimx/sb800/USB.c
deleted file mode 100644
index 14794cd..0000000
--- a/src/vendorcode/amd/cimx/sb800/USB.c
+++ /dev/null
@@ -1,431 +0,0 @@
-/**
- * @file
- *
- * Config Southbridge USB controller
- *
- * Init USB features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: CIMx-SB
- * @e sub-project:
- * @e \$Revision:$ @e \$Date:$
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-#include "SBPLATFORM.h"
-#include "cbtypes.h"
-
-//
-// Declaration of local functions
-//
-
-/**
- * EhciInitAfterPciInit - Config USB controller after PCI emulation
- *
- * @param[in] Value Controller PCI config address (bus# + device# + function#)
- * @param[in] pConfig Southbridge configuration structure pointer.
- */
-VOID EhciInitAfterPciInit (IN UINT32 Value, IN AMDSBCFG* pConfig);
-/**
- * OhciInitAfterPciInit - Config USB OHCI controller after PCI emulation
- *
- * @param[in] Value Controller PCI config address (bus# + device# + function#)
- * @param[in] pConfig Southbridge configuration structure pointer.
- */
-VOID OhciInitAfterPciInit (IN UINT32 Value, IN AMDSBCFG* pConfig);
-
-/**
- * SetEhciP11Wr - FIXME
- *
- * @param[in] Value Controller PCI config address (bus# + device# + function#)
- * @param[in] pConfig Southbridge configuration structure pointer.
- */
-UINT32 SetEhciPllWr (IN UINT32 Value, IN AMDSBCFG* pConfig);
-
-
-/**
- * usbInitBeforePciEnum - Config USB controller before PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-usbInitBeforePciEnum (
- IN AMDSBCFG* pConfig
- )
-{
- // Disabled All USB controller
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, BIT7, 0);
- // Clear PM_IO 0x65[4] UsbResetByPciRstEnable, Set this bit so that usb gets reset whenever there is PCIRST.
- // Enable UsbResumeEnable (USB PME) * Default value
- // In SB700 USB SleepCtrl set as BIT10+BIT9, but SB800 default is BIT9+BIT8 (6 uframes)
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint16 | S3_SAVE, ~BIT2, BIT2 + BIT7 + BIT8 + BIT9);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, 0, pConfig->USBMODE.UsbModeReg);
-}
-
-/**
- * usbInitAfterPciInit - Config USB controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-usbInitAfterPciInit (
- IN AMDSBCFG* pConfig
- )
-{
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGED, AccWidthUint8, ~BIT1, BIT1);
-
- usb1EhciInitAfterPciInit (pConfig);
- usb2EhciInitAfterPciInit (pConfig);
- usb3EhciInitAfterPciInit (pConfig);
- usb1OhciInitAfterPciInit (pConfig);
- usb2OhciInitAfterPciInit (pConfig);
- usb3OhciInitAfterPciInit (pConfig);
- usb4OhciInitAfterPciInit (pConfig);
-
- if ( pConfig->UsbPhyPowerDown ) {
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint8, ~BIT0, BIT0);
- } else
- {
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint8, ~BIT0, 0);
- }
-
-}
-
-/**
- * usb1EhciInitAfterPciInit - Config USB1 EHCI controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-usb1EhciInitAfterPciInit (
- IN AMDSBCFG* pConfig
- )
-{
- UINT32 ddDeviceId;
- ddDeviceId = (USB1_EHCI_BUS_DEV_FUN << 16);
- EhciInitAfterPciInit (ddDeviceId, pConfig);
-}
-
-/**
- * usb2EhciInitAfterPciInit - Config USB2 EHCI controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-usb2EhciInitAfterPciInit (
- IN AMDSBCFG* pConfig
- )
-{
- UINT32 ddDeviceId;
- ddDeviceId = (USB2_EHCI_BUS_DEV_FUN << 16);
- EhciInitAfterPciInit (ddDeviceId, pConfig);
-}
-
-/**
- * usb3EhciInitAfterPciInit - Config USB3 EHCI controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-usb3EhciInitAfterPciInit (
- IN AMDSBCFG* pConfig
- )
-{
- UINT32 ddDeviceId;
- ddDeviceId = (USB3_EHCI_BUS_DEV_FUN << 16);
- EhciInitAfterPciInit (ddDeviceId, pConfig);
-}
-
-VOID
-EhciInitAfterPciInit (
- IN UINT32 Value,
- IN AMDSBCFG* pConfig
- )
-{
- UINT32 ddBarAddress;
- UINT32 ddVar;
- //Get BAR address
- ReadPCI ((UINT32) Value + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress);
- if ( (ddBarAddress != - 1) && (ddBarAddress != 0) ) {
- //Enable Memory access
- RWPCI ((UINT32) Value + SB_EHCI_REG04, AccWidthUint8, 0, BIT1);
- if (pConfig->BuildParameters.EhciSsid != 0 ) {
- RWPCI ((UINT32) Value + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.EhciSsid);
- }
- //USB Common PHY CAL & Control Register setting
- ddVar = 0x00020F00;
- WriteMEM (ddBarAddress + SB_EHCI_BAR_REGC0, AccWidthUint32, &ddVar);
- // RPR IN AND OUT DATA PACKET FIFO THRESHOLD
- // EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40 //OUT threshold bits[23:16]=0x40
- RWMEM (ddBarAddress + SB_EHCI_BAR_REGA4, AccWidthUint32, 0xFF00FF00, 0x00400040);
- // RPR EHCI Dynamic Clock Gating Feature
- RWMEM (ddBarAddress + SB_EHCI_BAR_REGBC, AccWidthUint32, ~BIT12, 0);
- // RPR Enable adding extra flops to PHY rsync path
- // Step 1:
- // EHCI_BAR 0xB4 [6] = 1
- // EHCI_BAR 0xB4 [7] = 0
- // EHCI_BAR 0xB4 [12] = 0 ("VLoad")
- // All other bit field untouched
- // Step 2:
- // EHCI_BAR 0xB4[12] = 1
- RWMEM (ddBarAddress + SB_EHCI_BAR_REGB4, AccWidthUint32, ~(BIT6 + BIT7 + BIT12), 0x00);
- RWMEM (ddBarAddress + SB_EHCI_BAR_REGB4, AccWidthUint32, ~BIT12, BIT12);
- //Set EHCI_pci_configx50[6]='1' to disable EHCI MSI support
- //RPR recommended setting "EHCI Async Park Mode"
- //Set EHCI_pci_configx50[23]='0' to enable "EHCI Async Park Mode support"
- //RPR Enabling EHCI Async Stop Enhancement
- //Set EHCI_pci_configx50[29]='1' to disableEnabling EHCI Async Stop Enhancement
- RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(BIT23), BIT29 + BIT23 + BIT8 + BIT6);
- // RPR recommended setting "EHCI Advance PHY Power Savings"
- // Set EHCI_pci_configx50[31]='1'
- // Fix for EHCI controller driver yellow sign issue under device manager
- // when used in conjunction with HSET tool driver. EHCI PCI config 0x50[20]=1
- RWPCI ((UINT32) Value + SB_EHCI_REG50 + 2, AccWidthUint16 | S3_SAVE, (UINT16)0xFFFF, BIT15);
- // RPR USB Delay A-Link Express L1 State
- // RPR PING Response Fix Enable EHCI_PCI_Config x54[1] = 1
- // RPR Empty-list Detection Fix Enable EHCI_PCI_Config x54[3] = 1
- RWPCI ((UINT32) Value + SB_EHCI_REG54, AccWidthUint32 | S3_SAVE, ~BIT0, BIT0);
- if ( pConfig->BuildParameters.UsbMsi) {
- RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~BIT6, 0x00);
- }
- }
-}
-
-/**
- * usb1OhciInitAfterPciInit - Config USB1 OHCI controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-usb1OhciInitAfterPciInit (
- IN AMDSBCFG* pConfig
- )
-{
- UINT32 ddDeviceId;
- ddDeviceId = (USB1_OHCI_BUS_DEV_FUN << 16);
- OhciInitAfterPciInit (ddDeviceId, pConfig);
-}
-
-/**
- * usb2OhciInitAfterPciInit - Config USB2 OHCI controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-usb2OhciInitAfterPciInit (
- IN AMDSBCFG* pConfig
- )
-{
- UINT32 ddDeviceId;
- ddDeviceId = (USB2_OHCI_BUS_DEV_FUN << 16);
- OhciInitAfterPciInit (ddDeviceId, pConfig);
-}
-
-/**
- * usb3OhciInitAfterPciInit - Config USB3 OHCI controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-usb3OhciInitAfterPciInit (
- IN AMDSBCFG* pConfig
- )
-{
- UINT32 ddDeviceId;
- ddDeviceId = (USB3_OHCI_BUS_DEV_FUN << 16);
- OhciInitAfterPciInit (ddDeviceId, pConfig);
-}
-
-/**
- * usb4OhciInitAfterPciInit - Config USB4 OHCI controller after PCI emulation
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-usb4OhciInitAfterPciInit (
- IN AMDSBCFG* pConfig
- )
-{
- UINT32 ddDeviceId;
- ddDeviceId = (USB4_OHCI_BUS_DEV_FUN << 16);
- OhciInitAfterPciInit (ddDeviceId, pConfig);
- if (pConfig->BuildParameters.Ohci4Ssid != 0 ) {
- RWPCI ((USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.Ohci4Ssid);
- }
-}
-
-VOID
-OhciInitAfterPciInit (
- IN UINT32 Value,
- IN AMDSBCFG* pConfig
- )
-{
- // Disable the MSI capability of USB host controllers
- RWPCI ((UINT32) Value + SB_OHCI_REG40 + 1, AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
- RWPCI ((UINT32) Value + SB_OHCI_REG50, AccWidthUint8 | S3_SAVE, ~(BIT5 + BIT12), 0x00);
- // RPR USB SMI Handshake
- RWPCI ((UINT32) Value + SB_OHCI_REG50 + 1, AccWidthUint8 | S3_SAVE, ~BIT4, 0x00);
- // SB02186
- RWPCI ((UINT32) Value + SB_OHCI_REG50 + 1, AccWidthUint8 | S3_SAVE, 0xFC, 0x00);
- if (Value != (USB4_OHCI_BUS_DEV_FUN << 16)) {
- if ( pConfig->BuildParameters.OhciSsid != 0 ) {
- RWPCI ((UINT32) Value + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.OhciSsid);
- }
- }
- //RPR recommended setting to, enable fix to cover the corner case S3 wake up issue from some USB 1.1 devices
- //OHCI 0_PCI_Config 0x50[30] = 1
- RWPCI ((UINT32) Value + SB_OHCI_REG50 + 3, AccWidthUint8 | S3_SAVE, ~BIT6, BIT6);
- if ( pConfig->BuildParameters.UsbMsi) {
- RWPCI ((UINT32) Value + SB_OHCI_REG40 + 1, AccWidthUint8 | S3_SAVE, ~BIT0, 0x00);
- RWPCI ((UINT32) Value + SB_OHCI_REG50, AccWidthUint8 | S3_SAVE, ~BIT5, BIT5);
- }
-}
-
-
-UINT32
-SetEhciPllWr (
- IN UINT32 Value,
- IN AMDSBCFG* pConfig
- )
-{
- UINT32 ddRetureValue;
- UINT32 ddBarAddress;
- UINT16 dwVar;
- UINT16 dwData;
- UINT8 portSC;
- ddRetureValue = 0;
- dwData = 0;
- // Memory, and etc.
- //_asm { jmp $};
- RWPCI ((UINT32) Value + 0xC4, AccWidthUint8, 0xF0, 0x00);
- RWPCI ((UINT32) Value + 0x04, AccWidthUint8, 0xFF, 0x02);
- // Get Bar address
- ReadPCI ((UINT32) Value + 0x10, AccWidthUint32, &ddBarAddress);
- for (portSC = 0x64; portSC < 0x75; portSC += 0x04 ) {
- // Get OHCI command registers
- ReadMEM (ddBarAddress + portSC, AccWidthUint16, &dwVar);
- if ( dwVar & BIT6 ) {
- ddRetureValue = ddBarAddress + portSC;
- RWMEM (ddBarAddress + portSC, AccWidthUint16, ~BIT6, 0);
- for (;;) {
- SbStall (5);
- ReadMEM (ddBarAddress + portSC, AccWidthUint16, &dwData);
- if (dwData == 0x1005) break;
- }
- dwData = 0;
- }
- }
- return ddRetureValue;
-}
-
-VOID
-usbSetPllDuringS3 (
- IN AMDSBCFG* pConfig
- )
-{
- UINT32 resumeEhciPortTmp;
- UINT32 resumeEhciPort;
- resumeEhciPortTmp = 0;
- resumeEhciPort = 0;
-// UINT32 ddDeviceId;
-//if Force Port Resume == 1
-// {
-// clear Force Port Resume;
-// while (!(PORTSC == 0x1005)){wait 5 us; read PORTSC;}
-// }
- if (pConfig->USBMODE.UsbModeReg & BIT1) {
- resumeEhciPortTmp = SetEhciPllWr (USB1_EHCI_BUS_DEV_FUN << 16, pConfig);
- if (resumeEhciPortTmp > 0) resumeEhciPort = resumeEhciPortTmp;
- }
- if (pConfig->USBMODE.UsbModeReg & BIT3) {
- resumeEhciPortTmp = SetEhciPllWr (USB2_EHCI_BUS_DEV_FUN << 16, pConfig);
- if (resumeEhciPortTmp > 0) resumeEhciPort = resumeEhciPortTmp;
- }
- if (pConfig->USBMODE.UsbModeReg & BIT5) {
- resumeEhciPortTmp = SetEhciPllWr (USB3_EHCI_BUS_DEV_FUN << 16, pConfig);
- if (resumeEhciPortTmp > 0) resumeEhciPort = resumeEhciPortTmp;
- }
-
- RWPCI ((UINT32) (USB1_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, 0);
- RWPCI ((UINT32) (USB2_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, 0);
- RWPCI ((UINT32) (USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, 0);
- RWPCI ((UINT32) (USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, 0);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF3, AccWidthUint8, 0, 0x20);
- SbStall (10);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF3, AccWidthUint8, 0, 0x00);
- RWPCI ((UINT32) (USB1_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, BIT29);
- RWPCI ((UINT32) (USB2_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, BIT29);
- RWPCI ((UINT32) (USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, BIT29);
- RWPCI ((UINT32) (USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, BIT29);
-
- if (resumeEhciPort > 0) {
- RWMEM (resumeEhciPort, AccWidthUint8, ~BIT7, BIT7);
- SbStall (4000);
- RWMEM (resumeEhciPort, AccWidthUint8, ~BIT6, BIT6);
- }
-
- RWPCI ((UINT32) (USB1_EHCI_BUS_DEV_FUN << 16) + 0xC4, AccWidthUint8, 0xF0, 0x03);
- RWPCI ((UINT32) (USB2_EHCI_BUS_DEV_FUN << 16) + 0xC4, AccWidthUint8, 0xF0, 0x03);
- RWPCI ((UINT32) (USB3_EHCI_BUS_DEV_FUN << 16) + 0xC4, AccWidthUint8, 0xF0, 0x03);
-
-}
-
diff --git a/src/vendorcode/amd/cimx/sb800/Usb.c b/src/vendorcode/amd/cimx/sb800/Usb.c
new file mode 100644
index 0000000..14794cd
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/Usb.c
@@ -0,0 +1,431 @@
+/**
+ * @file
+ *
+ * Config Southbridge USB controller
+ *
+ * Init USB features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$ @e \$Date:$
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+
+#include "SBPLATFORM.h"
+#include "cbtypes.h"
+
+//
+// Declaration of local functions
+//
+
+/**
+ * EhciInitAfterPciInit - Config USB controller after PCI emulation
+ *
+ * @param[in] Value Controller PCI config address (bus# + device# + function#)
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ */
+VOID EhciInitAfterPciInit (IN UINT32 Value, IN AMDSBCFG* pConfig);
+/**
+ * OhciInitAfterPciInit - Config USB OHCI controller after PCI emulation
+ *
+ * @param[in] Value Controller PCI config address (bus# + device# + function#)
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ */
+VOID OhciInitAfterPciInit (IN UINT32 Value, IN AMDSBCFG* pConfig);
+
+/**
+ * SetEhciP11Wr - FIXME
+ *
+ * @param[in] Value Controller PCI config address (bus# + device# + function#)
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ */
+UINT32 SetEhciPllWr (IN UINT32 Value, IN AMDSBCFG* pConfig);
+
+
+/**
+ * usbInitBeforePciEnum - Config USB controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+usbInitBeforePciEnum (
+ IN AMDSBCFG* pConfig
+ )
+{
+ // Disabled All USB controller
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, BIT7, 0);
+ // Clear PM_IO 0x65[4] UsbResetByPciRstEnable, Set this bit so that usb gets reset whenever there is PCIRST.
+ // Enable UsbResumeEnable (USB PME) * Default value
+ // In SB700 USB SleepCtrl set as BIT10+BIT9, but SB800 default is BIT9+BIT8 (6 uframes)
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint16 | S3_SAVE, ~BIT2, BIT2 + BIT7 + BIT8 + BIT9);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, 0, pConfig->USBMODE.UsbModeReg);
+}
+
+/**
+ * usbInitAfterPciInit - Config USB controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+usbInitAfterPciInit (
+ IN AMDSBCFG* pConfig
+ )
+{
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGED, AccWidthUint8, ~BIT1, BIT1);
+
+ usb1EhciInitAfterPciInit (pConfig);
+ usb2EhciInitAfterPciInit (pConfig);
+ usb3EhciInitAfterPciInit (pConfig);
+ usb1OhciInitAfterPciInit (pConfig);
+ usb2OhciInitAfterPciInit (pConfig);
+ usb3OhciInitAfterPciInit (pConfig);
+ usb4OhciInitAfterPciInit (pConfig);
+
+ if ( pConfig->UsbPhyPowerDown ) {
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint8, ~BIT0, BIT0);
+ } else
+ {
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint8, ~BIT0, 0);
+ }
+
+}
+
+/**
+ * usb1EhciInitAfterPciInit - Config USB1 EHCI controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+usb1EhciInitAfterPciInit (
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT32 ddDeviceId;
+ ddDeviceId = (USB1_EHCI_BUS_DEV_FUN << 16);
+ EhciInitAfterPciInit (ddDeviceId, pConfig);
+}
+
+/**
+ * usb2EhciInitAfterPciInit - Config USB2 EHCI controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+usb2EhciInitAfterPciInit (
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT32 ddDeviceId;
+ ddDeviceId = (USB2_EHCI_BUS_DEV_FUN << 16);
+ EhciInitAfterPciInit (ddDeviceId, pConfig);
+}
+
+/**
+ * usb3EhciInitAfterPciInit - Config USB3 EHCI controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+usb3EhciInitAfterPciInit (
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT32 ddDeviceId;
+ ddDeviceId = (USB3_EHCI_BUS_DEV_FUN << 16);
+ EhciInitAfterPciInit (ddDeviceId, pConfig);
+}
+
+VOID
+EhciInitAfterPciInit (
+ IN UINT32 Value,
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT32 ddBarAddress;
+ UINT32 ddVar;
+ //Get BAR address
+ ReadPCI ((UINT32) Value + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress);
+ if ( (ddBarAddress != - 1) && (ddBarAddress != 0) ) {
+ //Enable Memory access
+ RWPCI ((UINT32) Value + SB_EHCI_REG04, AccWidthUint8, 0, BIT1);
+ if (pConfig->BuildParameters.EhciSsid != 0 ) {
+ RWPCI ((UINT32) Value + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.EhciSsid);
+ }
+ //USB Common PHY CAL & Control Register setting
+ ddVar = 0x00020F00;
+ WriteMEM (ddBarAddress + SB_EHCI_BAR_REGC0, AccWidthUint32, &ddVar);
+ // RPR IN AND OUT DATA PACKET FIFO THRESHOLD
+ // EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40 //OUT threshold bits[23:16]=0x40
+ RWMEM (ddBarAddress + SB_EHCI_BAR_REGA4, AccWidthUint32, 0xFF00FF00, 0x00400040);
+ // RPR EHCI Dynamic Clock Gating Feature
+ RWMEM (ddBarAddress + SB_EHCI_BAR_REGBC, AccWidthUint32, ~BIT12, 0);
+ // RPR Enable adding extra flops to PHY rsync path
+ // Step 1:
+ // EHCI_BAR 0xB4 [6] = 1
+ // EHCI_BAR 0xB4 [7] = 0
+ // EHCI_BAR 0xB4 [12] = 0 ("VLoad")
+ // All other bit field untouched
+ // Step 2:
+ // EHCI_BAR 0xB4[12] = 1
+ RWMEM (ddBarAddress + SB_EHCI_BAR_REGB4, AccWidthUint32, ~(BIT6 + BIT7 + BIT12), 0x00);
+ RWMEM (ddBarAddress + SB_EHCI_BAR_REGB4, AccWidthUint32, ~BIT12, BIT12);
+ //Set EHCI_pci_configx50[6]='1' to disable EHCI MSI support
+ //RPR recommended setting "EHCI Async Park Mode"
+ //Set EHCI_pci_configx50[23]='0' to enable "EHCI Async Park Mode support"
+ //RPR Enabling EHCI Async Stop Enhancement
+ //Set EHCI_pci_configx50[29]='1' to disableEnabling EHCI Async Stop Enhancement
+ RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(BIT23), BIT29 + BIT23 + BIT8 + BIT6);
+ // RPR recommended setting "EHCI Advance PHY Power Savings"
+ // Set EHCI_pci_configx50[31]='1'
+ // Fix for EHCI controller driver yellow sign issue under device manager
+ // when used in conjunction with HSET tool driver. EHCI PCI config 0x50[20]=1
+ RWPCI ((UINT32) Value + SB_EHCI_REG50 + 2, AccWidthUint16 | S3_SAVE, (UINT16)0xFFFF, BIT15);
+ // RPR USB Delay A-Link Express L1 State
+ // RPR PING Response Fix Enable EHCI_PCI_Config x54[1] = 1
+ // RPR Empty-list Detection Fix Enable EHCI_PCI_Config x54[3] = 1
+ RWPCI ((UINT32) Value + SB_EHCI_REG54, AccWidthUint32 | S3_SAVE, ~BIT0, BIT0);
+ if ( pConfig->BuildParameters.UsbMsi) {
+ RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~BIT6, 0x00);
+ }
+ }
+}
+
+/**
+ * usb1OhciInitAfterPciInit - Config USB1 OHCI controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+usb1OhciInitAfterPciInit (
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT32 ddDeviceId;
+ ddDeviceId = (USB1_OHCI_BUS_DEV_FUN << 16);
+ OhciInitAfterPciInit (ddDeviceId, pConfig);
+}
+
+/**
+ * usb2OhciInitAfterPciInit - Config USB2 OHCI controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+usb2OhciInitAfterPciInit (
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT32 ddDeviceId;
+ ddDeviceId = (USB2_OHCI_BUS_DEV_FUN << 16);
+ OhciInitAfterPciInit (ddDeviceId, pConfig);
+}
+
+/**
+ * usb3OhciInitAfterPciInit - Config USB3 OHCI controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+usb3OhciInitAfterPciInit (
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT32 ddDeviceId;
+ ddDeviceId = (USB3_OHCI_BUS_DEV_FUN << 16);
+ OhciInitAfterPciInit (ddDeviceId, pConfig);
+}
+
+/**
+ * usb4OhciInitAfterPciInit - Config USB4 OHCI controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+usb4OhciInitAfterPciInit (
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT32 ddDeviceId;
+ ddDeviceId = (USB4_OHCI_BUS_DEV_FUN << 16);
+ OhciInitAfterPciInit (ddDeviceId, pConfig);
+ if (pConfig->BuildParameters.Ohci4Ssid != 0 ) {
+ RWPCI ((USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.Ohci4Ssid);
+ }
+}
+
+VOID
+OhciInitAfterPciInit (
+ IN UINT32 Value,
+ IN AMDSBCFG* pConfig
+ )
+{
+ // Disable the MSI capability of USB host controllers
+ RWPCI ((UINT32) Value + SB_OHCI_REG40 + 1, AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
+ RWPCI ((UINT32) Value + SB_OHCI_REG50, AccWidthUint8 | S3_SAVE, ~(BIT5 + BIT12), 0x00);
+ // RPR USB SMI Handshake
+ RWPCI ((UINT32) Value + SB_OHCI_REG50 + 1, AccWidthUint8 | S3_SAVE, ~BIT4, 0x00);
+ // SB02186
+ RWPCI ((UINT32) Value + SB_OHCI_REG50 + 1, AccWidthUint8 | S3_SAVE, 0xFC, 0x00);
+ if (Value != (USB4_OHCI_BUS_DEV_FUN << 16)) {
+ if ( pConfig->BuildParameters.OhciSsid != 0 ) {
+ RWPCI ((UINT32) Value + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.OhciSsid);
+ }
+ }
+ //RPR recommended setting to, enable fix to cover the corner case S3 wake up issue from some USB 1.1 devices
+ //OHCI 0_PCI_Config 0x50[30] = 1
+ RWPCI ((UINT32) Value + SB_OHCI_REG50 + 3, AccWidthUint8 | S3_SAVE, ~BIT6, BIT6);
+ if ( pConfig->BuildParameters.UsbMsi) {
+ RWPCI ((UINT32) Value + SB_OHCI_REG40 + 1, AccWidthUint8 | S3_SAVE, ~BIT0, 0x00);
+ RWPCI ((UINT32) Value + SB_OHCI_REG50, AccWidthUint8 | S3_SAVE, ~BIT5, BIT5);
+ }
+}
+
+
+UINT32
+SetEhciPllWr (
+ IN UINT32 Value,
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT32 ddRetureValue;
+ UINT32 ddBarAddress;
+ UINT16 dwVar;
+ UINT16 dwData;
+ UINT8 portSC;
+ ddRetureValue = 0;
+ dwData = 0;
+ // Memory, and etc.
+ //_asm { jmp $};
+ RWPCI ((UINT32) Value + 0xC4, AccWidthUint8, 0xF0, 0x00);
+ RWPCI ((UINT32) Value + 0x04, AccWidthUint8, 0xFF, 0x02);
+ // Get Bar address
+ ReadPCI ((UINT32) Value + 0x10, AccWidthUint32, &ddBarAddress);
+ for (portSC = 0x64; portSC < 0x75; portSC += 0x04 ) {
+ // Get OHCI command registers
+ ReadMEM (ddBarAddress + portSC, AccWidthUint16, &dwVar);
+ if ( dwVar & BIT6 ) {
+ ddRetureValue = ddBarAddress + portSC;
+ RWMEM (ddBarAddress + portSC, AccWidthUint16, ~BIT6, 0);
+ for (;;) {
+ SbStall (5);
+ ReadMEM (ddBarAddress + portSC, AccWidthUint16, &dwData);
+ if (dwData == 0x1005) break;
+ }
+ dwData = 0;
+ }
+ }
+ return ddRetureValue;
+}
+
+VOID
+usbSetPllDuringS3 (
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT32 resumeEhciPortTmp;
+ UINT32 resumeEhciPort;
+ resumeEhciPortTmp = 0;
+ resumeEhciPort = 0;
+// UINT32 ddDeviceId;
+//if Force Port Resume == 1
+// {
+// clear Force Port Resume;
+// while (!(PORTSC == 0x1005)){wait 5 us; read PORTSC;}
+// }
+ if (pConfig->USBMODE.UsbModeReg & BIT1) {
+ resumeEhciPortTmp = SetEhciPllWr (USB1_EHCI_BUS_DEV_FUN << 16, pConfig);
+ if (resumeEhciPortTmp > 0) resumeEhciPort = resumeEhciPortTmp;
+ }
+ if (pConfig->USBMODE.UsbModeReg & BIT3) {
+ resumeEhciPortTmp = SetEhciPllWr (USB2_EHCI_BUS_DEV_FUN << 16, pConfig);
+ if (resumeEhciPortTmp > 0) resumeEhciPort = resumeEhciPortTmp;
+ }
+ if (pConfig->USBMODE.UsbModeReg & BIT5) {
+ resumeEhciPortTmp = SetEhciPllWr (USB3_EHCI_BUS_DEV_FUN << 16, pConfig);
+ if (resumeEhciPortTmp > 0) resumeEhciPort = resumeEhciPortTmp;
+ }
+
+ RWPCI ((UINT32) (USB1_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, 0);
+ RWPCI ((UINT32) (USB2_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, 0);
+ RWPCI ((UINT32) (USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, 0);
+ RWPCI ((UINT32) (USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, 0);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF3, AccWidthUint8, 0, 0x20);
+ SbStall (10);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF3, AccWidthUint8, 0, 0x00);
+ RWPCI ((UINT32) (USB1_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, BIT29);
+ RWPCI ((UINT32) (USB2_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, BIT29);
+ RWPCI ((UINT32) (USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, BIT29);
+ RWPCI ((UINT32) (USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, BIT29);
+
+ if (resumeEhciPort > 0) {
+ RWMEM (resumeEhciPort, AccWidthUint8, ~BIT7, BIT7);
+ SbStall (4000);
+ RWMEM (resumeEhciPort, AccWidthUint8, ~BIT6, BIT6);
+ }
+
+ RWPCI ((UINT32) (USB1_EHCI_BUS_DEV_FUN << 16) + 0xC4, AccWidthUint8, 0xF0, 0x03);
+ RWPCI ((UINT32) (USB2_EHCI_BUS_DEV_FUN << 16) + 0xC4, AccWidthUint8, 0xF0, 0x03);
+ RWPCI ((UINT32) (USB3_EHCI_BUS_DEV_FUN << 16) + 0xC4, AccWidthUint8, 0xF0, 0x03);
+
+}
+
diff --git a/src/vendorcode/amd/cimx/sb900/Makefile.inc b/src/vendorcode/amd/cimx/sb900/Makefile.inc
index 8d753d1..8cdc4b1 100644
--- a/src/vendorcode/amd/cimx/sb900/Makefile.inc
+++ b/src/vendorcode/amd/cimx/sb900/Makefile.inc
@@ -33,7 +33,7 @@ romstage-y += Pmio2Lib.c
romstage-y += Sata.c
romstage-y += SbCmn.c
romstage-y += SbMain.c
-romstage-y += SBPort.c
+romstage-y += SbPort.c
romstage-y += MemLib.c
romstage-y += PciLib.c
romstage-y += IoLib.c
@@ -58,7 +58,7 @@ ramstage-y += Pmio2Lib.c
ramstage-y += Sata.c
ramstage-y += SbCmn.c
ramstage-y += SbMain.c
-ramstage-y += SBPort.c
+ramstage-y += SbPort.c
ramstage-y += MemLib.c
ramstage-y += PciLib.c
ramstage-y += IoLib.c
diff --git a/src/vendorcode/amd/cimx/sb900/SBPort.c b/src/vendorcode/amd/cimx/sb900/SBPort.c
deleted file mode 100644
index 90e878e..0000000
--- a/src/vendorcode/amd/cimx/sb900/SBPort.c
+++ /dev/null
@@ -1,737 +0,0 @@
-
-/**
- * @file
- *
- * Southbridge Init during POWER-ON
- *
- * Prepare Southbridge environment during power on stage.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: CIMx-SB
- * @e sub-project:
- * @e \$Revision:$ @e \$Date:$
- *
- */
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#include "SbPlatform.h"
-#include "cbtypes.h"
-#include "AmdSbLib.h"
-#include "Hudson-2.h"
-
-/**
- * sbPorInitPciTable - PCI device registers initial during the power on stage.
- *
- *
- *
- *
- */
-REG8MASK sbPorInitPciTable[] =
-{
- // SATA device
- {0x00, SATA_BUS_DEV_FUN, 0},
- {SB_SATA_REG84 + 3, ~BIT2, 0},
- {SB_SATA_REGA0, ~(BIT2 + BIT3 + BIT4 + BIT5 + BIT6), BIT2 + BIT3 + BIT4 + BIT5},
- {0xFF, 0xFF, 0xFF},
- // LPC Device (Bus 0, Dev 20, Func 3)
- {0x00, LPC_BUS_DEV_FUN, 0},
- {SB_LPC_REG44, 0xFF, BIT6 + BIT7}, //Enable COM1 and COM2
- {SB_LPC_REG47, 0xFF, BIT5},
- {SB_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2},
- {SB_LPC_REG7C, 0x00, BIT0 + BIT2},
- {SB_LPC_REG78, 0xF0, BIT2 + BIT3}, // Enable LDRQ pin
- {SB_LPC_REGBB, 0xFF, BIT3 + BIT4 + BIT5},
- // A12 set 0xBB [5:3] = 111 to improve SPI timing margin.
- // A12 Set 0xBA [6:5] = 11 improve SPI timing margin. (SPI Prefetch enhancement)
- {SB_LPC_REGBB, 0xBE, BIT0 + BIT3 + BIT4 + BIT5},
- {SB_LPC_REGBA, 0x9F, BIT5 + BIT6},
- {SB_LPC_REGA4, ~ BIT0, BIT0}, //[BUG Fix] Force EC_PortActive to 1 to fix possible IR non function issue when NO_EC_SUPPORT is defined
- {0xFF, 0xFF, 0xFF},
- // P2P Bridge (Bus 0, Dev 20, Func 4)
- {0x00, PCIB_BUS_DEV_FUN, 0},
- {SB_PCIB_REG4B, 0xFF, BIT6 + BIT7 + BIT4},
- // ENH230012: Disable P2P bridge decoder for IO address 0x1000-0x1FFF in SBPOR
- // ENH260809: Add PCI port 80 support in Hudson-2/3
-#ifdef SB_PCIB_PORT_80_SUPPORT
- {SB_PCIB_REG1C, 0x00, 0xF0},
- {SB_PCIB_REG1D, 0x00, 0x00},
- {SB_PCIB_REG04, 0x00, 0x21},
-#endif
- {SB_PCIB_REG40, 0xDF, 0x20},
- {SB_PCIB_REG50, 0x02, 0x01},
- {0xFF, 0xFF, 0xFF},
-};
-
-/**
- * sbPmioPorInitTable - Southbridge ACPI MMIO initial during the power on stage.
- *
- *
- *
- *
- */
-AcpiRegWrite sbPmioPorInitTable[] =
-{
- {00, 00, 0xB0, 0xAC}, // Signature
- {MISC_BASE >> 8, SB_MISC_REG41, 0x1F, 0x40}, //keep Auxiliary_14Mclk_Sel [12]
- //RPR 8.9 USB 3.0 Reference Clock MISC_REG 0x40 [4] = 0 Enable spread-spectrum reference clock.
- {MISC_BASE >> 8, SB_MISC_REG40, 0xEF, 0x00},
-// {MISC_BASE >> 8, 0x24 + 2, 0xFF, 0x20}, Testing CPU clk strength
- {PMIO_BASE >> 8, SB_PMIOA_REG5D, 0x00, BIT0},
- {PMIO_BASE >> 8, SB_PMIOA_REGD2, 0xCF, BIT4 + BIT5},
- {SMBUS_BASE >> 8, SB_SMBUS_REG12, 0x00, BIT0},
- {PMIO_BASE >> 8, SB_PMIOA_REG28, 0xFF, BIT0 + BIT2},
- {PMIO_BASE >> 8, SB_PMIOA_REG44 + 3, 0x67, BIT7 + BIT3}, // 2.5 Enable Boot Timer
- {PMIO_BASE >> 8, SB_PMIOA_REG48, 0xFF, BIT0},
- {PMIO_BASE >> 8, SB_PMIOA_REG00, 0xFF, 0x0E},
- {PMIO_BASE >> 8, SB_PMIOA_REG00 + 2, 0xFF, 0x40},
- {PMIO_BASE >> 8, SB_PMIOA_REG00 + 3, 0xFF, 0x08},
- {PMIO_BASE >> 8, SB_PMIOA_REG34, 0xEF, BIT0 + BIT1},
- {PMIO_BASE >> 8, SB_PMIOA_REGEC, 0xFD, BIT1},
- //{PMIO_BASE >> 8, SB_PMIOA_REG5B, 0xF9, BIT1 + BIT2},
- {PMIO_BASE >> 8, SB_PMIOA_REG08, 0xFE, BIT2 + BIT4},
- {PMIO_BASE >> 8, SB_PMIOA_REG08 + 1, 0xFF, BIT0},
- {PMIO_BASE >> 8, SB_PMIOA_REG54, 0x00, BIT4 + BIT6 + BIT7},
- {PMIO_BASE >> 8, SB_PMIOA_REG04 + 3, 0xFD, BIT1},
- {PMIO_BASE >> 8, SB_PMIOA_REG74, 0xF6, BIT0 + BIT3},
- {PMIO_BASE >> 8, SB_PMIOA_REGF0, ~BIT2, 0x00},
- // RPR GEC I/O Termination Setting
- // PM_Reg 0xF6 = Power-on default setting
- // PM_Reg 0xF7 = Power-on default setting
- // PM_Reg 0xF8 = 0x6C
- // PM_Reg 0xF9 = 0x21
- // PM_Reg 0xFA = 0x00 Hudson-2 A12 GEC I/O Pad settings for 3.3V CMOS
- {PMIO_BASE >> 8, SB_PMIOA_REGF8, 0x00, 0x6C},
- {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 1, 0x00, 0x07},
- {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 2, 0x00, 0x00},
- // PRP GEC -end
- {PMIO_BASE >> 8, SB_PMIOA_REGC4, 0xee, 0x04}, // Release NB_PCIE_RST
- {PMIO_BASE >> 8, SB_PMIOA_REGC0 + 2, 0xBF, 0x40},
-
- {PMIO_BASE >> 8, SB_PMIOA_REGBE, 0xDF, BIT5},
-
- //OBS200280
- //{PMIO_BASE >> 8, SB_PMIOA_REGBE, 0xFF, BIT1},
-
-
- {0xFF, 0xFF, 0xFF, 0xFF},
-};
-
-/**
- * sbPowerOnInit - Config Southbridge during power on stage.
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-sbPowerOnInit (
- IN AMDSBCFG* pConfig
- )
-{
- UINT8 dbPortStatus;
- //UINT8 dbSysConfig;
- UINT32 abValue;
- UINT32 abValue2;
- UINT8 dbValue;
- UINT8 dbEfuse;
- UINT32 dbSpiMode;
- UINT16 dwAsfPort;
- UINT16 smbusBase;
- UINT8 cimSataMode;
-// UINT8 cimSpiFastReadEnable;
-// UINT8 cimSpiFastReadSpeed;
- UINT8 cimSataInternal100Spread;
- UINT8 indexValue;
- UINT32 ddValue;
- UINT8 SataPortNum;
- UINT8 XhciEfuse;
- XhciEfuse = XHCI_EFUSE_LOCATION;
-
- cimSataMode = pConfig->SATAMODE.SataModeReg;
-// if (pConfig->BuildParameters.SpiFastReadEnable != NULL ) {
-// cimSpiFastReadEnable = (UINT8) pConfig->BuildParameters.SpiFastReadEnable;
-// } else {
-// cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
-// }
-// cimSpiFastReadSpeed = (UINT8) pConfig->BuildParameters.SpiFastReadSpeed;
- cimSataInternal100Spread = ( UINT8 ) pConfig->SataInternal100Spread;
-
-#if SB_CIMx_PARAMETER == 0
- cimSataMode = (UINT8) ((cimSataMode & 0xFB) | cimSataSetMaxGen2Default);
- cimSataMode = (UINT8) ((cimSataMode & 0x0F) | cimSataClkModeDefault);
- cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
- cimSpiFastReadSpeed = cimSpiFastReadSpeedDefault;
- cimSataInternal100Spread = SataInternal100SpreadDefault;
-#endif
-
- TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbPowerOnInit \n"));
-
-// Hudson-2 Only Enabled (Mmio_mem_enablr) // Default value is correct
- RWPMIO (SB_PMIOA_REG24, AccWidthUint8, 0xFF, BIT0);
-
- RWPMIO (0xD3, AccWidthUint8, ~BIT4, 0);
- RWPMIO (0xD3, AccWidthUint8, ~BIT4, BIT4);
-
- if ( pConfig->Cg2Pll == 1 ) {
- TurnOffCG2 ();
- pConfig->SATAMODE.SataMode.SataClkMode = 0x0a;
- }
-
- //enable CF9
- RWPMIO (0xD2, AccWidthUint8, ~BIT6, 0);
-
-// Set A-Link bridge access address. This address is set at device 14h, function 0,
-// register 0f0h. This is an I/O address. The I/O address must be on 16-byte boundary.
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGE0, AccWidthUint32, 00, ALINK_ACCESS_INDEX);
- writeAlink (0x80000004, 0x04); // RPR 4.2 Enable Hudson-2 to issue memory read/write requests in the upstream direction
- abValue = readAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29)); // RPR 4.5 Disable the credit variable in the downstream arbitration equation
- abValue = abValue | BIT0;
- writeAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29), abValue);
- writeAlink (0x30, 0x10); // AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform.
- writeAlink (0x34, readAlink (0x34) | BIT9);
- rwAlink (SB_ABCFG_REG10050 | (UINT32) (ABCFG << 29), ~BIT2, 0x00);
-
- // Enable external Stickybit register reset feature
- //writeAlink (SB_AX_INDXC_REG30 | (UINT32) (AXINDC << 29), 0x30);
- //abValue = readAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29));
- //abValue |= BIT6 + BIT5;
- //writeAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29), abValue);
-
- // Configure UMI target link speed
- dbEfuse = PCIE_FORCE_GEN1_EFUSE_LOCATION;
- getEfuseStatus (&dbEfuse);
- if ( dbEfuse & BIT0 ) {
- pConfig->NbSbGen2 = 0;
- }
-
- dbEfuse = FCH_Variant_EFUSE_LOCATION;
- getEfuseStatus (&dbEfuse);
- if ((dbEfuse == 0x07) || (dbEfuse == 0x08)) {
- pConfig->NbSbGen2 = 0;
- }
-
- if (pConfig->NbSbGen2) {
- abValue = 2;
- abValue2 = BIT0;
- } else {
- abValue = 1;
- abValue2 = 0;
- }
- rwAlink (SB_AX_INDXP_REGA4, 0xFFFFFFFE, abValue2);
- rwAlink ((UINT32)SB_AX_CFG_REG88, 0xFFFFFFF0, abValue);
-
- if (pConfig->sdbEnable) {
- rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~BIT12, 0x00);
- RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 0, AccWidthUint8, 0, pConfig->Debug_Reg00);
- RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 2, AccWidthUint8, 0, pConfig->Debug_Reg02);
- RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 4, AccWidthUint8, 0, pConfig->Debug_Reg04);
- RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 1, AccWidthUint8, 0, pConfig->Debug_Reg01);
- RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 3, AccWidthUint8, 0, pConfig->Debug_Reg03);
- RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 5, AccWidthUint8, 0, pConfig->Debug_Reg05);
- }
-
-// Set Build option into SB
- WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioPmeBaseAddress));
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F, (pConfig->BuildParameters.SpiRomBaseAddress));
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint32 | S3_SAVE, 0, (pConfig->BuildParameters.GecShadowRomBase + 1));
-// Enabled SMBUS0/SMBUS1 (ASF) Base Address
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2C, AccWidthUint16, 06, (pConfig->BuildParameters.Smbus0BaseAddress) + BIT0); //protect BIT[2:1]
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG28, AccWidthUint16, 06, (pConfig->BuildParameters.Smbus1BaseAddress) + BIT0);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG60, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1EvtBlkAddr));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG62, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1CntBlkAddr));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmTmrBlkAddr));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG66, AccWidthUint16, 00, (pConfig->BuildParameters.CpuControlBlkAddr));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG68, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiGpe0BlkAddr));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6A, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6C, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmaCntBlkAddr));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6E, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr) + 8);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG48, AccWidthUint32, 00, (pConfig->BuildParameters.WatchDogTimerBase));
-
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2E, AccWidthUint8, ~(BIT1 + BIT2), 0); //clear BIT[2:1]
- smbusBase = (UINT16) (pConfig->BuildParameters.Smbus0BaseAddress);
- dbValue = 0x00;
- WriteIO (smbusBase + 0x14, AccWidthUint8, &dbValue);
-
- dbEfuse = SATA_FIS_BASE_EFUSE_LOC;
- getEfuseStatus (&dbEfuse);
-
- programSbAcpiMmioTbl ((AcpiRegWrite*) FIXUP_PTR (&sbPmioPorInitTable[0]));
-
- //RPR 3.4 Enabling ClkRun Function
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBB, AccWidthUint8, ~ BIT2, BIT2);
- //BUG265683: Mismatch clkrun enable register setting between RPR and CIMX code
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGD0, AccWidthUint8, ~ BIT2, 0);
-
- SataPortNum = 0;
- for ( SataPortNum = 0; SataPortNum < 0x06; SataPortNum++ ) {
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, 1 << SataPortNum);
- SbStall (2);
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, (0xFF ^ (1 << SataPortNum)) , 0x00);
- SbStall (2);
- }
-
- dbValue = 0x0A;
- WriteIO (SB_IOMAP_REG70, AccWidthUint8, &dbValue);
- ReadIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
- dbValue &= 0xEF;
- WriteIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
-
- RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, (BIT19 + BIT24 + BIT25 + BIT26));
- RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, 0xFFC0FFFF, 0 );
- if (pConfig->BuildParameters.SpiSpeed) {
- RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, ~(BIT13 + BIT12), ((pConfig->BuildParameters.SpiSpeed - 1 ) << 12));
- }
- if (pConfig->BuildParameters.SpiFastSpeed) {
- RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, ~(BIT15 + BIT14), ((pConfig->BuildParameters.SpiFastSpeed - 1 ) << 14));
- }
- //if (pConfig->BuildParameters.SpiBurstWrite) {
- RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG1C, AccWidthUint32 | S3_SAVE, ~(BIT10), ((pConfig->BuildParameters.SpiBurstWrite) << 10));
- //}
- dbSpiMode = pConfig->BuildParameters.SpiMode;
- if (pConfig->BuildParameters.SpiMode) {
- if ((dbSpiMode == SB_SPI_MODE_QUAL_114) || (dbSpiMode == SB_SPI_MODE_QUAL_112) || (dbSpiMode == SB_SPI_MODE_QUAL_144) || (dbSpiMode == SB_SPI_MODE_QUAL_122)) {
- // RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFF0000, 0x013e);
- // RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, 0xFFFFFF00, 0x80 );
- // RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFEFFFF, 0x10000);
- // SbStall (1000);
- }
- RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, ~( BIT18 + BIT29 + BIT30), ((pConfig->BuildParameters.SpiMode & 1) << 18) + ((pConfig->BuildParameters.SpiMode & 6) << 28));
- }
-
-// if ( cimSpiFastReadSpeed ) {
-// RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT15 + BIT14), ( cimSpiFastReadSpeed << 14));
-// }
- //Program power on pci init table
- programPciByteTable ( (REG8MASK*) FIXUP_PTR (&sbPorInitPciTable[0]), sizeof (sbPorInitPciTable) / sizeof (REG8MASK) );
-
- programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr));
-
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint32 | S3_SAVE, 0xFFFFFF00, 0);
-
- if (pConfig->SATAMODE.SataModeReg == 0) {
- pConfig->SATAMODE.SataModeReg = (pConfig->SATAMODE.SataMode.SataController << 0) \
- + (pConfig->SATAMODE.SataMode.SataIdeCombMdPriSecOpt << 1) \
- + (pConfig->SATAMODE.SataMode.SataSetMaxGen2 << 2) \
- + (pConfig->SATAMODE.SataMode.SataIdeCombinedMode << 3) \
- + (pConfig->SATAMODE.SataMode.SataClkMode << 4);
- }
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0x00, pConfig->SATAMODE.SataModeReg);
-
- if (dbEfuse & BIT0) {
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0xFB, 0x04);
- }
-
- ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, &dbPortStatus);
- if ( ((dbPortStatus & 0xF0) == 0x10) ) {
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_PMIOA_REG08, AccWidthUint8, 0, BIT5);
- }
-
- if ( pConfig->BuildParameters.LegacyFree ) {
- RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000);
- } else {
- RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5);
- }
-
- if ( cimSataInternal100Spread ) {
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1E, AccWidthUint8, 0xFF, BIT4);
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG84), AccWidthUint32, 0xFFFFFFFB, 0x00);
- } else {
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1E, AccWidthUint8, ~BIT4, 0x00);
- }
- // Toggle GEVENT4 to reset all GPP devices
- sbGppTogglePcieReset (pConfig);
-
- if ( cimSataInternal100Spread ) {
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG84), AccWidthUint32, 0xFFFFFFFF, 0x04);
- }
-
- dbValue = 0x08;
- WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue);
- ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
- if ( !pConfig->BuildParameters.EcKbd ) {
- // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
- dbValue = dbValue | 0x0A;
- }
- WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
-
- dbValue = 0x09;
- WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue);
- ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
- if ( !pConfig->BuildParameters.EcKbd ) {
- // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
- dbValue = dbValue & 0xF9;
- }
- if ( pConfig->BuildParameters.LegacyFree ) {
- // Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation.
- dbValue = dbValue & 0x9F;
- }
- // Enabled IRQ input
- dbValue = dbValue | BIT4;
- WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
-
- dwAsfPort = ((UINT16) pConfig->BuildParameters.Smbus1BaseAddress & 0xFFF0);
- if ( dwAsfPort != 0 ) {
- RWIO (dwAsfPort + 0x0E, AccWidthUint8, 0x0, 0x70); // 0x70 will change to EQU ( Remote control address)
- }
-
-#ifndef NO_EC_SUPPORT
- getChipSysMode (&dbPortStatus);
- if ( ((dbPortStatus & ChipSysEcEnable) == 0x00) ) {
- // EC is disabled by jumper setting or board config
- RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4), AccWidthUint16 | S3_SAVE, 0xFFFE, BIT0);
- } else {
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xF7, 0x08);
- ecPowerOnInit ( pConfig);
- imcSleep ( pConfig);
- }
-#endif
-
-
- ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue);
- ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue);
- if ( ddValue == 0x78121022 ) {
-//
-// First Xhci controller.
-//
- ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue);
- ddValue = 0;
- indexValue = XHCI_REGISTER_BAR03;
- WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
- ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
- ddValue = (UINT32) dbValue;
-
- indexValue = XHCI_REGISTER_BAR02;
- WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
- ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
- ddValue <<= 8;
- ddValue |= (UINT32) dbValue;
-
- indexValue = XHCI_REGISTER_BAR01;
- WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
- ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
- ddValue <<= 8;
- ddValue |= (UINT32) dbValue;
-
- indexValue = XHCI_REGISTER_BAR00;
- WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
- ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
- ddValue <<= 8;
- ddValue |= (UINT32) dbValue;
- WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x10, AccWidthUint32, &ddValue);
-
- indexValue = XHCI_REGISTER_04H;
- WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
- ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
- WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x04, AccWidthUint8, &dbValue);
-
- indexValue = XHCI_REGISTER_0CH;
- WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
- ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
- WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x0C, AccWidthUint8, &dbValue);
-
- indexValue = XHCI_REGISTER_3CH;
- WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
- ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
- WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x3C, AccWidthUint8, &dbValue);
-//
-// Second Xhci controller.
-//
- ReadPCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue);
- ddValue = 0;
- indexValue = XHCI1_REGISTER_BAR03;
- WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
- ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
- ddValue = (UINT32) dbValue;
-
- indexValue = XHCI1_REGISTER_BAR02;
- WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
- ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
- ddValue <<= 8;
- ddValue |= (UINT32) dbValue;
-
- indexValue = XHCI1_REGISTER_BAR01;
- WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
- ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
- ddValue <<= 8;
- ddValue |= (UINT32) dbValue;
-
- indexValue = XHCI1_REGISTER_BAR00;
- WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
- ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
- ddValue <<= 8;
- ddValue |= (UINT32) dbValue;
- WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x10, AccWidthUint32, &ddValue);
-
- indexValue = XHCI1_REGISTER_04H;
- WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
- ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
- WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x04, AccWidthUint8, &dbValue);
-
- indexValue = XHCI1_REGISTER_0CH;
- WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
- ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
- WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x0C, AccWidthUint8, &dbValue);
-
- indexValue = XHCI1_REGISTER_3CH;
- WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
- ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
- WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x3C, AccWidthUint8, &dbValue);
- }
- // RPR 3.2 Enabling SPI ROM Prefetch
- // Set LPC cfg 0xBA bit 8
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBA, AccWidthUint16 | S3_SAVE, 0xFFFF, BIT8);
- if (IsSbA12Plus ()) {
- // Enable SPI Prefetch for USB, set LPC cfg 0xBA bit 7 to 1 for A12 and above
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBA, AccWidthUint16 | S3_SAVE, 0xFFFF, BIT7);
- }
-#ifdef XHCI_SUPPORT
-#ifdef XHCI_INIT_IN_ROM_SUPPORT
- if ( pConfig->XhciSwitch == 1 ) {
- if ( pConfig->S3Resume == 0 ) {
- XhciEarlyInit ();
- } else {
- XhciInitIndirectReg ();
- }
- } else {
- // for power saving.
-
- // add Efuse checking for Xhci enable/disable
- getEfuseStatus (&XhciEfuse);
- if ((XhciEfuse & (BIT0 + BIT1)) != (BIT0 + BIT1)) {
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFBFF, 0x0);
- }
- }
-#endif
-#endif
-}
-
-#ifdef XHCI_SUPPORT
-VOID
-XhciInitIndirectReg (
- )
-{
- UINT32 ddDrivingStrength;
- UINT32 port;
- ddDrivingStrength = 0;
- port = 0;
-#ifdef SB_USB_BATTERY_CHARGE_SUPPORT
- RWXhciIndReg ( 0x40000018, 0xFFFFFFFF, 0x00000030);
-#endif
-//
-// RPR SuperSpeed PHY Configuration (adaptation mode setting)
-//
- RWXhciIndReg ( SB_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021);
- RWXhciIndReg ( SB_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021);
-//
-// RPR SuperSpeed PHY Configuration (CR phase and frequency filter settings)
-//
- RWXhciIndReg ( SB_XHCI_IND_REG98, 0xFFFFFFC0, 0x0000000A);
- RWXhciIndReg ( SB_XHCI_IND_REGD8, 0xFFFFFFC0, 0x0000000A);
-
-//
-// RPR BLM Meaasge
-//
- RWXhciIndReg ( SB_XHCI_IND_REG00, 0xF8FFFFFF, 0x07000000);
-//
-// RPR 8.13 xHCI USB 2.0 PHY Settings
-// Step 1 is done by hardware default
-// Step 2
-#ifdef USB3_EHCI_DRIVING_STRENGTH
- for (port = 0; port < 4; port ++) {
- ddDrivingStrength = (USB3_EHCI_DRIVING_STRENGTH >> (port * 4)) & 0xF;
- if (ddDrivingStrength & BIT3) {
- ddDrivingStrength &= 0x07;
- if (port < 2) {
- RWXhci0IndReg ( SB_XHCI_IND60_REG00, 0xFFFE0FF8, (port << 13) + ddDrivingStrength);
- RWXhci0IndReg ( SB_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000);
- } else {
- RWXhci1IndReg ( SB_XHCI_IND60_REG00, 0xFFFE0FF8, (port << 13) + ddDrivingStrength);
- RWXhci1IndReg ( SB_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000);
- }
- }
- }
-#endif
-
-// Step 3
- if (IsSbA11 ()) {
- RWXhciIndReg ( SB_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x00 << 8)));
- RWXhciIndReg ( SB_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x15 << 8)));
- } else {
- RWXhciIndReg ( SB_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8)));
- RWXhciIndReg ( SB_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x0f << 8)));
- }
-}
-
-VOID
-XhciEarlyInit (
- )
-{
- UINT16 BcdAddress;
- UINT16 BcdSize;
- UINT16 AcdAddress;
- UINT16 AcdSize;
- UINT16 FwAddress;
- UINT16 FwSize;
- UINTN XhciFwStarting;
- UINT32 SpiValidBase;
- UINT32 RegData;
- UINT16 i;
-
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0x00000000, 0x00400700);
- SbStall (20);
-//
-// Get ROM SIG starting address for USB firmware starting address (offset 0x0C to SIG address)
-//
- GetRomSigPtr (&XhciFwStarting);
-
- if (XhciFwStarting == 0) {
- return;
- }
-
- XhciFwStarting = ACPIMMIO32 (XhciFwStarting + FW_TO_SIGADDR_OFFSET);
- if (IsLpcRom ()) {
- //XHCI firmware re-load
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGCC, AccWidthUint32 | S3_SAVE, ~BIT2, (BIT2 + BIT1 + BIT0));
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGCC, AccWidthUint32 | S3_SAVE, 0x00000FFF, (UINT32) (XhciFwStarting));
- }
-//
-// RPR Enable SuperSpeed receive special error case logic. 0x20 bit8
-// RPR Enable USB2.0 RX_Valid Synchronization. 0x20 bit9
-// Enable USB2.0 DIN/SE0 Synchronization. 0x20 bit10
-//
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccWidthUint32, 0xFFFFF8FF, 0x00000700);
-//
-// RPR SuperSpeed PHY Configuration (adaptation timer setting)
-//
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccWidthUint32, 0xFFF00000, 0x000AAAAA);
- //RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90 + 0x40, AccWidthUint32, 0xFFF00000, 0x000AAAAA);
-
-//
-// Step 1. to enable Xhci IO and Firmware load mode
-//
-
-#ifdef XHCI_SUPPORT_ONE_CONTROLLER
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFFFC, 0x00000001);
-#else
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFFFC, 0x00000003);
-#endif
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xEFFFFFFF, 0x10000000);
-
-//
-// Step 2. to read a portion of the USB3_APPLICATION_CODE from BIOS ROM area and program certain registers.
-//
-
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA0, AccWidthUint32, 0x00000000, (SPI_HEAD_LENGTH << 16));
-
- BcdAddress = ACPIMMIO16 (XhciFwStarting + BCD_ADDR_OFFSET);
- BcdSize = ACPIMMIO16 (XhciFwStarting + BCD_SIZE_OFFSET);
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4, AccWidthUint16, 0x0000, BcdAddress);
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4 + 2, AccWidthUint16, 0x0000, BcdSize);
-
- AcdAddress = ACPIMMIO16 (XhciFwStarting + ACD_ADDR_OFFSET);
- AcdSize = ACPIMMIO16 (XhciFwStarting + ACD_SIZE_OFFSET);
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8, AccWidthUint16, 0x0000, AcdAddress);
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8 + 2, AccWidthUint16, 0x0000, AcdSize);
-
- SpiValidBase = SPI_BASE2 (XhciFwStarting + 4) | SPI_BAR0_VLD | SPI_BASE0 | SPI_BAR1_VLD | SPI_BASE1 | SPI_BAR2_VLD;
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB0, AccWidthUint32, 0x00000000, SpiValidBase);
-
- //
- // Copy Type0/1/2 data block from ROM image to MMIO starting from 0xC0
- //
- for (i = 0; i < SPI_HEAD_LENGTH; i++) {
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + i));
- }
-
- for (i = 0; i < BcdSize; i++) {
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + BcdAddress + i));
- }
-
- for (i = 0; i < AcdSize; i++) {
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + BcdSize + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + AcdAddress + i));
- }
-
-//
-// Step 3. to enable the instruction RAM preload functionality.
-//
- FwAddress = ACPIMMIO16 (XhciFwStarting + FW_ADDR_OFFSET);
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccWidthUint16, 0x0000, ACPIMMIO16 (XhciFwStarting + FwAddress));
- FwAddress += 2;
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04, AccWidthUint16, 0x0000, FwAddress);
-
- FwSize = ACPIMMIO16 (XhciFwStarting + FW_SIZE_OFFSET);
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04 + 2, AccWidthUint16, 0x0000, FwSize);
-
- //
- // Set the starting address offset for Instruction RAM preload.
- //
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG08, AccWidthUint16, 0x0000, 0);
-
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~BIT29, BIT29);
-
- for (;;) {
- ReadMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccWidthUint32, &RegData);
- if (RegData & BIT30) break;
- }
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~BIT29, 0);
-
-//
-// Step 4. to release resets in XHCI_ACPI_MMIO_AMD_REG00. wait for USPLL to lock by polling USPLL lock.
-//
-
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3PLL_RESET, 0); //Release U3PLLreset
- for (;;) {
- ReadMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccWidthUint32, &RegData);
- if (RegData & U3PLL_LOCK) break;
- }
-
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3PHY_RESET, 0); //Release U3PHY
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3CORE_RESET, 0); //Release core reset
-
-// RPR 8.8 SuperSpeed PHY Configuration, it is only for A11.
- if (IsSbA11 ()) {
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccWidthUint32, 0xFFF00000, 0x000AAAAA); //
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGD0, AccWidthUint32, 0xFFF00000, 0x000AAAAA); //
- }
-
- XhciInitIndirectReg ();
-
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, ~(BIT4 + BIT5), 0); // Disable Device 22
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, ~(BIT7), BIT7); // Enable 2.0 devices
- //if (!(pConfig->S4Resume)) {
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~(BIT21), BIT21); //SMI
- //}
-//
-// Step 5.
-//
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~(BIT17 + BIT18 + BIT19), BIT17 + BIT18);
-}
-#endif
diff --git a/src/vendorcode/amd/cimx/sb900/SbPort.c b/src/vendorcode/amd/cimx/sb900/SbPort.c
new file mode 100644
index 0000000..90e878e
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/SbPort.c
@@ -0,0 +1,737 @@
+
+/**
+ * @file
+ *
+ * Southbridge Init during POWER-ON
+ *
+ * Prepare Southbridge environment during power on stage.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$ @e \$Date:$
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; * Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; * Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; * Neither the name of Advanced Micro Devices, Inc. nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*********************************************************************************/
+
+#include "SbPlatform.h"
+#include "cbtypes.h"
+#include "AmdSbLib.h"
+#include "Hudson-2.h"
+
+/**
+ * sbPorInitPciTable - PCI device registers initial during the power on stage.
+ *
+ *
+ *
+ *
+ */
+REG8MASK sbPorInitPciTable[] =
+{
+ // SATA device
+ {0x00, SATA_BUS_DEV_FUN, 0},
+ {SB_SATA_REG84 + 3, ~BIT2, 0},
+ {SB_SATA_REGA0, ~(BIT2 + BIT3 + BIT4 + BIT5 + BIT6), BIT2 + BIT3 + BIT4 + BIT5},
+ {0xFF, 0xFF, 0xFF},
+ // LPC Device (Bus 0, Dev 20, Func 3)
+ {0x00, LPC_BUS_DEV_FUN, 0},
+ {SB_LPC_REG44, 0xFF, BIT6 + BIT7}, //Enable COM1 and COM2
+ {SB_LPC_REG47, 0xFF, BIT5},
+ {SB_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2},
+ {SB_LPC_REG7C, 0x00, BIT0 + BIT2},
+ {SB_LPC_REG78, 0xF0, BIT2 + BIT3}, // Enable LDRQ pin
+ {SB_LPC_REGBB, 0xFF, BIT3 + BIT4 + BIT5},
+ // A12 set 0xBB [5:3] = 111 to improve SPI timing margin.
+ // A12 Set 0xBA [6:5] = 11 improve SPI timing margin. (SPI Prefetch enhancement)
+ {SB_LPC_REGBB, 0xBE, BIT0 + BIT3 + BIT4 + BIT5},
+ {SB_LPC_REGBA, 0x9F, BIT5 + BIT6},
+ {SB_LPC_REGA4, ~ BIT0, BIT0}, //[BUG Fix] Force EC_PortActive to 1 to fix possible IR non function issue when NO_EC_SUPPORT is defined
+ {0xFF, 0xFF, 0xFF},
+ // P2P Bridge (Bus 0, Dev 20, Func 4)
+ {0x00, PCIB_BUS_DEV_FUN, 0},
+ {SB_PCIB_REG4B, 0xFF, BIT6 + BIT7 + BIT4},
+ // ENH230012: Disable P2P bridge decoder for IO address 0x1000-0x1FFF in SBPOR
+ // ENH260809: Add PCI port 80 support in Hudson-2/3
+#ifdef SB_PCIB_PORT_80_SUPPORT
+ {SB_PCIB_REG1C, 0x00, 0xF0},
+ {SB_PCIB_REG1D, 0x00, 0x00},
+ {SB_PCIB_REG04, 0x00, 0x21},
+#endif
+ {SB_PCIB_REG40, 0xDF, 0x20},
+ {SB_PCIB_REG50, 0x02, 0x01},
+ {0xFF, 0xFF, 0xFF},
+};
+
+/**
+ * sbPmioPorInitTable - Southbridge ACPI MMIO initial during the power on stage.
+ *
+ *
+ *
+ *
+ */
+AcpiRegWrite sbPmioPorInitTable[] =
+{
+ {00, 00, 0xB0, 0xAC}, // Signature
+ {MISC_BASE >> 8, SB_MISC_REG41, 0x1F, 0x40}, //keep Auxiliary_14Mclk_Sel [12]
+ //RPR 8.9 USB 3.0 Reference Clock MISC_REG 0x40 [4] = 0 Enable spread-spectrum reference clock.
+ {MISC_BASE >> 8, SB_MISC_REG40, 0xEF, 0x00},
+// {MISC_BASE >> 8, 0x24 + 2, 0xFF, 0x20}, Testing CPU clk strength
+ {PMIO_BASE >> 8, SB_PMIOA_REG5D, 0x00, BIT0},
+ {PMIO_BASE >> 8, SB_PMIOA_REGD2, 0xCF, BIT4 + BIT5},
+ {SMBUS_BASE >> 8, SB_SMBUS_REG12, 0x00, BIT0},
+ {PMIO_BASE >> 8, SB_PMIOA_REG28, 0xFF, BIT0 + BIT2},
+ {PMIO_BASE >> 8, SB_PMIOA_REG44 + 3, 0x67, BIT7 + BIT3}, // 2.5 Enable Boot Timer
+ {PMIO_BASE >> 8, SB_PMIOA_REG48, 0xFF, BIT0},
+ {PMIO_BASE >> 8, SB_PMIOA_REG00, 0xFF, 0x0E},
+ {PMIO_BASE >> 8, SB_PMIOA_REG00 + 2, 0xFF, 0x40},
+ {PMIO_BASE >> 8, SB_PMIOA_REG00 + 3, 0xFF, 0x08},
+ {PMIO_BASE >> 8, SB_PMIOA_REG34, 0xEF, BIT0 + BIT1},
+ {PMIO_BASE >> 8, SB_PMIOA_REGEC, 0xFD, BIT1},
+ //{PMIO_BASE >> 8, SB_PMIOA_REG5B, 0xF9, BIT1 + BIT2},
+ {PMIO_BASE >> 8, SB_PMIOA_REG08, 0xFE, BIT2 + BIT4},
+ {PMIO_BASE >> 8, SB_PMIOA_REG08 + 1, 0xFF, BIT0},
+ {PMIO_BASE >> 8, SB_PMIOA_REG54, 0x00, BIT4 + BIT6 + BIT7},
+ {PMIO_BASE >> 8, SB_PMIOA_REG04 + 3, 0xFD, BIT1},
+ {PMIO_BASE >> 8, SB_PMIOA_REG74, 0xF6, BIT0 + BIT3},
+ {PMIO_BASE >> 8, SB_PMIOA_REGF0, ~BIT2, 0x00},
+ // RPR GEC I/O Termination Setting
+ // PM_Reg 0xF6 = Power-on default setting
+ // PM_Reg 0xF7 = Power-on default setting
+ // PM_Reg 0xF8 = 0x6C
+ // PM_Reg 0xF9 = 0x21
+ // PM_Reg 0xFA = 0x00 Hudson-2 A12 GEC I/O Pad settings for 3.3V CMOS
+ {PMIO_BASE >> 8, SB_PMIOA_REGF8, 0x00, 0x6C},
+ {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 1, 0x00, 0x07},
+ {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 2, 0x00, 0x00},
+ // PRP GEC -end
+ {PMIO_BASE >> 8, SB_PMIOA_REGC4, 0xee, 0x04}, // Release NB_PCIE_RST
+ {PMIO_BASE >> 8, SB_PMIOA_REGC0 + 2, 0xBF, 0x40},
+
+ {PMIO_BASE >> 8, SB_PMIOA_REGBE, 0xDF, BIT5},
+
+ //OBS200280
+ //{PMIO_BASE >> 8, SB_PMIOA_REGBE, 0xFF, BIT1},
+
+
+ {0xFF, 0xFF, 0xFF, 0xFF},
+};
+
+/**
+ * sbPowerOnInit - Config Southbridge during power on stage.
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+sbPowerOnInit (
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT8 dbPortStatus;
+ //UINT8 dbSysConfig;
+ UINT32 abValue;
+ UINT32 abValue2;
+ UINT8 dbValue;
+ UINT8 dbEfuse;
+ UINT32 dbSpiMode;
+ UINT16 dwAsfPort;
+ UINT16 smbusBase;
+ UINT8 cimSataMode;
+// UINT8 cimSpiFastReadEnable;
+// UINT8 cimSpiFastReadSpeed;
+ UINT8 cimSataInternal100Spread;
+ UINT8 indexValue;
+ UINT32 ddValue;
+ UINT8 SataPortNum;
+ UINT8 XhciEfuse;
+ XhciEfuse = XHCI_EFUSE_LOCATION;
+
+ cimSataMode = pConfig->SATAMODE.SataModeReg;
+// if (pConfig->BuildParameters.SpiFastReadEnable != NULL ) {
+// cimSpiFastReadEnable = (UINT8) pConfig->BuildParameters.SpiFastReadEnable;
+// } else {
+// cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
+// }
+// cimSpiFastReadSpeed = (UINT8) pConfig->BuildParameters.SpiFastReadSpeed;
+ cimSataInternal100Spread = ( UINT8 ) pConfig->SataInternal100Spread;
+
+#if SB_CIMx_PARAMETER == 0
+ cimSataMode = (UINT8) ((cimSataMode & 0xFB) | cimSataSetMaxGen2Default);
+ cimSataMode = (UINT8) ((cimSataMode & 0x0F) | cimSataClkModeDefault);
+ cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
+ cimSpiFastReadSpeed = cimSpiFastReadSpeedDefault;
+ cimSataInternal100Spread = SataInternal100SpreadDefault;
+#endif
+
+ TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbPowerOnInit \n"));
+
+// Hudson-2 Only Enabled (Mmio_mem_enablr) // Default value is correct
+ RWPMIO (SB_PMIOA_REG24, AccWidthUint8, 0xFF, BIT0);
+
+ RWPMIO (0xD3, AccWidthUint8, ~BIT4, 0);
+ RWPMIO (0xD3, AccWidthUint8, ~BIT4, BIT4);
+
+ if ( pConfig->Cg2Pll == 1 ) {
+ TurnOffCG2 ();
+ pConfig->SATAMODE.SataMode.SataClkMode = 0x0a;
+ }
+
+ //enable CF9
+ RWPMIO (0xD2, AccWidthUint8, ~BIT6, 0);
+
+// Set A-Link bridge access address. This address is set at device 14h, function 0,
+// register 0f0h. This is an I/O address. The I/O address must be on 16-byte boundary.
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGE0, AccWidthUint32, 00, ALINK_ACCESS_INDEX);
+ writeAlink (0x80000004, 0x04); // RPR 4.2 Enable Hudson-2 to issue memory read/write requests in the upstream direction
+ abValue = readAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29)); // RPR 4.5 Disable the credit variable in the downstream arbitration equation
+ abValue = abValue | BIT0;
+ writeAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29), abValue);
+ writeAlink (0x30, 0x10); // AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform.
+ writeAlink (0x34, readAlink (0x34) | BIT9);
+ rwAlink (SB_ABCFG_REG10050 | (UINT32) (ABCFG << 29), ~BIT2, 0x00);
+
+ // Enable external Stickybit register reset feature
+ //writeAlink (SB_AX_INDXC_REG30 | (UINT32) (AXINDC << 29), 0x30);
+ //abValue = readAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29));
+ //abValue |= BIT6 + BIT5;
+ //writeAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29), abValue);
+
+ // Configure UMI target link speed
+ dbEfuse = PCIE_FORCE_GEN1_EFUSE_LOCATION;
+ getEfuseStatus (&dbEfuse);
+ if ( dbEfuse & BIT0 ) {
+ pConfig->NbSbGen2 = 0;
+ }
+
+ dbEfuse = FCH_Variant_EFUSE_LOCATION;
+ getEfuseStatus (&dbEfuse);
+ if ((dbEfuse == 0x07) || (dbEfuse == 0x08)) {
+ pConfig->NbSbGen2 = 0;
+ }
+
+ if (pConfig->NbSbGen2) {
+ abValue = 2;
+ abValue2 = BIT0;
+ } else {
+ abValue = 1;
+ abValue2 = 0;
+ }
+ rwAlink (SB_AX_INDXP_REGA4, 0xFFFFFFFE, abValue2);
+ rwAlink ((UINT32)SB_AX_CFG_REG88, 0xFFFFFFF0, abValue);
+
+ if (pConfig->sdbEnable) {
+ rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~BIT12, 0x00);
+ RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 0, AccWidthUint8, 0, pConfig->Debug_Reg00);
+ RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 2, AccWidthUint8, 0, pConfig->Debug_Reg02);
+ RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 4, AccWidthUint8, 0, pConfig->Debug_Reg04);
+ RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 1, AccWidthUint8, 0, pConfig->Debug_Reg01);
+ RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 3, AccWidthUint8, 0, pConfig->Debug_Reg03);
+ RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 5, AccWidthUint8, 0, pConfig->Debug_Reg05);
+ }
+
+// Set Build option into SB
+ WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioPmeBaseAddress));
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F, (pConfig->BuildParameters.SpiRomBaseAddress));
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint32 | S3_SAVE, 0, (pConfig->BuildParameters.GecShadowRomBase + 1));
+// Enabled SMBUS0/SMBUS1 (ASF) Base Address
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2C, AccWidthUint16, 06, (pConfig->BuildParameters.Smbus0BaseAddress) + BIT0); //protect BIT[2:1]
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG28, AccWidthUint16, 06, (pConfig->BuildParameters.Smbus1BaseAddress) + BIT0);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG60, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1EvtBlkAddr));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG62, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1CntBlkAddr));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmTmrBlkAddr));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG66, AccWidthUint16, 00, (pConfig->BuildParameters.CpuControlBlkAddr));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG68, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiGpe0BlkAddr));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6A, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6C, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmaCntBlkAddr));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6E, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr) + 8);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG48, AccWidthUint32, 00, (pConfig->BuildParameters.WatchDogTimerBase));
+
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2E, AccWidthUint8, ~(BIT1 + BIT2), 0); //clear BIT[2:1]
+ smbusBase = (UINT16) (pConfig->BuildParameters.Smbus0BaseAddress);
+ dbValue = 0x00;
+ WriteIO (smbusBase + 0x14, AccWidthUint8, &dbValue);
+
+ dbEfuse = SATA_FIS_BASE_EFUSE_LOC;
+ getEfuseStatus (&dbEfuse);
+
+ programSbAcpiMmioTbl ((AcpiRegWrite*) FIXUP_PTR (&sbPmioPorInitTable[0]));
+
+ //RPR 3.4 Enabling ClkRun Function
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBB, AccWidthUint8, ~ BIT2, BIT2);
+ //BUG265683: Mismatch clkrun enable register setting between RPR and CIMX code
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGD0, AccWidthUint8, ~ BIT2, 0);
+
+ SataPortNum = 0;
+ for ( SataPortNum = 0; SataPortNum < 0x06; SataPortNum++ ) {
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, 1 << SataPortNum);
+ SbStall (2);
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, (0xFF ^ (1 << SataPortNum)) , 0x00);
+ SbStall (2);
+ }
+
+ dbValue = 0x0A;
+ WriteIO (SB_IOMAP_REG70, AccWidthUint8, &dbValue);
+ ReadIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
+ dbValue &= 0xEF;
+ WriteIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
+
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, (BIT19 + BIT24 + BIT25 + BIT26));
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, 0xFFC0FFFF, 0 );
+ if (pConfig->BuildParameters.SpiSpeed) {
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, ~(BIT13 + BIT12), ((pConfig->BuildParameters.SpiSpeed - 1 ) << 12));
+ }
+ if (pConfig->BuildParameters.SpiFastSpeed) {
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, ~(BIT15 + BIT14), ((pConfig->BuildParameters.SpiFastSpeed - 1 ) << 14));
+ }
+ //if (pConfig->BuildParameters.SpiBurstWrite) {
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG1C, AccWidthUint32 | S3_SAVE, ~(BIT10), ((pConfig->BuildParameters.SpiBurstWrite) << 10));
+ //}
+ dbSpiMode = pConfig->BuildParameters.SpiMode;
+ if (pConfig->BuildParameters.SpiMode) {
+ if ((dbSpiMode == SB_SPI_MODE_QUAL_114) || (dbSpiMode == SB_SPI_MODE_QUAL_112) || (dbSpiMode == SB_SPI_MODE_QUAL_144) || (dbSpiMode == SB_SPI_MODE_QUAL_122)) {
+ // RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFF0000, 0x013e);
+ // RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, 0xFFFFFF00, 0x80 );
+ // RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFEFFFF, 0x10000);
+ // SbStall (1000);
+ }
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, ~( BIT18 + BIT29 + BIT30), ((pConfig->BuildParameters.SpiMode & 1) << 18) + ((pConfig->BuildParameters.SpiMode & 6) << 28));
+ }
+
+// if ( cimSpiFastReadSpeed ) {
+// RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT15 + BIT14), ( cimSpiFastReadSpeed << 14));
+// }
+ //Program power on pci init table
+ programPciByteTable ( (REG8MASK*) FIXUP_PTR (&sbPorInitPciTable[0]), sizeof (sbPorInitPciTable) / sizeof (REG8MASK) );
+
+ programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr));
+
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint32 | S3_SAVE, 0xFFFFFF00, 0);
+
+ if (pConfig->SATAMODE.SataModeReg == 0) {
+ pConfig->SATAMODE.SataModeReg = (pConfig->SATAMODE.SataMode.SataController << 0) \
+ + (pConfig->SATAMODE.SataMode.SataIdeCombMdPriSecOpt << 1) \
+ + (pConfig->SATAMODE.SataMode.SataSetMaxGen2 << 2) \
+ + (pConfig->SATAMODE.SataMode.SataIdeCombinedMode << 3) \
+ + (pConfig->SATAMODE.SataMode.SataClkMode << 4);
+ }
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0x00, pConfig->SATAMODE.SataModeReg);
+
+ if (dbEfuse & BIT0) {
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0xFB, 0x04);
+ }
+
+ ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, &dbPortStatus);
+ if ( ((dbPortStatus & 0xF0) == 0x10) ) {
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_PMIOA_REG08, AccWidthUint8, 0, BIT5);
+ }
+
+ if ( pConfig->BuildParameters.LegacyFree ) {
+ RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000);
+ } else {
+ RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5);
+ }
+
+ if ( cimSataInternal100Spread ) {
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1E, AccWidthUint8, 0xFF, BIT4);
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG84), AccWidthUint32, 0xFFFFFFFB, 0x00);
+ } else {
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1E, AccWidthUint8, ~BIT4, 0x00);
+ }
+ // Toggle GEVENT4 to reset all GPP devices
+ sbGppTogglePcieReset (pConfig);
+
+ if ( cimSataInternal100Spread ) {
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG84), AccWidthUint32, 0xFFFFFFFF, 0x04);
+ }
+
+ dbValue = 0x08;
+ WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue);
+ ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
+ if ( !pConfig->BuildParameters.EcKbd ) {
+ // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
+ dbValue = dbValue | 0x0A;
+ }
+ WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
+
+ dbValue = 0x09;
+ WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue);
+ ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
+ if ( !pConfig->BuildParameters.EcKbd ) {
+ // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
+ dbValue = dbValue & 0xF9;
+ }
+ if ( pConfig->BuildParameters.LegacyFree ) {
+ // Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation.
+ dbValue = dbValue & 0x9F;
+ }
+ // Enabled IRQ input
+ dbValue = dbValue | BIT4;
+ WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
+
+ dwAsfPort = ((UINT16) pConfig->BuildParameters.Smbus1BaseAddress & 0xFFF0);
+ if ( dwAsfPort != 0 ) {
+ RWIO (dwAsfPort + 0x0E, AccWidthUint8, 0x0, 0x70); // 0x70 will change to EQU ( Remote control address)
+ }
+
+#ifndef NO_EC_SUPPORT
+ getChipSysMode (&dbPortStatus);
+ if ( ((dbPortStatus & ChipSysEcEnable) == 0x00) ) {
+ // EC is disabled by jumper setting or board config
+ RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4), AccWidthUint16 | S3_SAVE, 0xFFFE, BIT0);
+ } else {
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xF7, 0x08);
+ ecPowerOnInit ( pConfig);
+ imcSleep ( pConfig);
+ }
+#endif
+
+
+ ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue);
+ ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue);
+ if ( ddValue == 0x78121022 ) {
+//
+// First Xhci controller.
+//
+ ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue);
+ ddValue = 0;
+ indexValue = XHCI_REGISTER_BAR03;
+ WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+ ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+ ddValue = (UINT32) dbValue;
+
+ indexValue = XHCI_REGISTER_BAR02;
+ WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+ ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+ ddValue <<= 8;
+ ddValue |= (UINT32) dbValue;
+
+ indexValue = XHCI_REGISTER_BAR01;
+ WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+ ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+ ddValue <<= 8;
+ ddValue |= (UINT32) dbValue;
+
+ indexValue = XHCI_REGISTER_BAR00;
+ WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+ ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+ ddValue <<= 8;
+ ddValue |= (UINT32) dbValue;
+ WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x10, AccWidthUint32, &ddValue);
+
+ indexValue = XHCI_REGISTER_04H;
+ WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+ ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+ WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x04, AccWidthUint8, &dbValue);
+
+ indexValue = XHCI_REGISTER_0CH;
+ WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+ ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+ WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x0C, AccWidthUint8, &dbValue);
+
+ indexValue = XHCI_REGISTER_3CH;
+ WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+ ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+ WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x3C, AccWidthUint8, &dbValue);
+//
+// Second Xhci controller.
+//
+ ReadPCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue);
+ ddValue = 0;
+ indexValue = XHCI1_REGISTER_BAR03;
+ WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+ ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+ ddValue = (UINT32) dbValue;
+
+ indexValue = XHCI1_REGISTER_BAR02;
+ WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+ ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+ ddValue <<= 8;
+ ddValue |= (UINT32) dbValue;
+
+ indexValue = XHCI1_REGISTER_BAR01;
+ WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+ ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+ ddValue <<= 8;
+ ddValue |= (UINT32) dbValue;
+
+ indexValue = XHCI1_REGISTER_BAR00;
+ WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+ ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+ ddValue <<= 8;
+ ddValue |= (UINT32) dbValue;
+ WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x10, AccWidthUint32, &ddValue);
+
+ indexValue = XHCI1_REGISTER_04H;
+ WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+ ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+ WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x04, AccWidthUint8, &dbValue);
+
+ indexValue = XHCI1_REGISTER_0CH;
+ WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+ ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+ WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x0C, AccWidthUint8, &dbValue);
+
+ indexValue = XHCI1_REGISTER_3CH;
+ WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+ ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+ WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x3C, AccWidthUint8, &dbValue);
+ }
+ // RPR 3.2 Enabling SPI ROM Prefetch
+ // Set LPC cfg 0xBA bit 8
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBA, AccWidthUint16 | S3_SAVE, 0xFFFF, BIT8);
+ if (IsSbA12Plus ()) {
+ // Enable SPI Prefetch for USB, set LPC cfg 0xBA bit 7 to 1 for A12 and above
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBA, AccWidthUint16 | S3_SAVE, 0xFFFF, BIT7);
+ }
+#ifdef XHCI_SUPPORT
+#ifdef XHCI_INIT_IN_ROM_SUPPORT
+ if ( pConfig->XhciSwitch == 1 ) {
+ if ( pConfig->S3Resume == 0 ) {
+ XhciEarlyInit ();
+ } else {
+ XhciInitIndirectReg ();
+ }
+ } else {
+ // for power saving.
+
+ // add Efuse checking for Xhci enable/disable
+ getEfuseStatus (&XhciEfuse);
+ if ((XhciEfuse & (BIT0 + BIT1)) != (BIT0 + BIT1)) {
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFBFF, 0x0);
+ }
+ }
+#endif
+#endif
+}
+
+#ifdef XHCI_SUPPORT
+VOID
+XhciInitIndirectReg (
+ )
+{
+ UINT32 ddDrivingStrength;
+ UINT32 port;
+ ddDrivingStrength = 0;
+ port = 0;
+#ifdef SB_USB_BATTERY_CHARGE_SUPPORT
+ RWXhciIndReg ( 0x40000018, 0xFFFFFFFF, 0x00000030);
+#endif
+//
+// RPR SuperSpeed PHY Configuration (adaptation mode setting)
+//
+ RWXhciIndReg ( SB_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021);
+ RWXhciIndReg ( SB_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021);
+//
+// RPR SuperSpeed PHY Configuration (CR phase and frequency filter settings)
+//
+ RWXhciIndReg ( SB_XHCI_IND_REG98, 0xFFFFFFC0, 0x0000000A);
+ RWXhciIndReg ( SB_XHCI_IND_REGD8, 0xFFFFFFC0, 0x0000000A);
+
+//
+// RPR BLM Meaasge
+//
+ RWXhciIndReg ( SB_XHCI_IND_REG00, 0xF8FFFFFF, 0x07000000);
+//
+// RPR 8.13 xHCI USB 2.0 PHY Settings
+// Step 1 is done by hardware default
+// Step 2
+#ifdef USB3_EHCI_DRIVING_STRENGTH
+ for (port = 0; port < 4; port ++) {
+ ddDrivingStrength = (USB3_EHCI_DRIVING_STRENGTH >> (port * 4)) & 0xF;
+ if (ddDrivingStrength & BIT3) {
+ ddDrivingStrength &= 0x07;
+ if (port < 2) {
+ RWXhci0IndReg ( SB_XHCI_IND60_REG00, 0xFFFE0FF8, (port << 13) + ddDrivingStrength);
+ RWXhci0IndReg ( SB_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000);
+ } else {
+ RWXhci1IndReg ( SB_XHCI_IND60_REG00, 0xFFFE0FF8, (port << 13) + ddDrivingStrength);
+ RWXhci1IndReg ( SB_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000);
+ }
+ }
+ }
+#endif
+
+// Step 3
+ if (IsSbA11 ()) {
+ RWXhciIndReg ( SB_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x00 << 8)));
+ RWXhciIndReg ( SB_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x15 << 8)));
+ } else {
+ RWXhciIndReg ( SB_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8)));
+ RWXhciIndReg ( SB_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x0f << 8)));
+ }
+}
+
+VOID
+XhciEarlyInit (
+ )
+{
+ UINT16 BcdAddress;
+ UINT16 BcdSize;
+ UINT16 AcdAddress;
+ UINT16 AcdSize;
+ UINT16 FwAddress;
+ UINT16 FwSize;
+ UINTN XhciFwStarting;
+ UINT32 SpiValidBase;
+ UINT32 RegData;
+ UINT16 i;
+
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0x00000000, 0x00400700);
+ SbStall (20);
+//
+// Get ROM SIG starting address for USB firmware starting address (offset 0x0C to SIG address)
+//
+ GetRomSigPtr (&XhciFwStarting);
+
+ if (XhciFwStarting == 0) {
+ return;
+ }
+
+ XhciFwStarting = ACPIMMIO32 (XhciFwStarting + FW_TO_SIGADDR_OFFSET);
+ if (IsLpcRom ()) {
+ //XHCI firmware re-load
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGCC, AccWidthUint32 | S3_SAVE, ~BIT2, (BIT2 + BIT1 + BIT0));
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGCC, AccWidthUint32 | S3_SAVE, 0x00000FFF, (UINT32) (XhciFwStarting));
+ }
+//
+// RPR Enable SuperSpeed receive special error case logic. 0x20 bit8
+// RPR Enable USB2.0 RX_Valid Synchronization. 0x20 bit9
+// Enable USB2.0 DIN/SE0 Synchronization. 0x20 bit10
+//
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccWidthUint32, 0xFFFFF8FF, 0x00000700);
+//
+// RPR SuperSpeed PHY Configuration (adaptation timer setting)
+//
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccWidthUint32, 0xFFF00000, 0x000AAAAA);
+ //RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90 + 0x40, AccWidthUint32, 0xFFF00000, 0x000AAAAA);
+
+//
+// Step 1. to enable Xhci IO and Firmware load mode
+//
+
+#ifdef XHCI_SUPPORT_ONE_CONTROLLER
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFFFC, 0x00000001);
+#else
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFFFC, 0x00000003);
+#endif
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xEFFFFFFF, 0x10000000);
+
+//
+// Step 2. to read a portion of the USB3_APPLICATION_CODE from BIOS ROM area and program certain registers.
+//
+
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA0, AccWidthUint32, 0x00000000, (SPI_HEAD_LENGTH << 16));
+
+ BcdAddress = ACPIMMIO16 (XhciFwStarting + BCD_ADDR_OFFSET);
+ BcdSize = ACPIMMIO16 (XhciFwStarting + BCD_SIZE_OFFSET);
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4, AccWidthUint16, 0x0000, BcdAddress);
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4 + 2, AccWidthUint16, 0x0000, BcdSize);
+
+ AcdAddress = ACPIMMIO16 (XhciFwStarting + ACD_ADDR_OFFSET);
+ AcdSize = ACPIMMIO16 (XhciFwStarting + ACD_SIZE_OFFSET);
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8, AccWidthUint16, 0x0000, AcdAddress);
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8 + 2, AccWidthUint16, 0x0000, AcdSize);
+
+ SpiValidBase = SPI_BASE2 (XhciFwStarting + 4) | SPI_BAR0_VLD | SPI_BASE0 | SPI_BAR1_VLD | SPI_BASE1 | SPI_BAR2_VLD;
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB0, AccWidthUint32, 0x00000000, SpiValidBase);
+
+ //
+ // Copy Type0/1/2 data block from ROM image to MMIO starting from 0xC0
+ //
+ for (i = 0; i < SPI_HEAD_LENGTH; i++) {
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + i));
+ }
+
+ for (i = 0; i < BcdSize; i++) {
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + BcdAddress + i));
+ }
+
+ for (i = 0; i < AcdSize; i++) {
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + BcdSize + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + AcdAddress + i));
+ }
+
+//
+// Step 3. to enable the instruction RAM preload functionality.
+//
+ FwAddress = ACPIMMIO16 (XhciFwStarting + FW_ADDR_OFFSET);
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccWidthUint16, 0x0000, ACPIMMIO16 (XhciFwStarting + FwAddress));
+ FwAddress += 2;
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04, AccWidthUint16, 0x0000, FwAddress);
+
+ FwSize = ACPIMMIO16 (XhciFwStarting + FW_SIZE_OFFSET);
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04 + 2, AccWidthUint16, 0x0000, FwSize);
+
+ //
+ // Set the starting address offset for Instruction RAM preload.
+ //
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG08, AccWidthUint16, 0x0000, 0);
+
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~BIT29, BIT29);
+
+ for (;;) {
+ ReadMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccWidthUint32, &RegData);
+ if (RegData & BIT30) break;
+ }
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~BIT29, 0);
+
+//
+// Step 4. to release resets in XHCI_ACPI_MMIO_AMD_REG00. wait for USPLL to lock by polling USPLL lock.
+//
+
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3PLL_RESET, 0); //Release U3PLLreset
+ for (;;) {
+ ReadMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccWidthUint32, &RegData);
+ if (RegData & U3PLL_LOCK) break;
+ }
+
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3PHY_RESET, 0); //Release U3PHY
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3CORE_RESET, 0); //Release core reset
+
+// RPR 8.8 SuperSpeed PHY Configuration, it is only for A11.
+ if (IsSbA11 ()) {
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccWidthUint32, 0xFFF00000, 0x000AAAAA); //
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGD0, AccWidthUint32, 0xFFF00000, 0x000AAAAA); //
+ }
+
+ XhciInitIndirectReg ();
+
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, ~(BIT4 + BIT5), 0); // Disable Device 22
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, ~(BIT7), BIT7); // Enable 2.0 devices
+ //if (!(pConfig->S4Resume)) {
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~(BIT21), BIT21); //SMI
+ //}
+//
+// Step 5.
+//
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~(BIT17 + BIT18 + BIT19), BIT17 + BIT18);
+}
+#endif
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