[coreboot-gerrit] Patch set updated for coreboot: SB800: Port to 64bit

Stefan Reinauer (stefan.reinauer@coreboot.org) gerrit at coreboot.org
Fri Jun 19 07:27:47 CEST 2015


Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10582

-gerrit

commit d3215a087d6201f2f8ca30cdeec27e39ac617d18
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Thu Jun 18 01:17:38 2015 -0700

    SB800: Port to 64bit
    
    Change-Id: I944fb254e9470c80b13c9eef9d6b1177a56e615f
    Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
    Signed-off-by: Scott Duplichan <scott at notabs.org>
---
 src/southbridge/amd/cimx/sb800/fadt.c | 20 ++++++++++++++------
 src/southbridge/amd/cimx/sb800/late.c |  8 ++++----
 2 files changed, 18 insertions(+), 10 deletions(-)

diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c
index 70173b6..6a565b8 100644
--- a/src/southbridge/amd/cimx/sb800/fadt.c
+++ b/src/southbridge/amd/cimx/sb800/fadt.c
@@ -63,8 +63,16 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	memcpy(header->asl_compiler_id, ASLC, 4);
 	header->asl_compiler_revision = 0;
 
-	fadt->firmware_ctrl = (u32) facs;
-	fadt->dsdt = (u32) dsdt;
+	if ((uintptr_t)facs > 0xffffffff)
+		printk(BIOS_WARN, "ACPI: FACS lives above 4G\n");
+	else
+		fadt->firmware_ctrl = (uintptr_t)facs;
+
+	if ((uintptr_t)dsdt > 0xffffffff)
+		printk(BIOS_WARN, "ACPI: DSDT lives above 4G\n");
+	else
+		fadt->dsdt = (uintptr_t)dsdt;
+
 	fadt->model = 0;		/* reserved, should be 0 ACPI 3.0 */
 	fadt->preferred_pm_profile = FADT_PM_PROFILE;
 	fadt->sci_int = 9;		/* HUDSON 1 - IRQ 09 – ACPI SCI */
@@ -153,10 +161,10 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->res4 = 0;		/* reserved, MUST be 0 ACPI 3.0 */
 	fadt->res5 = 0;		/* reserved, MUST be 0 ACPI 3.0 */
 
-	fadt->x_firmware_ctl_l = 0;	/* set to 0 if firmware_ctrl is used */
-	fadt->x_firmware_ctl_h = 0;
-	fadt->x_dsdt_l = (u32) dsdt;
-	fadt->x_dsdt_h = 0;
+	fadt->x_firmware_ctl_l = ((uintptr_t)facs) & 0xffffffff;
+	fadt->x_firmware_ctl_h = ((uintptr_t)facs) >> 32;
+	fadt->x_dsdt_l = ((uintptr_t)dsdt) & 0xffffffff;
+	fadt->x_dsdt_h = ((uintptr_t)dsdt) >> 32;
 
 	fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 	fadt->x_pm1a_evt_blk.bit_width = 32;
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 0ada673..01900fe 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -108,15 +108,15 @@ static void ahci_raid_init(struct device *dev)
 	bar5 = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
 	printk(BIOS_DEBUG, "IOMEM base: 0x%X, IRQ: 0x%X\n", bar5, irq);
 
-	caps = *(volatile u32 *)(bar5 + HOST_CAP);
+	caps = *(volatile u32 *)((uintptr_t)bar5 + HOST_CAP);
 	caps = (caps & 0x1F) + 1;
-	ports= *(volatile u32 *)(bar5 + HOST_PORTS_IMPL);
+	ports= *(volatile u32 *)((uintptr_t)bar5 + HOST_PORTS_IMPL);
 	printk(BIOS_DEBUG, "Number of Ports: 0x%x, Port implemented(bit map): 0x%x\n", caps, ports);
 
 	/* make sure ahci is enabled */
-	val = *(volatile u32 *)(bar5 + HOST_CTL);
+	val = *(volatile u32 *)((uintptr_t)bar5 + HOST_CTL);
 	if (!(val & HOST_CTL_AHCI_EN)) {
-		*(volatile u32 *)(bar5 + HOST_CTL) = val | HOST_CTL_AHCI_EN;
+		*(volatile u32 *)((uintptr_t)bar5 + HOST_CTL) = val | HOST_CTL_AHCI_EN;
 	}
 
 	dev->command |= PCI_COMMAND_MASTER;



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