[coreboot-gerrit] New patch to review for coreboot: vendorcode: 64bit fixes for AMD CIMX SB800
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Thu Jun 18 10:24:38 CEST 2015
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10573
-gerrit
commit 0d1fde472585e13c524f693d009672dbc496e8df
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date: Wed Jun 17 16:05:05 2015 -0700
vendorcode: 64bit fixes for AMD CIMX SB800
Make SB800 code compile with x64 compiler
These fixes probably apply 1:1 to the other SB components
in that directory.
Change-Id: I9ff9f27dff5074d2faf41ebc14bfe50871d9c7f7
Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
Signed-off-by: Scott Duplichan <scott at notabs.org>
---
src/vendorcode/amd/cimx/sb800/ACPILIB.c | 4 ++--
src/vendorcode/amd/cimx/sb800/DISPATCHER.c | 8 ++------
src/vendorcode/amd/cimx/sb800/GEC.c | 2 +-
src/vendorcode/amd/cimx/sb800/MEMLIB.c | 20 ++++++++++----------
src/vendorcode/amd/cimx/sb800/Makefile.inc | 5 +++++
src/vendorcode/amd/cimx/sb800/SBMAIN.c | 2 +-
src/vendorcode/amd/cimx/sb800/SBPELIB.c | 2 +-
7 files changed, 22 insertions(+), 21 deletions(-)
diff --git a/src/vendorcode/amd/cimx/sb800/ACPILIB.c b/src/vendorcode/amd/cimx/sb800/ACPILIB.c
index bc11209..62cd3f8 100644
--- a/src/vendorcode/amd/cimx/sb800/ACPILIB.c
+++ b/src/vendorcode/amd/cimx/sb800/ACPILIB.c
@@ -56,14 +56,14 @@ ACPI_LocateTable (
UINT32 i;
UINT32* RsdPtr;
UINT32* Rsdt;
- UINTN tableOffset;
+ intptr_t tableOffset;
DESCRIPTION_HEADER* CurrentTable;
RsdPtr = (UINT32*) (UINTN)0xe0000;
Rsdt = NULL;
do {
if ( *RsdPtr == Int32FromChar('R', 'S', 'D', ' ') && *(RsdPtr + 1) == Int32FromChar('P', 'T', 'R', ' ')) {
- Rsdt = (UINT32*) (UINTN) ((RSDP*)RsdPtr)->RsdtAddress;
+ Rsdt = (UINT32*) (intptr_t) ((RSDP*)RsdPtr)->RsdtAddress;
break;
}
RsdPtr += 4;
diff --git a/src/vendorcode/amd/cimx/sb800/DISPATCHER.c b/src/vendorcode/amd/cimx/sb800/DISPATCHER.c
index 84bbccb..07afea2 100644
--- a/src/vendorcode/amd/cimx/sb800/DISPATCHER.c
+++ b/src/vendorcode/amd/cimx/sb800/DISPATCHER.c
@@ -183,11 +183,7 @@ LocateImage (
ImagePtr = 0xffffffff - (IMAGE_ALIGN - 1);
while ( ImagePtr >= (0xfffffff - (NUM_IMAGE_LOCATION * IMAGE_ALIGN - 1)) ) {
-#ifdef x64
- 12346789
-#else
- Result = VerifyImage (Signature, (VOID*) ImagePtr);
-#endif
+ Result = VerifyImage (Signature, (VOID*)(intptr_t)ImagePtr);
if ( Result != NULL ) {
return Result;
}
@@ -244,7 +240,7 @@ saveConfigPointer (
UINT8 i;
UINT32 ddValue;
- ddValue = (UINT32) (UINTN)pConfig;
+ ddValue = (UINT32) (intptr_t)pConfig; // Needs to live below 4G
dbReg = SB_ECMOS_REG08;
for ( i = 0; i <= 3; i++ ) {
diff --git a/src/vendorcode/amd/cimx/sb800/GEC.c b/src/vendorcode/amd/cimx/sb800/GEC.c
index d1715bc..8ce606c 100644
--- a/src/vendorcode/amd/cimx/sb800/GEC.c
+++ b/src/vendorcode/amd/cimx/sb800/GEC.c
@@ -115,7 +115,7 @@ gecInitAfterPciEnum (
WritePCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbTemp);
if ( pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr != NULL ) {
GecRomAddress = pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr;
- GecShadowRomAddress = (VOID*) (UINTN) pConfig->BuildParameters.GecShadowRomBase;
+ GecShadowRomAddress = (VOID*) (intptr_t) pConfig->BuildParameters.GecShadowRomBase;
AmdSbCopyMem (GecShadowRomAddress, GecRomAddress, 0x100);
ReadPCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG10, AccWidthUint32, &ddTemp);
ddTemp = ddTemp & 0xFFFFFFF0;
diff --git a/src/vendorcode/amd/cimx/sb800/MEMLIB.c b/src/vendorcode/amd/cimx/sb800/MEMLIB.c
index 5531c62..174f3cf 100644
--- a/src/vendorcode/amd/cimx/sb800/MEMLIB.c
+++ b/src/vendorcode/amd/cimx/sb800/MEMLIB.c
@@ -43,15 +43,15 @@ ReadMEM (
OpFlag = OpFlag & 0x7f;
switch ( OpFlag ) {
case AccWidthUint8:
- *((UINT8*)Value) = *((UINT8*) ((UINTN)Address));
+ *((UINT8*)Value) = *((UINT8*) ((intptr_t)Address));
break;
case AccWidthUint16:
- //*((UINT16*)Value) = *((UINT16*) ((UINTN)Address)); //gcc break strict-aliasing rules
- *((UINT8*)Value) = *((UINT8*) ((UINTN)Address));
- *((UINT8*)Value + 1) = *((UINT8*)((UINTN)Address) + 1);
+ //*((UINT16*)Value) = *((UINT16*) ((intptr_t)Address)); //gcc break strict-aliasing rules
+ *((UINT8*)Value) = *((UINT8*) ((intptr_t)Address));
+ *((UINT8*)Value + 1) = *((UINT8*)((intptr_t)Address) + 1);
break;
case AccWidthUint32:
- *((UINT32*)Value) = *((UINT32*) ((UINTN)Address));
+ *((UINT32*)Value) = *((UINT32*) ((intptr_t)Address));
break;
}
}
@@ -66,15 +66,15 @@ WriteMEM (
OpFlag = OpFlag & 0x7f;
switch ( OpFlag ) {
case AccWidthUint8 :
- *((UINT8*) ((UINTN)Address)) = *((UINT8*)Value);
+ *((UINT8*) ((intptr_t)Address)) = *((UINT8*)Value);
break;
case AccWidthUint16:
- //*((UINT16*) ((UINTN)Address)) = *((UINT16*)Value); //gcc break strict-aliasing rules
- *((UINT8*)((UINTN)Address)) = *((UINT8*)Value);
- *((UINT8*)((UINTN)Address) + 1) = *((UINT8*)Value + 1);
+ //*((UINT16*) ((intptr_t)Address)) = *((UINT16*)Value); //gcc break strict-aliasing rules
+ *((UINT8*)((intptr_t)Address)) = *((UINT8*)Value);
+ *((UINT8*)((intptr_t)Address) + 1) = *((UINT8*)Value + 1);
break;
case AccWidthUint32:
- *((UINT32*) ((UINTN)Address)) = *((UINT32*)Value);
+ *((UINT32*) ((intptr_t)Address)) = *((UINT32*)Value);
break;
}
}
diff --git a/src/vendorcode/amd/cimx/sb800/Makefile.inc b/src/vendorcode/amd/cimx/sb800/Makefile.inc
index 96cae03..fde6239 100644
--- a/src/vendorcode/amd/cimx/sb800/Makefile.inc
+++ b/src/vendorcode/amd/cimx/sb800/Makefile.inc
@@ -22,6 +22,11 @@ CPPFLAGS_x86_32 += -I$(src)/southbridge/amd/cimx/sb800
CPPFLAGS_x86_32 += -I$(src)/include/cpu/amd/common
CPPFLAGS_x86_32 += -I$(src)/vendorcode/amd/cimx/sb800
+CPPFLAGS_x86_64 += -I$(src)/mainboard/$(MAINBOARDDIR)
+CPPFLAGS_x86_64 += -I$(src)/southbridge/amd/cimx/sb800
+CPPFLAGS_x86_64 += -I$(src)/include/cpu/amd/common
+CPPFLAGS_x86_64 += -I$(src)/vendorcode/amd/cimx/sb800
+
romstage-y += ACPILIB.c
romstage-y += AZALIA.c
romstage-y += DISPATCHER.c
diff --git a/src/vendorcode/amd/cimx/sb800/SBMAIN.c b/src/vendorcode/amd/cimx/sb800/SBMAIN.c
index eb21770..a494d30 100644
--- a/src/vendorcode/amd/cimx/sb800/SBMAIN.c
+++ b/src/vendorcode/amd/cimx/sb800/SBMAIN.c
@@ -240,7 +240,7 @@ sbSmmAcpiOn (
* @param[in] Data Callback specific data.
* @param[in] pConfig Southbridge configuration structure pointer.
*/
-UINTN
+UINT32
CallBackToOEM (
IN UINT32 Func,
IN UINT32 Data,
diff --git a/src/vendorcode/amd/cimx/sb800/SBPELIB.c b/src/vendorcode/amd/cimx/sb800/SBPELIB.c
index 403f21f..c9f5dd1 100644
--- a/src/vendorcode/amd/cimx/sb800/SBPELIB.c
+++ b/src/vendorcode/amd/cimx/sb800/SBPELIB.c
@@ -176,7 +176,7 @@ getConfigPointer (
ddValue |= (dbValue << (i * 8));
dbReg++;
}
- return ( (AMDSBCFG*) (UINTN)ddValue);
+ return ( (AMDSBCFG*) (intptr_t)ddValue);
}
/**
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