[coreboot-gerrit] New patch to review for coreboot: coreboot_tables: Add CBMEM ID and tag for MTC

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10562

-gerrit

commit f81f7f8751227da113a6b3c311531ac664928432
Author: Furquan Shaikh <furquan at google.com>
Date:   Wed Jun 10 20:43:24 2015 -0700

    coreboot_tables: Add CBMEM ID and tag for MTC
    
    BUG=chrome-os-partner:41125
    BRANCH=None
    TEST=Compiles successfully and boots to kernel prompt
    
    Change-Id: Ia95b2a21863df5c3d6c08e9a134618db03a58775
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 8462a33c62ab34d0f5049fc3a7c5c2ee8e5e2e4c
    Original-Change-Id: Ie48a9a776b1c3ad30acf924c3d073acc8f2a8eda
    Original-Signed-off-by: Furquan Shaikh <furquan at google.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/276779
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-by: Jimmy Zhang <jimmzhang at nvidia.com>
    Original-Commit-Queue: Furquan Shaikh <furquan at chromium.org>
    Original-Trybot-Ready: Furquan Shaikh <furquan at chromium.org>
    Original-Tested-by: Furquan Shaikh <furquan at chromium.org>
---
 src/include/boot/coreboot_tables.h | 1 +
 src/include/cbmem_id.h             | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index 35ebd6e..c8d5251 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -229,6 +229,7 @@ struct lb_gpios {
 #define LB_TAB_VBOOT_HANDOFF	0x0020
 #define LB_TAB_DMA		0x0022
 #define LB_TAG_RAM_OOPS		0x0023
+#define LB_TAG_MTC		0x002b
 struct lb_range {
 	uint32_t tag;
 	uint32_t size;
diff --git a/src/include/cbmem_id.h b/src/include/cbmem_id.h
index b9c5ff2..1b03770 100644
--- a/src/include/cbmem_id.h
+++ b/src/include/cbmem_id.h
@@ -43,6 +43,7 @@
 #define CBMEM_ID_MEMINFO	0x494D454D
 #define CBMEM_ID_MPTABLE	0x534d5054
 #define CBMEM_ID_MRCDATA	0x4d524344
+#define CBMEM_ID_MTC		0xcb31d31c
 #define CBMEM_ID_NONE		0x00000000
 #define CBMEM_ID_PIRQ		0x49525154
 #define CBMEM_ID_POWER_STATE	0x50535454
@@ -88,6 +89,7 @@
 	{ CBMEM_ID_MEMINFO,		"MEM INFO   " }, \
 	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
 	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
+	{ CBMEM_ID_MTC,			"MTC        " }, \
 	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
 	{ CBMEM_ID_POWER_STATE,		"POWER STATE" }, \
 	{ CBMEM_ID_RAM_OOPS,		"RAMOOPS    " }, \