[coreboot-gerrit] New patch to review for coreboot: amd/sb800: Make UsbRxMode per-board customizable

Tobias Diedrich (ranma+coreboot@tdiedrich.de) gerrit at coreboot.org
Mon Jun 15 02:21:47 CEST 2015

Tobias Diedrich (ranma+coreboot at tdiedrich.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10549


commit cf676036544ee072c55c512191f1d378b863129e
Author: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
Date:   Mon Jun 15 01:59:03 2015 +0200

    amd/sb800: Make UsbRxMode per-board customizable
    On my Foxconn nT-A3500 on cold boot the board doesn't survive the soft
    reboot in the UsbRxMode path and the vendor bios doesn't touch this
    Cg2Pll voltage setting either.
    The fixup code for UsbRxMode in src/vendorcode/amd/cimx/sb800/SBPort.c
    doesn't seem to "CG PLL multiplier for USB Rx 1.1 mode", but rather
    lowers the Cg2Pll voltage from the hw default of 1.222V to 1.1V
    by setting Cg2Pll_IVR_TRIM in CGPllConfig5 to 1000.
    See also USB_PLL_Voltage which is only used in the UsbRxMode code path.
    However if this is already the efuse/eprom default for the SB800 then
    UsbRxMode is a no-op, so wether or not it gets executed depends on the
    very exact hw revision of the southbridge chip and could change between
    two instances of the same board.
    UsbRxMode used to be unitialized and was first set to default to 1
    in http://review.coreboot.org/#/c/6474/:
    > > Why initialize those to 1? (just curious)
    > See src/vendorcode/amd/cimx/sb800/SBTYPE.h
    > git grep 'SbSpiSpeedSupport\|UsbRxMode'
    > src/vendorcode/amd/cimx/sb800/SBTYPE.h
    I could not find a corresponding errata in the SB800 errata list,
    however errata 15 (USB Resets Asynchronously With Port CF9h Hard Reset)
    might play into this being unsafe to do since the code uses CF9h to
    So its possible that while previously undefined it still ended up
    defaulting to 0 and the codepath exercised on my board is simply
    buggy or there is a difference between a true "SB800" and the
    "A50 Hudson M1" presumably used on my board.
    Change-Id: I33f45925e222b86c0a97ece48f1ba97f6f878499
    Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
 src/southbridge/amd/cimx/sb800/cfg.c | 2 +-
 src/vendorcode/amd/cimx/sb800/OEM.h  | 8 ++++++++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c
index 9a3ca3a..a3e69fc 100644
--- a/src/southbridge/amd/cimx/sb800/cfg.c
+++ b/src/southbridge/amd/cimx/sb800/cfg.c
@@ -84,7 +84,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
 	sb_config->USBMODE.UsbModeReg = USB_CONFIG;
 	sb_config->SbUsbPll = 0;
 	/* CG PLL multiplier for USB Rx 1.1 mode (0=disable, 1=enable) */
-	sb_config->UsbRxMode = 1;
+	sb_config->UsbRxMode = USB_RX_MODE;
 	/* SATA */
 	sb_config->SataClass = SATA_MODE;
diff --git a/src/vendorcode/amd/cimx/sb800/OEM.h b/src/vendorcode/amd/cimx/sb800/OEM.h
index 36ba33b..d81f93c 100644
--- a/src/vendorcode/amd/cimx/sb800/OEM.h
+++ b/src/vendorcode/amd/cimx/sb800/OEM.h
@@ -285,6 +285,14 @@
+ * USB_RX_MODE - Enable CG2 clock voltage setting.
+ *
+ */
+#ifndef USB_RX_MODE
+  #define USB_RX_MODE                  0x01
  * Spread_Spectrum_Type
  *  - 0 : Normal platform

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