[coreboot-gerrit] Patch merged into coreboot/master: pistachio: add DDR3 initialization code

gerrit at coreboot.org gerrit at coreboot.org
Fri Jun 12 20:19:45 CEST 2015

the following patch was just integrated into master:
commit 3fa1ad0d2cb5d4a81e9e7bd0acdbc912d00f3bfe
Author: Ionela Voinescu <ionela.voinescu at imgtec.com>
Date:   Sun Apr 5 17:55:51 2015 +0100

    pistachio: add DDR3 initialization code
    Initialization for the Winbond W631GG6KB part using Synopsys
    DDR uMCTL and DDR Phy.
    This code adds a separate function for DDR3 initialization
    and moves all the necessary defines in a separate header file.
    The programming procedure that is executed at power up to bring
    up the uMCTL, PHY and memories into a state where reads and
    writes to the memory can be performed is the following:
    1. uPCTL (Universal DDR protocol controller) initialization
       The timining registers TOGCNT1U, TINIT, TOGCNT100N and TRSTH
       needed for driving the memory power-up sequence are programmed
       as a function of the internal timers clock frequency.
       Organization (memory chip specific) values are set
       (column/bank/row address width and number of ranks), together
       with other static values (latency, timing, power up configuration).
       All these values are static, provided by the datasheet,
       being determined by the memory type, size and frequency.
    2. PHY initialization
       The PHY is programmed with datasheet provided values,
       specifying the initialization values for it to send to the
       external memory (timing parameters).
       Also, delay lines (DLL) and strength of drive pads are
       calibrated (based on external conditions: temperature,
       voltage, noise) and locked. After that, the PHY goes
       through a trainig process (also dependent on the
       current conditions at boot time) to establish precise
       timing configuration between the DDR clock and DQS (data strobe)
       and between DQS and DQ (data).
    3. Memory power up
    4. Switch from configuration state to access state.
    It was tested on Pistachio bring up board where DDR was initialized
    properly and ramstage executed correctly
    Change-Id: I3bcbce2044327a22fce09b184d85ee11228a6b2b
    Signed-off-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
    Reviewed-on: http://review.coreboot.org/10529
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

See http://review.coreboot.org/10529 for details.


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