[coreboot-gerrit] New patch to review for coreboot: AMD OemS3Save: refactor for Merlin Falcon

WANG Siyuan (wangsiyuanbuaa@gmail.com) gerrit at coreboot.org
Fri Jun 12 13:46:13 CEST 2015


WANG Siyuan (wangsiyuanbuaa at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10526

-gerrit

commit b4f627c56e721d2b12cbac714f02476083384e09
Author: WANG Siyuan <wangsiyuanbuaa at gmail.com>
Date:   Fri Jun 12 16:41:50 2015 +0800

    AMD OemS3Save: refactor for Merlin Falcon
    
    Merlin Falcon(Carrizo) replaces struct AMD_S3SAVE_PARAMS
    with struct AMD_RTB_PARAMS. Use CONFIG_CPU_AMD_PI_00660F01
    to distinguish them.
    
    Change-Id: If074a8de95d82130d29b2e3cfbd7e35cdb9b929d
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa at gmail.com>
    Signed-off-by: WANG Siyuan <SiYuan.Wang at amd.com>
---
 src/northbridge/amd/agesa/agesawrapper.h | 2 +-
 src/northbridge/amd/agesa/oem_s3.c       | 7 ++++++-
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h
index eb1a59c..7e58e79 100644
--- a/src/northbridge/amd/agesa/agesawrapper.h
+++ b/src/northbridge/amd/agesa/agesawrapper.h
@@ -74,6 +74,6 @@ extern const struct OEM_HOOK OemCustomize;
 /* For suspend-to-ram support. */
 AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *ResumeParams);
 AGESA_STATUS OemS3LateRestore(AMD_S3LATE_PARAMS *S3LateParams);
-AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams);
+AGESA_STATUS OemS3Save(void *vS3SaveParams);
 
 #endif /* _AGESAWRAPPER_H_ */
diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c
index dfc1ebc..127d62f 100644
--- a/src/northbridge/amd/agesa/oem_s3.c
+++ b/src/northbridge/amd/agesa/oem_s3.c
@@ -115,8 +115,13 @@ static int spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len)
 #endif
 }
 
-AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams)
+AGESA_STATUS OemS3Save(void *vS3SaveParams)
 {
+#if IS_ENABLED(CONFIG_CPU_AMD_PI_00660F01)
+	AMD_RTB_PARAMS *S3SaveParams = (AMD_RTB_PARAMS *)vS3SaveParams;
+#else
+	AMD_S3SAVE_PARAMS *S3SaveParams = (AMD_S3SAVE_PARAMS *)vS3SaveParams;
+#endif
 	AMD_S3_PARAMS *dataBlock = &S3SaveParams->S3DataBlock;
 	u8 MTRRStorage[S3_DATA_MTRR_SIZE];
 	u32 MTRRStorageSize = 0;



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