[coreboot-gerrit] Patch set updated for coreboot: 5fad960 cpu/amd: Detect any conflicts between sysinfo and the stack region
Timothy Pearson (tpearson@raptorengineeringinc.com)
gerrit at coreboot.org
Wed Jun 10 18:58:40 CEST 2015
Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10401
-gerrit
commit 5fad960b95392b9b4267db241d2541d3e67dcc01
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date: Tue Jun 2 13:47:36 2015 -0500
cpu/amd: Detect any conflicts between sysinfo and the stack region
When increasing the number of supported CPUs on AMD Family 10h/15h
systems there is a relatively high chance of causing a collision
between the CAR global variable region and the AP stack space.
Such collision was noted when increasing the number of supported
CPUs to 32 on the ASUS KGPE-D16.
Detect collision at runtime and print a warning if collision is
present.
Change-Id: Ib5c32f868b1dfffb3b840bb1b1df5f55b5a25f8d
Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
src/cpu/Kconfig | 6 ++++++
src/cpu/amd/car/cache_as_ram.inc | 3 ++-
src/cpu/amd/geode_gx2/Kconfig | 8 ++++++++
src/cpu/amd/geode_lx/Kconfig | 8 ++++++++
src/cpu/amd/model_10xxx/Kconfig | 8 ++++++++
src/cpu/amd/model_10xxx/init_cpus.c | 8 ++++++++
src/cpu/amd/socket_754/Kconfig | 8 ++++++++
src/cpu/amd/socket_940/Kconfig | 8 ++++++++
src/cpu/amd/socket_S1G1/Kconfig | 8 ++++++++
9 files changed, 64 insertions(+), 1 deletion(-)
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index c8dc136..ae2e88c 100644
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -16,6 +16,12 @@ config DCACHE_RAM_BASE
config DCACHE_RAM_SIZE
hex
+config DCACHE_BSP_STACK_SIZE
+ hex
+
+config DCACHE_AP_STACK_SIZE
+ hex
+
config SMP
bool
default y if MAX_CPUS != 1
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 769e5cf..1c22447 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -24,9 +24,10 @@
#define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase (0xd0000 - CacheSize)
+#define CacheSizeBSPStack CONFIG_DCACHE_BSP_STACK_SIZE
/* For CAR with Fam10h. */
-#define CacheSizeAPStack 0x400 /* 1K */
+#define CacheSizeAPStack CONFIG_DCACHE_AP_STACK_SIZE
#define MSR_MCFG_BASE 0xC0010058
#define MSR_FAM10 0xC001102A
diff --git a/src/cpu/amd/geode_gx2/Kconfig b/src/cpu/amd/geode_gx2/Kconfig
index e00fea4..b867e37 100644
--- a/src/cpu/amd/geode_gx2/Kconfig
+++ b/src/cpu/amd/geode_gx2/Kconfig
@@ -37,6 +37,14 @@ config DCACHE_RAM_SIZE
hex
default 0x04000
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x1000
+
+config DCACHE_AP_STACK_SIZE
+ hex
+ default 0x400
+
config GEODE_VSA
bool
default y
diff --git a/src/cpu/amd/geode_lx/Kconfig b/src/cpu/amd/geode_lx/Kconfig
index 6001cc7..d799d6b 100644
--- a/src/cpu/amd/geode_lx/Kconfig
+++ b/src/cpu/amd/geode_lx/Kconfig
@@ -19,6 +19,14 @@ config DCACHE_RAM_SIZE
hex
default 0x8000
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x2000
+
+config DCACHE_AP_STACK_SIZE
+ hex
+ default 0x400
+
config GEODE_VSA
bool
default y
diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig
index cd69cae..4b5cded 100644
--- a/src/cpu/amd/model_10xxx/Kconfig
+++ b/src/cpu/amd/model_10xxx/Kconfig
@@ -30,6 +30,14 @@ config DCACHE_RAM_SIZE
hex
default 0x0c000
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x2000
+
+config DCACHE_AP_STACK_SIZE
+ hex
+ default 0x400
+
config UDELAY_IO
bool
default n
diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
index 62ba0b0..7e79307 100644
--- a/src/cpu/amd/model_10xxx/init_cpus.c
+++ b/src/cpu/amd/model_10xxx/init_cpus.c
@@ -250,6 +250,14 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
u32 apicid;
struct node_core_id id;
+ uint32_t max_ap_stack_region_size = CONFIG_MAX_CPUS * CONFIG_DCACHE_AP_STACK_SIZE;
+ uint32_t bsp_stack_region_lower_boundary = CONFIG_DCACHE_RAM_BASE + (CONFIG_DCACHE_RAM_SIZE / 2);
+ void * lower_stack_region_boundary = (void*)(bsp_stack_region_lower_boundary - max_ap_stack_region_size);
+ if (((void*)(sysinfo + 1)) > lower_stack_region_boundary)
+ printk(BIOS_WARNING,
+ "sysinfo extends into stack region (sysinfo range: [%p,%p] lower stack region boundary: %p)\n",
+ sysinfo, sysinfo + 1, lower_stack_region_boundary);
+
/*
* already set early mtrr in cache_as_ram.inc
*/
diff --git a/src/cpu/amd/socket_754/Kconfig b/src/cpu/amd/socket_754/Kconfig
index 3ddaea0..395fc78 100644
--- a/src/cpu/amd/socket_754/Kconfig
+++ b/src/cpu/amd/socket_754/Kconfig
@@ -20,4 +20,12 @@ config DCACHE_RAM_SIZE
hex
default 0x08000
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x2000
+
+config DCACHE_AP_STACK_SIZE
+ hex
+ default 0x400
+
endif # CPU_AMD_SOCKET_754
diff --git a/src/cpu/amd/socket_940/Kconfig b/src/cpu/amd/socket_940/Kconfig
index 1ca23e7..a481ded 100644
--- a/src/cpu/amd/socket_940/Kconfig
+++ b/src/cpu/amd/socket_940/Kconfig
@@ -21,4 +21,12 @@ config DCACHE_RAM_SIZE
hex
default 0x08000
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x2000
+
+config DCACHE_AP_STACK_SIZE
+ hex
+ default 0x400
+
endif # CPU_AMD_SOCKET_940
diff --git a/src/cpu/amd/socket_S1G1/Kconfig b/src/cpu/amd/socket_S1G1/Kconfig
index f88f64a..2c79e1f 100644
--- a/src/cpu/amd/socket_S1G1/Kconfig
+++ b/src/cpu/amd/socket_S1G1/Kconfig
@@ -31,4 +31,12 @@ config DCACHE_RAM_SIZE
hex
default 0x08000
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x2000
+
+config DCACHE_AP_STACK_SIZE
+ hex
+ default 0x400
+
endif
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