[coreboot-gerrit] Patch set updated for coreboot: 5ddae32 cpu/amd/car: Move AP stacks below the BSP stack to free up space

[Timothy Pearson (tpearson@raptorengineeringinc.com)]

Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10404

-gerrit

commit 5ddae32d830d7a3398befd5769ccec7afc0f6cad
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Tue Jun 2 20:25:03 2015 -0500

    cpu/amd/car: Move AP stacks below the BSP stack to free up space
    
    Caching SPD data during startup requires additional CAR space.
    There was a large chunk of free space between the AP stack top and
    the BSP stack bottom; moving the AP stacks below the BSP stack
    allows this space to be utilized.
    
    TEST: Booted ASUS KGPE-D16 with dual Opteron 6129 processors (16 cores)
    and 120k of CAR.
    
    Change-Id: I370ff368affde7061d6547527bda058b9016e977
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
 src/cpu/amd/car/cache_as_ram.inc    | 14 +++++++++++---
 src/cpu/amd/model_10xxx/init_cpus.c |  3 ++-
 2 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 51ebba6..83fbb07 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -377,9 +377,17 @@ CAR_FAM10_ap:
 	/*
 	 * Need to set stack pointer for AP.
 	 * It will be from:
-	 *   CacheBase + CacheSize / 2
+	 *   CacheBase + (CacheSize - CacheSizeBSPStack * 2)
 	 *   - (NodeID << CoreIDbits + CoreID) * CacheSizeAPStack
-	 * So need to get the NodeID and CoreID at first.
+	 * The spacing between the BSP stack and the top of the AP
+	 * stacks is purposefully set larger (an extra CacheSizeBSPStack
+	 * worth of unused space) than necessary to aid debugging when
+	 * additional stack variables are added  by future developers.
+	 * The extra space will allow BSP overruns to be caught by
+	 * the warning logic and easily fixed instead of crashing the
+	 * system with no obvious clues of what went wrong.
+	 *
+	 * So, need to get the NodeID and CoreID at first.
 	 * If NB_CFG bit 54 is set just use initial APIC ID, otherwise need
 	 * to reverse it.
 	 */
@@ -411,7 +419,7 @@ roll_cfg:
 	/* Calculate stack pointer. */
 	movl	$CacheSizeAPStack, %eax
 	mull	%ebx
-	movl	$(CacheBase + CacheSize / 2), %esp
+	movl	$(CacheBase + (CacheSize - CacheSizeBSPStack * 2)), %esp
 	subl	%eax, %esp
 
 	/* Retrive init detected. */
diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
index a8f6143..dd588cf 100644
--- a/src/cpu/amd/model_10xxx/init_cpus.c
+++ b/src/cpu/amd/model_10xxx/init_cpus.c
@@ -250,7 +250,8 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
 	u32 apicid;
 	struct node_core_id id;
 
-	void * lower_stack_region_boundary = (void*)((CONFIG_DCACHE_RAM_BASE + (CONFIG_DCACHE_RAM_SIZE / 2))
+	void * lower_stack_region_boundary = (void*)((CONFIG_DCACHE_RAM_BASE
+		 + (CONFIG_DCACHE_RAM_SIZE - (CONFIG_DCACHE_BSP_STACK_SIZE * 2)))
 		 - (CONFIG_MAX_CPUS * CONFIG_DCACHE_AP_STACK_SIZE));
 	if (((void*)(sysinfo + 1)) > lower_stack_region_boundary)
 		printk(BIOS_WARNING,