[coreboot-gerrit] New patch to review for coreboot: 27646a2 cpu/amd/car: Increase Family 10h CAR size limit to 128k

[Timothy Pearson (tpearson@raptorengineeringinc.com)]

Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10402

-gerrit

commit 27646a2a828a020d5615964b1b250d23b030a36d
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Tue Jun 2 13:53:25 2015 -0500

    cpu/amd/car: Increase Family 10h CAR size limit to 128k
    
    This resolves issues with 4-node (32-core) systems not having
    sufficient CAR memory available to boot.
    
    Change-Id: Ie884556edc5c85c2c908a8c6640eeec11594ba3a
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
 src/cpu/amd/car/cache_as_ram.inc       | 24 ++++++++++++++++++++++--
 src/cpu/amd/car/disable_cache_as_ram.c |  6 ++++++
 2 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 769e5cf..89c79e2 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -249,8 +249,14 @@ clear_fixed_var_mtrr_out:
 	 */
 .endm
 
-#if CacheSize > 0x10000
-#error Invalid CAR size, must be at most 64k.
+#if IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)
+  #if CacheSize > 0x80000
+  #error Invalid CAR size, must be at most 128k (processor limit is 512k).
+  #endif
+#else
+  #if CacheSize > 0x10000
+  #error Invalid CAR size, must be at most 64k.
+  #endif
 #endif
 #if CacheSize < 0x1000
 #error Invalid CAR size, must be at least 4k. This is a processor limitation.
@@ -266,6 +272,20 @@ clear_fixed_var_mtrr_out:
 	wrmsr
 #endif
 
+#if CacheSize > 0x10000
+	/* Enable caching for 64K-96K using fixed MTRR. */
+	movl	$MTRRfix4K_D0000_MSR, %ecx
+	simplemask CacheSize, 0x10000
+	wrmsr
+#endif
+
+#if CacheSize > 0x18000
+	/* Enable caching for 96K-128K using fixed MTRR. */
+	movl	$MTRRfix4K_D8000_MSR, %ecx
+	simplemask CacheSize, 0x18000
+	wrmsr
+#endif
+
 	/* Enable caching for 0-32K using fixed MTRR. */
 	movl	$MTRRfix4K_C8000_MSR, %ecx
 	simplemask CacheSize, 0
diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c
index 4a86280..03b6434 100644
--- a/src/cpu/amd/car/disable_cache_as_ram.c
+++ b/src/cpu/amd/car/disable_cache_as_ram.c
@@ -36,6 +36,12 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
 #if CONFIG_DCACHE_RAM_SIZE > 0x8000
 	wrmsr(MTRRfix4K_C0000_MSR, msr);
 #endif
+#if CONFIG_DCACHE_RAM_SIZE > 0x10000
+	wrmsr(MTRRfix4K_D0000_MSR, msr);
+#endif
+#if CONFIG_DCACHE_RAM_SIZE > 0x18000
+	wrmsr(MTRRfix4K_D8000_MSR, msr);
+#endif
 	/* disable fixed mtrr from now on, it will be enabled by ramstage again*/
 
 	msr = rdmsr(SYSCFG_MSR);