[coreboot-gerrit] New patch to review for coreboot: imgtech/pistacho: Add vboot2 memory region

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11100

-gerrit

commit ced0bf593475d8cfed55788e295a88f515a0e61e
Author: Patrick Georgi <pgeorgi at google.com>
Date:   Fri Jul 31 17:27:23 2015 +0200

    imgtech/pistacho: Add vboot2 memory region
    
    Change-Id: I375397d4a1db6fef6b40421590f315c0f7eb0948
    Signed-off-by: Patrick Georgi <pgeorgi at google.com>
---
 src/soc/imgtec/pistachio/include/soc/memlayout.ld | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index b36d47e..366b20a 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -18,6 +18,7 @@
  */
 
 #include <memlayout.h>
+#include <vendorcode/google/chromeos/memlayout.h>
 
 #include <arch/header.ld>
 
@@ -39,7 +40,8 @@ SECTIONS
 	 */
 	SRAM_START(0x1a000000)
 	ROMSTAGE(0x1a005000, 40K)
-	PRERAM_CBFS_CACHE(0x1a00f000, 68K)
+	VBOOT2_WORK(0x1a00f000, 12K)
+	PRERAM_CBFS_CACHE(0x1a012000, 56K)
 	SRAM_END(0x1a020000)
 
 	/* Bootblock executes out of KSEG0 and sets up the identity mapping.