[coreboot-gerrit] New patch to review for coreboot: More Hudson 64bit fixes

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11083

-gerrit

commit c473c5eae8ab145ce424b8e7a23cef0792a07872
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Jul 30 16:23:50 2015 -0700

    More Hudson 64bit fixes
    
    Change-Id: I2a6cd7ad27cb6d16dfe3267ea6fb844a5e2e20c6
    Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
---
 src/southbridge/amd/agesa/hudson/hudson.c | 8 ++++----
 src/southbridge/amd/agesa/hudson/sata.c   | 2 +-
 src/southbridge/amd/agesa/hudson/smi.h    | 8 ++++----
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c
index cafd6c6..dd52b3a 100644
--- a/src/southbridge/amd/agesa/hudson/hudson.c
+++ b/src/southbridge/amd/agesa/hudson/hudson.c
@@ -40,22 +40,22 @@
 
 void pm_write8(u8 reg, u8 value)
 {
-	write8((void *)(PM_MMIO_BASE + reg), value);
+	write8((void *)((uintptr_t)PM_MMIO_BASE + reg), value);
 }
 
 u8 pm_read8(u8 reg)
 {
-	return read8((void *)(PM_MMIO_BASE + reg));
+	return read8((void *)((uintptr_t)PM_MMIO_BASE + reg));
 }
 
 void pm_write16(u8 reg, u16 value)
 {
-	write16((void *)(PM_MMIO_BASE + reg), value);
+	write16((void *)((uintptr_t)PM_MMIO_BASE + reg), value);
 }
 
 u16 pm_read16(u16 reg)
 {
-	return read16((void *)(PM_MMIO_BASE + reg));
+	return read16((void *)((uintptr_t)PM_MMIO_BASE + reg));
 }
 
 #define PM_REG_USB_ENABLE	0xef
diff --git a/src/southbridge/amd/agesa/hudson/sata.c b/src/southbridge/amd/agesa/hudson/sata.c
index 00c2a07..c5dc196 100644
--- a/src/southbridge/amd/agesa/hudson/sata.c
+++ b/src/southbridge/amd/agesa/hudson/sata.c
@@ -41,7 +41,7 @@ static void sata_init(struct device *dev)
 	#define CFG_CAP_SPM (1<<12)
 
 	volatile u32 *ahci_ptr =
-		(u32*)(pci_read_config32(dev, AHCI_BASE_ADDRESS_REG) & 0xFFFFFF00);
+		(u32*)(uintptr_t)(pci_read_config32(dev, AHCI_BASE_ADDRESS_REG) & 0xFFFFFF00);
 	u32 temp;
 
 	/* unlock the write-protect */
diff --git a/src/southbridge/amd/agesa/hudson/smi.h b/src/southbridge/amd/agesa/hudson/smi.h
index 520c65f..652c886 100644
--- a/src/southbridge/amd/agesa/hudson/smi.h
+++ b/src/southbridge/amd/agesa/hudson/smi.h
@@ -36,22 +36,22 @@ enum smi_lvl {
 
 static inline uint32_t smi_read32(uint8_t offset)
 {
-	return read32((void *)(SMI_BASE + offset));
+	return read32((void *)((uintptr_t)SMI_BASE + offset));
 }
 
 static inline void smi_write32(uint8_t offset, uint32_t value)
 {
-	write32((void *)(SMI_BASE + offset), value);
+	write32((void *)((uintptr_t)SMI_BASE + offset), value);
 }
 
 static inline uint16_t smi_read16(uint8_t offset)
 {
-	return read16((void *)(SMI_BASE + offset));
+	return read16((void *)((uintptr_t)SMI_BASE + offset));
 }
 
 static inline void smi_write16(uint8_t offset, uint16_t value)
 {
-	write16((void *)(SMI_BASE + offset), value);
+	write16((void *)((uintptr_t)SMI_BASE + offset), value);
 }
 
 void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);