[coreboot-gerrit] Patch set updated for coreboot: Skylake: Fix microcode reload in bootblock cpu init

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11052

-gerrit

commit 3ec8109d372872b819840e555085bc50552418b2
Author: Rizwan Qureshi <rizwan.qureshi at intel.com>
Date:   Tue Jul 7 18:18:15 2015 +0530

    Skylake: Fix microcode reload in bootblock cpu init
    
    If Skylake microcode is being loaded from FIT, Skylake supports
    the PRMRR/SGX feature. If this is supported the FIT microcode
    load will set the msr (0x08b) with the patch ID one less than the
    ID in the microcode binary. This results in microcode getting
    reloaded again in the bootblock cpu init.
    Avoid the microcode reload by checking for PRMRR support.
    
    BUG=chrome-os-partner:42046
    BRANCH=None
    TEST=Built for glados and tested on RVP3
    
    Change-Id: I06e59f5cad549098c7ba2dfa608cd94a0b3f0ae1
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 6242b9dea283149bd0c968af1ba186647d37162d
    Original-Change-Id: Iea5a223aa625be3fc451e8ee5d3510f548b07f8b
    Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/286054
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/bootblock/cpu.c   | 24 +++++++++++++++++++++++-
 src/soc/intel/skylake/include/soc/msr.h |  2 +-
 2 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c
index d4506e5..2e3e000 100644
--- a/src/soc/intel/skylake/bootblock/cpu.c
+++ b/src/soc/intel/skylake/bootblock/cpu.c
@@ -178,11 +178,33 @@ static void check_for_clean_reset(void)
 		soft_reset();
 }
 
+static int need_microcode_update(void)
+{
+	/* If PRMRR/SGX is supported the FIT microcode load step will set
+	 * msr 0x08b with the Patch revision id one less than the id in the
+	 * microcode binary. The PRMRR support is indicated in the MSR
+	 * MTRRCAP[12]. Check for this feature and avoid reloading the
+	 * same microcode during early cpu initialization.
+	 */
+	msr = rdmsr(MTRRcap_MSR);
+	return (msr.lo & PRMRR_SUPPORTED) && (current_rev != patch->rev - 1);
+}
+
 static void bootblock_cpu_init(void)
 {
+	const struct microcode *patch;
+	u32 current_rev;
+	msr_t msr;
+
 	/* Set flex ratio and reset if needed */
 	set_flex_ratio_to_tdp_nominal();
 	check_for_clean_reset();
 	enable_rom_caching();
-	intel_update_microcode_from_cbfs();
+
+	patch = intel_microcode_find();
+
+	current_rev = read_microcode_rev();
+
+	if (need_microcode_update())
+		intel_update_microcode_from_cbfs();
 }
diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h
index b857dbe..3903757 100644
--- a/src/soc/intel/skylake/include/soc/msr.h
+++ b/src/soc/intel/skylake/include/soc/msr.h
@@ -105,6 +105,6 @@
 
 /* MTRRcap_MSR bits */
 #define SMRR_SUPPORTED (1<<11)
-#define EMRR_SUPPORTED (1<<12)
+#define PRMRR_SUPPORTED (1<<12)
 
 #endif