[coreboot-gerrit] New patch to review for coreboot: intel/braswell: fix build

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11065

-gerrit

commit 1dd96ed9bbe64dd9c90e11f79b569c126514f212
Author: Jenny TC <jenny.tc at intel.com>
Date:   Thu Jun 18 14:02:00 2015 +0530

    intel/braswell: fix build
    
    Commit "BCRD2: Enable LPDDR3" with the Change-Id listed below contained
    additions to braswell's chip.h which were lost during merging.
    
    BRANCH=None
    BUG=None
    TEST=google/strago builds
    
    Change-Id: I995b788b6a308cefa23228544127bb1e384bbcc7
    Signed-off-by: Patrick Georgi <pgeorgi at google.com>
    Original-Commit-Id: 561edf23ab696772fd0a6af34cb435db9d96e912
    Original-Change-Id: Ie08900bc62d517394412cc597274fb8f5b6b0f51
    Original-Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Original-Change-Id: I1cb5a03b77baf2df125b648dd75c9f8166f5571e
    Original-Original-Signed-off-by: Jenny TC <jenny.tc at intel.com>
    Original-Original-Signed-off-by: Divagar Mohandass <divagar.mohandass at intel.com>
    Original-Original-Reviewed-on: https://chromium-review.googlesource.com/282155
    Original-Reviewed-on: https://chromium-review.googlesource.com/288880
    Original-Reviewed-by: Stefan Reinauer <reinauer at chromium.org>
---
 src/soc/intel/braswell/chip.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index 7422bc4..191fc01 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -34,6 +34,9 @@
 #define SVID_CONFIG3		3
 #define SVID_PMIC_CONFIG	8
 
+#define MEM_DDR3	0
+#define MEM_LPDDR3	1
+
 struct soc_intel_braswell_config {
 	uint8_t enable_xdp_tap;
 	uint8_t clkreq_enable;