[coreboot-gerrit] Patch set updated for coreboot: skylake: Update microcode reload in ramstage.

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11056

-gerrit

commit ad42b92809ff811e0387049b6f8018e6e0fdc83b
Author: Rizwan Qureshi <rizwan.qureshi at intel.com>
Date:   Thu Jul 23 22:40:53 2015 +0530

    skylake: Update microcode reload in ramstage.
    
    For Skylake, Microcode is being loaded from FIT, Skylake supports
    the PRMRR/SGX feature. If This is supported the FIT microcode
    load will set the msr (0x08b) with the Patch id one less than the
    id in the microcode binary. This results in Microcode getting
    reloaded again in bootclock and ramstage (MP init).
    Avoid the microcode reload by checking for PRMRR support.
    
    BUG=chrome-os-partner:42046
    BRANCH=None TEST=Built for glados and tested on RVP3
    CQ-DEPEND=CL:287513
    
    Change-Id: Ic5dbf4d14dc1441e5b5acead589a418687df7dca
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: c599714b2aef476297eeaad5da8975731b12785a
    Original-Change-Id: Id3a387aa2d8fd2fd69052bfc7b4e88a7ec277a72
    Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/287674
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/cpu.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index cd88c10..97b928d 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -574,3 +574,19 @@ void soc_init_cpus(device_t dev)
 	if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER))
 		restore_default_smm_area(smm_save_area);
 }
+
+int soc_ucode_update_required(u32 currrent_patch_id, u32 new_patch_id)
+{
+	msr_t msr;
+	/* If PRMRR/SGX is supported the FIT microcode load will set the msr
+	 * 0x08b with the Patch revision id one less than the id in the
+	 * microcode binary. The PRMRR support is indicated in the MSR
+	 * MTRRCAP[12]. Check for this feature and avoid reloading the
+	 * same microcode during cpu initialization.
+	 */
+	msr = rdmsr(MTRRcap_MSR);
+	if ((msr.lo & PRMRR_SUPPORTED) && currrent_patch_id == new_patch_id - 1) {
+		return -1;
+	}
+	return 0;
+}