[coreboot-gerrit] Patch merged into coreboot/master: nvidia southbridges: don't touch 0x78 in LPC bridge with Fam10h

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit acba73aefcbd7dacb547b61570a1836b745be2e5
Author: Jonathan A. Kollasch <jakllsch at kollasch.net>
Date:   Mon Jul 20 09:51:34 2015 -0500

    nvidia southbridges: don't touch 0x78 in LPC bridge with Fam10h
    
    Based on the observations that AMD Fam10h with both Nvidia CK804 (Asus
    KFSN4-DRE) and MCP55 (Sun Ultra 40 M2) need to avoid adjusting the LPC
    bridge register 0x78 (particularly the 0x7b byte) to get to ramstage:
    Assume that there's something about this register that adjusting it the
    way we do for K8 is something that can/should be universally avoided on
    all Fam10h systems with these chipsets.
    
    Change-Id: I1eceeb20ecaefef4c61c11e19d1f5a59f91a0a2f
    Signed-off-by: Jonathan A. Kollasch <jakllsch at kollasch.net>
    Reviewed-on: http://review.coreboot.org/10984
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Timothy Pearson <tpearson at raptorengineeringinc.com>


See http://review.coreboot.org/10984 for details.

-gerrit