[coreboot-gerrit] New patch to review for coreboot: ddr3 spd: account fine timebase

[Patrick Rudolph (siro@das-labor.org)]

Patrick Rudolph (siro at das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11027

-gerrit

commit 610ae59fcdc00ecfadb6bf3612262e0920d5dc60
Author: Patrick Rudolph <siro at das-labor.org>
Date:   Wed Jul 15 10:03:30 2015 +0200

    ddr3 spd: account fine timebase
    
    SPD revision 1.1 adds optional fine timebase adjustments.
    Check SPD revision and apply the correction values.
    
    Change-Id: I3576821af5e78d2e9ea4d583a59dcc90cef6995f
    Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
 src/device/dram/ddr3.c | 32 ++++++++++++++++++++++++++------
 1 file changed, 26 insertions(+), 6 deletions(-)

diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c
index e1bb873..ee13de7 100644
--- a/src/device/dram/ddr3.c
+++ b/src/device/dram/ddr3.c
@@ -113,7 +113,9 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd)
 	u8 ftb_divisor, ftb_dividend, capacity_shift, bus_width;
 	u8 reg8;
 	u32 mtb;		/* medium time base */
+	u32 ftb;		/* fine time base */
 	unsigned int val, param;
+	char *comp;
 
 	ret = SPD_STATUS_OK;
 
@@ -239,12 +241,6 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd)
 	dimm->size_mb = ((1 << (capacity_shift + (25 - 20))) * bus_width
 			 * dimm->ranks) / dimm->width;
 
-	/* Fine Timebase (FTB) Dividend/Divisor */
-	/* Dividend */
-	ftb_dividend = (spd[9] >> 4) & 0x0f;
-	/* Divisor */
-	ftb_divisor = spd[9] & 0x0f;
-
 	/* Medium Timebase =
 	 *   Medium Timebase (MTB) Dividend /
 	 *   Medium Timebase (MTB) Divisor */
@@ -277,6 +273,30 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd)
 	/* Minimum Four Activate Window Delay Time (tFAWmin) */
 	dimm->tFAW = (((spd[28] & 0x0f) << 8) + spd[29]) * mtb;
 
+	/* Dividend */
+	ftb_dividend = (spd[9] >> 4) & 0x0f;
+	/* Divisor */
+	ftb_divisor = spd[9] & 0x0f;
+
+	/* SPD Revision 1.1 */
+	if (((spd[1] & 0xf0) == 0x10) && ((spd[1] & 0x0f) > 0) &&
+		    ftb_dividend && ftb_divisor) {
+		comp = (char *) &spd[34];
+		/* Fine Timebase (FTB) 1/256 ps Dividend/Divisor */
+		ftb = (ftb_dividend << 8) / ftb_divisor;
+
+		/* SDRAM Minimum Cycle Time (tCKmin) correction */
+		dimm->tCK += (comp[0] * ftb) / 1000;
+		/* Minimum CAS Latency Time (tAAmin) correction */
+		dimm->tAA += (comp[1] * ftb) / 1000;
+		/* Minimum RAS# to CAS# Delay Time (tRCDmin) correction */
+		dimm->tRCD += (comp[2] * ftb) / 1000;
+		/* Minimum Row Precharge Delay Time (tRPmin) correction */
+		dimm->tRP += (comp[3] * ftb) / 1000;
+		/* Minimum Active to Active/Refresh Delay Time (tRCmin) correction */
+		dimm->tRC += (comp[4] * ftb) / 1000;
+	}
+
 	/* SDRAM Optional Features */
 	reg8 = spd[30];
 	printram("  Optional features :");