[coreboot-gerrit] Patch merged into coreboot/master: t210: Correct device MMIO range

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 7fea2707efcdeb5559c333c96aad5b6632dd0fae
Author: Jimmy Zhang <jimmzhang at nvidia.com>
Date:   Mon Jul 13 14:10:18 2015 -0700

    t210: Correct device MMIO range
    
    Address region from 0x0 to 0x00ffffff is used for IROM_LOVEC and
    can not be accessed by Bootloader.
    
    Issue found in CL: 283104 is captured by this patch.
    
    BUG=None
    BRANCH=None
    TEST=Compiles successfully and reboot test does not crash in firmware
    
    Here are memory mapping table before and after this CL for evt2 board:
    
    Before:
    Mapping address range [0000000000000000:0000000040000000) as     cacheable | read-write |     secure | device
    Mapping address range [0000000040000000:0000000040040000) as     cacheable | read-write | non-secure | normal
    Mapping address range [0000000040040000:0000000080000000) as     cacheable | read-write |     secure | device
    Mapping address range [0000000080000000:00000000feb00000) as     cacheable | read-write | non-secure | normal
    Mapping address range [00000000fec00000:0000000100000000) as     cacheable | read-write |     secure | normal
    Mapping address range [0000000100000000:0000000140000000) as     cacheable | read-write | non-secure | normal
    
    After:
    Mapping address range [0000000001000000:0000000040000000) as     cacheable | read-write |     secure | device
    Mapping address range [0000000040000000:0000000040040000) as     cacheable | read-write | non-secure | normal
    Mapping address range [0000000040040000:0000000080000000) as     cacheable | read-write |     secure | device
    Mapping address range [0000000080000000:00000000feb00000) as     cacheable | read-write | non-secure | normal
    Mapping address range [00000000fec00000:0000000100000000) as     cacheable | read-write |     secure | normal
    Mapping address range [0000000100000000:0000000140000000) as     cacheable | read-write | non-secure | normal
    
    Signed-off-by: Jimmy Zhang <jimmzhang at nvidia.com>
    
    Change-Id: I07d38a8994c37bf945a68fb95a156c13f435ded2
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 3eee44944c2c83cc3530bfac0d71b86d3265f5b2
    Original-Change-Id: I2b827064807ed715625af627db1826c3a01121ec
    Original-Signed-off-by: Jimmy Zhang <jimmzhang at nvidia.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/285260
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11015
    Reviewed-by: Furquan Shaikh <furquan at google.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>


See http://review.coreboot.org/11015 for details.

-gerrit