[coreboot-gerrit] Patch merged into coreboot/master: skylake: read out and report full width of gen_pmcon registers

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit a3d36bd9693b78bc6ec2a30bef3413fa038d1a04
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Jul 16 17:49:33 2015 -0500

    skylake: read out and report full width of gen_pmcon registers
    
    GEN_PMCON_A and GEN_PMCON_B are 32-bits wide. Read out and
    save the full 32 bits for completeness.
    
    BUG=chrome-os-partner:42847
    BRANCH=None
    TEST=Built and booted. Noted output on terminal.
    
    Change-Id: I24e589271d49c8cfc3fab327cfe4999c24fb95d8
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 5a419b2538dc45b1bd0d19b7e6afd45fff9dd4a0
    Original-Change-Id: Ie587e886ea34e36d106ff4670781467266a51ddb
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/286270
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: http://review.coreboot.org/11006
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>


See http://review.coreboot.org/11006 for details.

-gerrit