[coreboot-gerrit] Patch set updated for coreboot: Glados: Update Serial IO modes in devicetree

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11002

-gerrit

commit 26cd87996a4e0fa0f0663e4637cc5939e3828771
Author: Naveen Krishna Chatradhi <naveenkrishna.ch at intel.com>
Date:   Fri Jul 10 17:09:37 2015 +0530

    Glados: Update Serial IO modes in devicetree
    
    This patch updates the Serial IO modes for UART2 to PCI mode
    in devicetree for glados board.
    
    Also we switch over to CONSOLE_SERIAL8250MEM_32 here. 8-bit
    legacy UART will stop working after devicetree change.
    
    BRANCH=None
    BUG=chrome-os-partner:40857
    TEST=Built for glados and tested LPSS logs on glados.
    
    CQ-DEPEND=CL:284881 CL:284882 CL:284883
    
    Change-Id: I433979c852c80848c006ef089b43d75a17e761c5
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 2c37519e0762801cbb9b547b538b385c84299189
    Original-Change-Id: I2faec08d089e407c5ab9838bea980553f49821c4
    Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/284826
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Commit-Queue: Wenkai Du <wenkai.du at intel.com>
    Original-Tested-by: Wenkai Du <wenkai.du at intel.com>
---
 src/mainboard/google/glados/devicetree.cb | 2 +-
 src/soc/intel/skylake/Kconfig             | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 2060866..6f89063 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -16,7 +16,7 @@ chip soc/intel/skylake
 		[PchSerialIoIndexSpi1]  = PchSerialIoDisabled, \
 		[PchSerialIoIndexUart0] = PchSerialIoPci, \
 		[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
-		[PchSerialIoIndexUart2] = PchSerialIoLegacyUart, \
+		[PchSerialIoIndexUart2] = PchSerialIoPci, \
 	}"
 
 	# Enable Root port 1 and 5.
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 856b84f..dbf68a7 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS
 	select CACHE_ROM
 	select CAR_MIGRATION
 	select CONSOLE_SERIAL8250MEM
+	select CONSOLE_SERIAL8250MEM_32
 	select COLLECT_TIMESTAMPS
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	select CPU_MICROCODE_IN_CBFS