[coreboot-gerrit] Patch set updated for coreboot: Sklrvp: Update Serial IO modes in devicetree
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Mon Jul 20 23:45:22 CEST 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11000
-gerrit
commit 2b07370c123117310fb28e1b5582bab961bbf695
Author: Naveen Krishna Chatradhi <naveenkrishna.ch at intel.com>
Date: Thu Jul 9 17:59:58 2015 +0530
Sklrvp: Update Serial IO modes in devicetree
This patch updates the Serial IO modes for UART 1 and 2
in devicetree for sklrvp boards.
UART1 is disabled and
UART2 is in PCI mode.
BRANCH=None
BUG=chrome-os-partner:40857
TEST=Built for sklrvp and tested LPSS logs on RVP3.
Change-Id: I59a657d6a3744040ec6be290ba966672e0e5f17e
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 5a20a70801d66abd87d4214e1ef187b86eed99da
Original-Change-Id: I381374272e1824ca8887ea5c5662215dde2c0a56
Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch at intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284824
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Original-Commit-Queue: Wenkai Du <wenkai.du at intel.com>
Original-Tested-by: Wenkai Du <wenkai.du at intel.com>
---
src/mainboard/intel/sklrvp/devicetree.cb | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/intel/sklrvp/devicetree.cb b/src/mainboard/intel/sklrvp/devicetree.cb
index 6cae727..66c1f18 100644
--- a/src/mainboard/intel/sklrvp/devicetree.cb
+++ b/src/mainboard/intel/sklrvp/devicetree.cb
@@ -11,8 +11,8 @@ chip soc/intel/skylake
[PchSerialIoIndexSpi0] = PchSerialIoPci, \
[PchSerialIoIndexSpi1] = PchSerialIoPci, \
[PchSerialIoIndexUart0] = PchSerialIoPci, \
- [PchSerialIoIndexUart1] = PchSerialIoPci, \
- [PchSerialIoIndexUart2] = PchSerialIoLegacyUart, \
+ [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
+ [PchSerialIoIndexUart2] = PchSerialIoPci, \
}"
# Enable eDP Hotplug with 6ms pulse
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