[coreboot-gerrit] New patch to review for coreboot: t210: Correct device MMIO range

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11015

-gerrit

commit 4cf5993c330c5e41786ab2f444707fff4eaa8b2b
Author: Jimmy Zhang <jimmzhang at nvidia.com>
Date:   Mon Jul 13 14:10:18 2015 -0700

    t210: Correct device MMIO range
    
    Address region from 0x0 to 0x00ffffff is used for IROM_LOVEC and
    can not be accessed by Bootloader.
    
    Issue found in CL: 283104 is captured by this patch.
    
    BUG=None
    BRANCH=None
    TEST=Compiles successfully and reboot test does not crash in firmware
    
    Here are memory mapping table before and after this CL for evt2 board:
    
    Before:
    Mapping address range [0000000000000000:0000000040000000) as     cacheable | read-write |     secure | device
    Mapping address range [0000000040000000:0000000040040000) as     cacheable | read-write | non-secure | normal
    Mapping address range [0000000040040000:0000000080000000) as     cacheable | read-write |     secure | device
    Mapping address range [0000000080000000:00000000feb00000) as     cacheable | read-write | non-secure | normal
    Mapping address range [00000000fec00000:0000000100000000) as     cacheable | read-write |     secure | normal
    Mapping address range [0000000100000000:0000000140000000) as     cacheable | read-write | non-secure | normal
    
    After:
    Mapping address range [0000000001000000:0000000040000000) as     cacheable | read-write |     secure | device
    Mapping address range [0000000040000000:0000000040040000) as     cacheable | read-write | non-secure | normal
    Mapping address range [0000000040040000:0000000080000000) as     cacheable | read-write |     secure | device
    Mapping address range [0000000080000000:00000000feb00000) as     cacheable | read-write | non-secure | normal
    Mapping address range [00000000fec00000:0000000100000000) as     cacheable | read-write |     secure | normal
    Mapping address range [0000000100000000:0000000140000000) as     cacheable | read-write | non-secure | normal
    
    Signed-off-by: Jimmy Zhang <jimmzhang at nvidia.com>
    
    Change-Id: I07d38a8994c37bf945a68fb95a156c13f435ded2
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 3eee44944c2c83cc3530bfac0d71b86d3265f5b2
    Original-Change-Id: I2b827064807ed715625af627db1826c3a01121ec
    Original-Signed-off-by: Jimmy Zhang <jimmzhang at nvidia.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/285260
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/nvidia/tegra210/include/soc/addressmap.h | 2 ++
 src/soc/nvidia/tegra210/mmu_operations.c         | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/soc/nvidia/tegra210/include/soc/addressmap.h b/src/soc/nvidia/tegra210/include/soc/addressmap.h
index 4a5372d..66888c6 100644
--- a/src/soc/nvidia/tegra210/include/soc/addressmap.h
+++ b/src/soc/nvidia/tegra210/include/soc/addressmap.h
@@ -30,6 +30,8 @@ enum {
 };
 
 enum {
+	TEGRA_ARM_PCIE_A1_BASE =	0x01000000,
+	TEGRA_ARM_LOWEST_PERIPH =	TEGRA_ARM_PCIE_A1_BASE,
 	TEGRA_ARM_PERIPHBASE =		0x50040000,
 	TEGRA_GICD_BASE =		0x50041000,
 	TEGRA_GICC_BASE =		0x50042000,
diff --git a/src/soc/nvidia/tegra210/mmu_operations.c b/src/soc/nvidia/tegra210/mmu_operations.c
index 66a93e1..dd7437c 100644
--- a/src/soc/nvidia/tegra210/mmu_operations.c
+++ b/src/soc/nvidia/tegra210/mmu_operations.c
@@ -43,7 +43,7 @@ static void tegra210_memrange_init(struct memranges *map)
 	memory_in_range_below_4gb(&start,&end);
 
 	/* Device memory below DRAM */
-	memranges_insert(map, 0, start * MiB, devmem);
+	memranges_insert(map, TEGRA_ARM_LOWEST_PERIPH, start * MiB, devmem);
 
 	/* DRAM */
 	memranges_insert(map, start * MiB, (end-start) * MiB, cachedmem);