[coreboot-gerrit] New patch to review for coreboot: skylake: take into account deep s3 in power failure check

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11007

-gerrit

commit 25add4325cccdd4fdb412d683f65a75f8d1da59a
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Jul 16 17:55:54 2015 -0500

    skylake: take into account deep s3 in power failure check
    
    If a resume from S3 is occuring one needs to take into account
    deep S3 in order to check the proper power failure bits.
    When deep S3 is enabled the suspend well will be turned off.
    Therefore don't look for that bit when determining a power
    failure.
    
    BUG=chrome-os-partner:42847
    BRANCH=None
    TEST=Suspend and resumed with deep s3 enabled and disabled.
    
    Change-Id: I2b3372a40b3d8295ee881a283b31ca7704e6764a
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: a3ba22be37d8700f4e8a4a0f5c05fb9290cfc9b2
    Original-Change-Id: I890f71a7cbea65f1db942fe2229a220cf0e721b0
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/286271
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/soc/intel/skylake/include/soc/pm.h       | 11 +++++++++++
 src/soc/intel/skylake/romstage/power_state.c | 18 ++++++++++++++++--
 2 files changed, 27 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h
index 4d9abcb..2e722bf 100644
--- a/src/soc/intel/skylake/include/soc/pm.h
+++ b/src/soc/intel/skylake/include/soc/pm.h
@@ -21,6 +21,9 @@
 #ifndef _SOC_PM_H_
 #define _SOC_PM_H_
 
+#include <arch/io.h>
+#include <soc/pmc.h>
+
 /* ACPI_BASE_ADDRESS / PMBASE */
 
 #define PM1_STS			0x00
@@ -169,4 +172,12 @@ uint8_t *pmc_mmio_regs(void);
 /* Get base address of TCO I/O registers. */
 uint16_t pmc_tco_regs(void);
 
+static inline int deep_s3_enabled(void)
+{
+	uint32_t deep_s3_pol;
+
+	deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL);
+	return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS));
+}
+
 #endif
diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c
index 4ffa381..5c94e89 100644
--- a/src/soc/intel/skylake/romstage/power_state.c
+++ b/src/soc/intel/skylake/romstage/power_state.c
@@ -74,8 +74,22 @@ static int prev_sleep_state(struct chipset_power_state *ps)
 		outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
 	}
 
-	if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))
-		prev_sleep_state = SLEEP_STATE_S5;
+	/*
+	 * If waking from S3 determine if deep S3 is enabled. If not,
+	 * need to check both deep sleep well and normal suspend well.
+	 * Otherwise just check deep sleep well.
+	 */
+	if (prev_sleep_state == SLEEP_STATE_S3) {
+		/* PWR_FLR represents deep sleep power well loss. */
+		uint32_t mask = PWR_FLR;
+
+		/* If deep s3 isn't enabled check the suspend well too. */
+		if (!deep_s3_enabled())
+			mask |= SUS_PWR_FLR;
+
+		if (ps->gen_pmcon_b & mask)
+			prev_sleep_state = SLEEP_STATE_S5;
+	}
 
 	return prev_sleep_state;
 }