[coreboot-gerrit] New patch to review for coreboot: skylake: Show SPI controller if enabled in devicetree.cb

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10986

-gerrit

commit 51fbdd9eb02da29d9ee9450969646a9d558c8cd3
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Jul 13 09:34:37 2015 -0700

    skylake: Show SPI controller if enabled in devicetree.cb
    
    Unhide the SPI controller PCI device if it is enabled in
    devicetree.cb so flashrom can do its job.
    
    BUG=chrome-os-partner:37711
    BRANCH=none
    TEST=run flashrom -r on glados
    
    Change-Id: Ie567f970149700d29df0ae09db4962f36cf24219
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 172eac55ad6134fe5e347e37c055b383e3b03245
    Original-Change-Id: Ia77b559cc607794aecc25d6d469224d855199568
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/284948
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/chip.h              | 3 ---
 src/soc/intel/skylake/romstage/romstage.c | 4 ++++
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 15e211e..d397c4e 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -199,9 +199,6 @@ struct soc_intel_skylake_config {
 	/* Integrated Sensor */
 	u8 IshEnable;
 
-	/* SPI related */
-	u8 ShowSpiController;
-
 	u8 PttSwitch;
 	u8 HeciTimeouts;
 	u8 HsioMessaging;
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index e8bb877..6d1310a 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -111,6 +111,10 @@ void soc_memory_init_params(MEMORY_INIT_UPD *params)
 	params->IoBufferOwnership = config->IoBufferOwnership;
 	params->DspEnable = config->DspEnable;
 	params->XdciEnable = config->XdciEnable;
+
+	/* Show SPI controller if enabled in devicetree.cb */
+	dev = dev_find_slot(0, PCH_DEVFN_SPI);
+	params->ShowSpiController = dev->enabled;
 }
 
 void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,