[coreboot-gerrit] Patch set updated for coreboot: AMD binary PI: add vendorcode support for fan control
WANG Siyuan (wangsiyuanbuaa@gmail.com)
gerrit at coreboot.org
Fri Jul 17 10:49:10 CEST 2015
WANG Siyuan (wangsiyuanbuaa at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10719
-gerrit
commit 7f345d8279980bd4508f2f92d9c16ddd6129bb4c
Author: WANG Siyuan <wangsiyuanbuaa at gmail.com>
Date: Tue Jun 23 22:14:33 2015 +0800
AMD binary PI: add vendorcode support for fan control
Binary PI doesn't provide fan control lib.
HwmLateService.c and ImcLib.c are ported from Kabini PI.
I have tested on AMD Bettong. The two files work.
Change-Id: Ia4d24650d2a5544674e9d44c502e8fd9da0b55d3
Signed-off-by: WANG Siyuan <wangsiyuanbuaa at gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang at amd.com>
---
src/vendorcode/amd/pi/Lib/imc/HwmLateService.c | 189 +++++++++++++++
src/vendorcode/amd/pi/Lib/imc/ImcLib.c | 314 +++++++++++++++++++++++++
src/vendorcode/amd/pi/Makefile.inc | 3 +
3 files changed, 506 insertions(+)
diff --git a/src/vendorcode/amd/pi/Lib/imc/HwmLateService.c b/src/vendorcode/amd/pi/Lib/imc/HwmLateService.c
new file mode 100644
index 0000000..f26dfc9
--- /dev/null
+++ b/src/vendorcode/amd/pi/Lib/imc/HwmLateService.c
@@ -0,0 +1,189 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Config FCH Hwm controller
+ *
+ * Init Hwm Controller features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_HWM_FAMILY_YANGTZE_YANGTZEHWMLATESERVICE_FILECODE
+
+/**
+ * Table for Function Number
+ *
+ *
+ *
+ *
+ */
+STATIC UINT8 FunctionNumber[] =
+{
+ Fun_81,
+ Fun_83,
+ Fun_85,
+ Fun_89,
+};
+
+/**
+ * Table for Max Thermal Zone
+ *
+ *
+ *
+ *
+ */
+UINT8 MaxZone[] =
+{
+ 4,
+ 4,
+ 4,
+ 4,
+};
+
+
+/**
+ * Table for Max Register
+ *
+ *
+ *
+ *
+ */
+UINT8 MaxRegister[] =
+{
+ MSG_REG9,
+ MSG_REGB,
+ MSG_REG9,
+ MSG_REGA,
+};
+
+/*-------------------------------------------------------------------------------
+;Procedure: IsZoneFuncEnable
+;
+;Description: This routine will check every zone support function with BitMap from user define
+;
+;
+;Exit: None
+;
+;Modified: None
+;
+;-----------------------------------------------------------------------------
+*/
+STATIC BOOLEAN
+IsZoneFuncEnable (
+ IN UINT16 Flag,
+ IN UINT8 func,
+ IN UINT8 Zone
+ )
+{
+ return (BOOLEAN) (((Flag >> (func *4)) & 0xF) & ((UINT8 )1 << Zone));
+}
+
+/*-------------------------------------------------------------------------------
+;Procedure: FchECfancontrolservice
+;
+;Description: This routine service EC fan policy
+;
+;
+;Exit: None
+;
+;Modified: None
+;
+;-----------------------------------------------------------------------------
+*/
+VOID
+FchECfancontrolservice (
+ IN VOID *FchDataPtr
+ )
+{
+ UINT8 ZoneNum;
+ UINT8 FunNum;
+ UINT8 RegNum;
+ UINT8 *CurPoint;
+ UINT8 FunIndex;
+ BOOLEAN IsSendEcMsg;
+ FCH_DATA_BLOCK *LocalCfgPtr;
+ AMD_CONFIG_PARAMS *StdHeader;
+
+ LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+ StdHeader = LocalCfgPtr->StdHeader;
+
+ if (!IsImcEnabled (StdHeader)) {
+ return; //IMC is not enabled
+ }
+
+ CurPoint = &LocalCfgPtr->Imc.EcStruct.MsgFun81Zone0MsgReg0 + MaxZone[0] * (MaxRegister[0] - MSG_REG0 + 1);
+
+ for ( FunIndex = 1; FunIndex <= 3; FunIndex++ ) {
+ FunNum = FunctionNumber[FunIndex];
+ for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) {
+ IsSendEcMsg = IsZoneFuncEnable (LocalCfgPtr->Imc.EcStruct.IMCFUNSupportBitMap, FunIndex, ZoneNum);
+ if (IsSendEcMsg) {
+ for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) {
+ WriteECmsg (RegNum, AccessWidth8, CurPoint, StdHeader);
+ CurPoint += 1;
+ }
+ WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &FunNum, StdHeader); // function number
+ WaitForEcLDN9MailboxCmdAck (StdHeader);
+ } else {
+ CurPoint += (MaxRegister[FunIndex] - MSG_REG0 + 1);
+ }
+ }
+ }
+
+ CurPoint = &LocalCfgPtr->Imc.EcStruct.MsgFun81Zone0MsgReg0;
+ for ( FunIndex = 0; FunIndex <= 0; FunIndex++ ) {
+ FunNum = FunctionNumber[FunIndex];
+ for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) {
+ IsSendEcMsg = IsZoneFuncEnable (LocalCfgPtr->Imc.EcStruct.IMCFUNSupportBitMap, FunIndex, ZoneNum);
+ if (IsSendEcMsg) {
+ for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) {
+ if (RegNum == MSG_REG2) {
+ *CurPoint &= 0xFE;
+ }
+ WriteECmsg (RegNum, AccessWidth8, CurPoint, StdHeader);
+ CurPoint += 1;
+ }
+ WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &FunNum, StdHeader); // function number
+ WaitForEcLDN9MailboxCmdAck (StdHeader);
+ } else {
+ CurPoint += (MaxRegister[FunIndex] - MSG_REG0 + 1);
+ }
+ }
+ }
+}
+
diff --git a/src/vendorcode/amd/pi/Lib/imc/ImcLib.c b/src/vendorcode/amd/pi/Lib/imc/ImcLib.c
new file mode 100644
index 0000000..5f192f3
--- /dev/null
+++ b/src/vendorcode/amd/pi/Lib/imc/ImcLib.c
@@ -0,0 +1,314 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH IMC lib
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 87213 $ @e \$Date: 2013-01-30 15:37:54 -0600 (Wed, 30 Jan 2013) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+****************************************************************************
+*/
+#include "FchPlatform.h"
+#include "Filecode.h"
+#define FILECODE PROC_FCH_IMC_IMCLIB_FILECODE
+
+/**
+ * WriteECmsg
+ *
+ *
+ *
+ * @param[in] Address - Address
+ * @param[in] OpFlag - Access width
+ * @param[in] *Value - Out Value pointer
+ * @param[in] StdHeader
+ *
+ */
+VOID
+WriteECmsg (
+ IN UINT8 Address,
+ IN UINT8 OpFlag,
+ IN VOID *Value,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT8 Index;
+
+ ASSERT (OpFlag < AccessWidth64); /* TODO: Add the assertion to make it not crash for now. */
+ OpFlag = (OpFlag & 0x7f) - 1;
+ if (OpFlag == 0x02) {
+ OpFlag = 0x03;
+ }
+
+ for (Index = 0; Index <= OpFlag; Index++) {
+ /// EC_LDN9_MAILBOX_BASE_ADDRESS
+ LibAmdIoWrite (AccessWidth8, MailBoxPort, &Address, StdHeader);
+ Address++;
+ /// EC_LDN9_MAILBOX_BASE_ADDRESS
+ LibAmdIoWrite (AccessWidth8, MailBoxPort + 1, (UINT8 *)Value + Index, StdHeader);
+ }
+}
+
+/**
+ * ReadECmsg
+ *
+ *
+ *
+ * @param[in] Address - Address
+ * @param[in] OpFlag - Access width
+ * @param[out] *Value - Out Value pointer
+ * @param[in] StdHeader
+ *
+ */
+VOID
+ReadECmsg (
+ IN UINT8 Address,
+ IN UINT8 OpFlag,
+ OUT VOID *Value,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT8 Index;
+
+ ASSERT (OpFlag < AccessWidth64); /* TODO: Add the assertion to make it not crash for now. */
+ OpFlag = (OpFlag & 0x7f) - 1;
+ if (OpFlag == 0x02) {
+ OpFlag = 0x03;
+ }
+
+ for (Index = 0; Index <= OpFlag; Index++) {
+ /// EC_LDN9_MAILBOX_BASE_ADDRESS
+ LibAmdIoWrite (AccessWidth8, MailBoxPort, &Address, StdHeader);
+ Address++;
+ /// EC_LDN9_MAILBOX_BASE_ADDRESS
+ LibAmdIoRead (AccessWidth8, MailBoxPort + 1, (UINT8 *)Value + Index, StdHeader);
+ }
+}
+
+/**
+ * WaitForEcLDN9MailboxCmdAck
+ *
+ *
+ * @param[in] StdHeader
+ *
+ */
+VOID
+WaitForEcLDN9MailboxCmdAck (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT8 Msgdata;
+ UINT16 Delaytime;
+
+ Msgdata = 0;
+
+ for (Delaytime = 0; Delaytime < 0xFFFF; Delaytime++) {
+ ReadECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader);
+ if ( Msgdata == 0xfa) {
+ break;
+ }
+
+ FchStall (5, StdHeader); /// Wait for 1ms
+ }
+}
+
+/**
+ * ImcSleep - IMC Sleep.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+ImcSleep (
+ IN VOID *FchDataPtr
+ )
+{
+ UINT8 Msgdata;
+ FCH_DATA_BLOCK *LocalCfgPtr;
+ AMD_CONFIG_PARAMS *StdHeader;
+
+ LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+ StdHeader = LocalCfgPtr->StdHeader;
+
+ if (!(IsImcEnabled (StdHeader)) ) {
+ return; ///IMC is not enabled
+ }
+
+ Msgdata = 0x00;
+ WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader);
+ Msgdata = 0xB4;
+ WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader);
+ Msgdata = 0x00;
+ WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader);
+ Msgdata = 0x96;
+ WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader);
+ WaitForEcLDN9MailboxCmdAck (StdHeader);
+}
+
+/**
+ * SoftwareDisableImc - Software disable IMC strap
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+SoftwareDisableImc (
+ IN VOID *FchDataPtr
+ )
+{
+ UINT8 ValueByte;
+ UINT8 PortStatusByte;
+ UINT32 AbValue;
+ UINT32 ABStrapOverrideReg;
+ AMD_CONFIG_PARAMS *StdHeader;
+
+ StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader;
+ GetChipSysMode (&PortStatusByte, StdHeader);
+
+ RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGC8 + 3, AccessWidth8, 0x7F, BIT7, StdHeader);
+ ReadPmio (0xBF, AccessWidth8, &ValueByte, StdHeader);
+
+ ReadMem ((ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80), AccessWidth32, &AbValue);
+ ABStrapOverrideReg = AbValue;
+ ABStrapOverrideReg &= ~BIT2; // bit2=0 EcEnableStrap
+ WriteMem ((ACPI_MMIO_BASE + MISC_BASE + 0x84), AccessWidth32, &ABStrapOverrideReg);
+
+ ReadPmio (FCH_PMIOA_REGD7, AccessWidth8, &ValueByte, StdHeader);
+ ValueByte |= BIT1;
+ WritePmio (FCH_PMIOA_REGD7, AccessWidth8, &ValueByte, StdHeader);
+
+ ValueByte = 06;
+ LibAmdIoWrite (AccessWidth8, 0xcf9, &ValueByte, StdHeader);
+ FchStall (0xffffffff, StdHeader);
+}
+
+/**
+ * ImcDisableSurebootTimer - IMC Disable Sureboot Timer.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+ImcDisableSurebootTimer (
+ IN VOID *FchDataPtr
+ )
+{
+ UINT8 Msgdata;
+ AMD_CONFIG_PARAMS *StdHeader;
+
+ StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader;
+
+ if (!(IsImcEnabled (StdHeader)) ) {
+ return; ///IMC is not enabled
+ }
+
+ ImcWakeup (FchDataPtr);
+ Msgdata = 0x00;
+ WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader);
+ Msgdata = 0x01;
+ WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader);
+ Msgdata = 0x00;
+ WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader);
+ Msgdata = 0x94;
+ WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader);
+ WaitForEcLDN9MailboxCmdAck (StdHeader);
+ ImcSleep (FchDataPtr);
+}
+
+/**
+ * ImcWakeup - IMC Wakeup.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+ImcWakeup (
+ IN VOID *FchDataPtr
+ )
+{
+ UINT8 Msgdata;
+ AMD_CONFIG_PARAMS *StdHeader;
+
+ StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader;
+ if (!(IsImcEnabled (StdHeader)) ) {
+ return; ///IMC is not enabled
+ }
+
+ Msgdata = 0x00;
+ WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader);
+ Msgdata = 0xB5;
+ WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader);
+ Msgdata = 0x00;
+ WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader);
+ Msgdata = 0x96;
+ WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader);
+ WaitForEcLDN9MailboxCmdAck (StdHeader);
+}
+
+/**
+ * ImcIdle - IMC Idle.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+ImcIdle (
+ IN VOID *FchDataPtr
+ )
+{
+ UINT8 Msgdata;
+ AMD_CONFIG_PARAMS *StdHeader;
+
+ StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader;
+
+ if (!(IsImcEnabled (StdHeader)) ) {
+ return; ///IMC is not enabled
+ }
+
+ Msgdata = 0x00;
+ WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader);
+ Msgdata = 0x01;
+ WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader);
+ Msgdata = 0x00;
+ WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader);
+ Msgdata = 0x98;
+ WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader);
+ WaitForEcLDN9MailboxCmdAck (StdHeader);
+}
diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc
index 42452f2..9353b82 100644
--- a/src/vendorcode/amd/pi/Makefile.inc
+++ b/src/vendorcode/amd/pi/Makefile.inc
@@ -103,6 +103,9 @@ agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Fch/Kern/KernImc/*.[cS])
agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Fch/Common/*.[cS])
agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Psp/PspBaseLib/*.[cS])
endif
+ifeq ($(CONFIG_HUDSON_IMC_FWM),y)
+agesa_raw_files += $(wildcard $(src)/vendorcode/amd/pi/Lib/imc/*.c)
+endif
classes-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += libagesa
$(eval $(call create_class_compiler,libagesa,x86_32))
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