[coreboot-gerrit] New patch to review for coreboot: t210: Reorganize memlayout.ld

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10948

-gerrit

commit c7624296be1b2cb857830fc6c89e79ac1a5659c2
Author: Furquan Shaikh <furquan at google.com>
Date:   Mon Jul 13 20:45:21 2015 -0700

    t210: Reorganize memlayout.ld
    
    Take up space from PRERAM_CBMEM_CACHE and increase verstage and
    romstage sizes.
    
    BUG=chrome-os-partner:36613
    BRANCH=None
    TEST=Compiles successfully and boots to kernel prompt
    
    Change-Id: I7fdd6c08f3ca1998a6220edd80a570816ec65ab5
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: cce3d7baa7446e227d3da41341d9e273d4195299
    Original-Signed-off-by: Furquan Shaikh <furquan at google.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/285344
    Original-Tested-by: Furquan Shaikh <furquan at chromium.org>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Commit-Queue: Furquan Shaikh <furquan at chromium.org>
    Original-Trybot-Ready: Furquan Shaikh <furquan at chromium.org>
    Original-Change-Id: I6d97a60b26fbbb29a875285c46724fb43b5fe5ab
    Original-Reviewed-on: https://chromium-review.googlesource.com/285533
    Original-Reviewed-by: Stefan Reinauer <reinauer at chromium.org>
---
 src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
index 26c6e34..dc25775 100644
--- a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
@@ -33,13 +33,13 @@ SECTIONS
 {
 	SRAM_START(0x40000000)
 	PRERAM_CBMEM_CONSOLE(0x40000000, 8K)
-	PRERAM_CBFS_CACHE(0x40002000, 72K)
-	VBOOT2_WORK(0x40014000, 16K)
-	STACK(0x40018000, 2K)
-	TIMESTAMP(0x40018800, 2K)
-	BOOTBLOCK(0x40019000, 24K)
-	VERSTAGE(0x4001F000, 52K)
-	ROMSTAGE(0x4002C000, 80K)
+	PRERAM_CBFS_CACHE(0x40002000, 36K)
+	VBOOT2_WORK(0x4000B000, 16K)
+	STACK(0x4000F000, 2K)
+	TIMESTAMP(0x4000F800, 2K)
+	BOOTBLOCK(0x40010000, 24K)
+	VERSTAGE(0x40016000, 64K)
+	ROMSTAGE(0x40026000, 104K)
 	SRAM_END(0x40040000)
 
 	DRAM_START(0x80000000)