[coreboot-gerrit] New patch to review for coreboot: AMD Merlin Falcon: Mask bit 31 of BIST while doing BIST check

[Zheng Bao (zheng.bao@amd.com)]

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10902

-gerrit

commit 5213ec8e5f7d0c362e62f5708a7f117ae27bfded
Author: zbao <fishbaozi at gmail.com>
Date:   Thu Jul 2 16:53:09 2015 -0400

    AMD Merlin Falcon: Mask bit 31 of BIST while doing BIST check
    
    This is a result of the Silcon Observation. On warm reset, the BIST
    is 0x80000000, which causes BIST error. We skip checking this bit.
    The update will be in CZ BKDG 1.05.
    
    The code is tested on AMD/bettong.
    
    Change-Id: I51c3f3567f758766079f7c8789f1ff072e1a7c53
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 src/mainboard/amd/bettong/romstage.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c
index 10813b3..a8a2777 100644
--- a/src/mainboard/amd/bettong/romstage.c
+++ b/src/mainboard/amd/bettong/romstage.c
@@ -48,7 +48,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	/* Halt if there was a built in self test failure */
 	post_code(0x34);
-	report_bist_failure(bist);
+	report_bist_failure(bist & 0x7FFFFFFF); /* Mask bit 31. One result of Silicon Observation */
 
 	/* Load MPB */
 	val = cpuid_eax(1);