[coreboot-gerrit] New patch to review for coreboot: arm64/a57: Move cortex_a57.h under include directory

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10898

-gerrit

commit b509965c6f5bdc2eb5a5f790ec93d46ff187f070
Author: Furquan Shaikh <furquan at google.com>
Date:   Fri Jul 10 15:27:02 2015 -0700

    arm64/a57: Move cortex_a57.h under include directory
    
    BUG=chrome-os-partner:41877
    BRANCH=None
    TEST=Compiles successfully
    
    Change-Id: I8a94176a3faacb25ae5e9eaeaac4011ddf5af6a1
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 802cba6f28a4e683256e8ce9fb6395acecdc9397
    Original-Change-Id: I3a5983d4a40466bc0aa8ab3bd8430ab6cdd093cc
    Original-Signed-off-by: Furquan Shaikh <furquan at google.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/284868
    Original-Reviewed-by: Yen Lin <yelin at nvidia.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Trybot-Ready: Furquan Shaikh <furquan at chromium.org>
    Original-Tested-by: Furquan Shaikh <furquan at chromium.org>
    Original-Commit-Queue: Furquan Shaikh <furquan at chromium.org>
---
 src/arch/arm64/cpu/cortex_a57.S         |  2 +-
 src/arch/arm64/cpu/cortex_a57.h         | 32 ------------------------------
 src/arch/arm64/include/cpu/cortex_a57.h | 35 +++++++++++++++++++++++++++++++++
 3 files changed, 36 insertions(+), 33 deletions(-)

diff --git a/src/arch/arm64/cpu/cortex_a57.S b/src/arch/arm64/cpu/cortex_a57.S
index ce8534b..4535d2b 100644
--- a/src/arch/arm64/cpu/cortex_a57.S
+++ b/src/arch/arm64/cpu/cortex_a57.S
@@ -19,7 +19,7 @@
 
 #include <arch/asm.h>
 #include <arch/cache_helpers.h>
-#include "cortex_a57.h"
+#include <cpu/cortex_a57.h>
 
 ENTRY(arm64_cpu_early_setup)
 	mrs x0, CPUECTLR_EL1
diff --git a/src/arch/arm64/cpu/cortex_a57.h b/src/arch/arm64/cpu/cortex_a57.h
deleted file mode 100644
index 5bd6160..0000000
--- a/src/arch/arm64/cpu/cortex_a57.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef __ARCH_ARM64_CORTEX_A57_H__
-#define __ARCH_ARM64_CORTEX_A57_H__
-
-#define CPUECTLR_EL1	S3_1_c15_c2_1
-#define SMPEN_SHIFT	6
-
-/* Cortex MIDR[15:4] PN */
-#define CORTEX_A53_PN	0xd03
-
-/* Double lock control bit */
-#define OSDLR_DBL_LOCK_BIT	1
-
-#endif /* __ARCH_ARM64_CORTEX_A57_H__ */
diff --git a/src/arch/arm64/include/cpu/cortex_a57.h b/src/arch/arm64/include/cpu/cortex_a57.h
new file mode 100644
index 0000000..113a6ff
--- /dev/null
+++ b/src/arch/arm64/include/cpu/cortex_a57.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __ARCH_ARM64_CORTEX_A57_H__
+#define __ARCH_ARM64_CORTEX_A57_H__
+
+#define CPUACTLR_EL1	s3_1_c15_c2_0
+#define BTB_INVALIDATE	(1 << 0)
+
+#define CPUECTLR_EL1	S3_1_c15_c2_1
+#define SMPEN_SHIFT	6
+
+/* Cortex MIDR[15:4] PN */
+#define CORTEX_A53_PN	0xd03
+
+/* Double lock control bit */
+#define OSDLR_DBL_LOCK_BIT	1
+
+#endif /* __ARCH_ARM64_CORTEX_A57_H__ */