[coreboot-gerrit] New patch to review for coreboot: t210: Add TZDRAM_BASE param to BL31_MAKEARGS

Fri Jul 10 08:30:01 CEST 2015

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10878

-gerrit

commit 584b44ef784019e8f189a85f1b8f354746f1a557
Author: Furquan Shaikh <furquan at google.com>
Date:   Tue Jul 7 21:35:56 2015 -0700

    t210: Add TZDRAM_BASE param to BL31_MAKEARGS
    
    1. Make TTB_SIZE Kconfig option
    2. Add Kconfig option for maximum secure component size
    3. Add check in Makefile to ensure that Trustzone area is big enough
    to hold TTB and secure components
    4. Calculate TZDRAM_BASE depending upon TTB_SIZE and TZ_CARVEOUT_SIZE
    
    BUG=chrome-os-partner:42319
    BRANCH=None
    
    Change-Id: I9ceb46ceedc931826657e5a0f6fc2b1886526bf8
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: a425d4978a467b157ea5d71e600242ebf427b5bb
    Original-Change-Id: I152a38830773d85aafab49c92cef945b7c4eb62c
    Original-Signed-off-by: Furquan Shaikh <furquan at google.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/284074
    Original-Reviewed-by: Varun Wadekar <vwadekar at nvidia.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-by: Tom Warren <twarren at nvidia.com>
    Original-Commit-Queue: Furquan Shaikh <furquan at chromium.org>
    Original-Trybot-Ready: Furquan Shaikh <furquan at chromium.org>
    Original-Tested-by: Furquan Shaikh <furquan at chromium.org>
---
 src/soc/nvidia/tegra210/Kconfig                    | 13 +++++++++++++
 src/soc/nvidia/tegra210/Makefile.inc               | 22 ++++++++++++++++++++++
 .../nvidia/tegra210/include/soc/mmu_operations.h   |  3 ---
 src/soc/nvidia/tegra210/mmu_operations.c           |  2 +-
 src/soc/nvidia/tegra210/secmon.c                   |  2 +-
 5 files changed, 37 insertions(+), 5 deletions(-)

diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig
index 7aa932a..7aff588 100644
--- a/src/soc/nvidia/tegra210/Kconfig
+++ b/src/soc/nvidia/tegra210/Kconfig
@@ -102,6 +102,19 @@ config TRUSTZONE_CARVEOUT_SIZE_MB
 	help
 	  Size of Trust Zone area in MiB to reserve in memory map.
 
+config TTB_SIZE_MB
+	hex "Size of TTB"
+	default 0x4
+	help
+	  Maximum size of Translation Table Buffer in MiB.
+
+config SEC_COMPONENT_SIZE_MB
+	hex "Size of resident EL3 components"
+	default 0x10
+	help
+	  Maximum size of resident EL3 components in MiB including BL31 and
+	  Secure OS.
+
 # Default to 700MHz. This value is based on nv bootloader setting.
 config PLLX_KHZ
 	int
diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc
index 98e752c..3b2dc7c 100644
--- a/src/soc/nvidia/tegra210/Makefile.inc
+++ b/src/soc/nvidia/tegra210/Makefile.inc
@@ -146,6 +146,28 @@ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BCT_BIN)
 	@printf "    CBOOTIMAGE $(subst $(obj)/,,$(@))\n"
 	$(CBOOTIMAGE) $(CBOOTIMAGE_OPTS) $(BCT_WRAPPER) $@
 
+# We need to ensure that TZ memory has enough space to hold TTB and resident EL3
+# components (including BL31 and Secure OS)
+ttb_size=$(shell printf "%d" $(CONFIG_TTB_SIZE_MB))
+sec_size=$(shell printf "%d" $(CONFIG_SEC_COMPONENT_SIZE_MB))
+req_tz_size=$(shell expr $(ttb_size) + $(sec_size))
+
+tz_size=$(shell printf "%d" $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB))
+
+ifeq ($(shell test $(tz_size) -lt $(req_tz_size) && echo 1), 1)
+     $(error "TRUSTZONE_CARVEOUT_SIZE_MB should be atleast as big as TTB_SIZE_MB + SEC_COMPONENT_SIZE_MB")
+endif
+
+# BL31 component is placed towards the end of 32-bit address space. This assumes
+# that TrustZone memory is placed at the end of 32-bit address space. Within the
+# TZ memory, we place TTB at the beginning and then remaining space can be used
+# up by BL31 and secure OS. Calculate TZDRAM_BASE i.e. base of BL31 component
+# by:
+#   0x1000 = end of 32-bit address space in MiB
+#   0x1000 - $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB) = start of TZ memory in MiB
+#   0x1000 - $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB) + $(CONFIG_TTB_SIZE_MB)
+#             = skip TTB buffer and get base address of BL31
+BL31_MAKEARGS += TZDRAM_BASE=$$(((0x1000 - $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB) + $(CONFIG_TTB_SIZE_MB)) << 20))
 BL31_MAKEARGS += PLAT=tegra TARGET_SOC=t210
 
 # MTC fw
diff --git a/src/soc/nvidia/tegra210/include/soc/mmu_operations.h b/src/soc/nvidia/tegra210/include/soc/mmu_operations.h
index 6a81e7c..a6e42aa 100644
--- a/src/soc/nvidia/tegra210/include/soc/mmu_operations.h
+++ b/src/soc/nvidia/tegra210/include/soc/mmu_operations.h
@@ -22,7 +22,4 @@
 
 void tegra210_mmu_init(void);
 
-/* Default ttb size of 4MiB */
-#define TTB_SIZE 0x4
-
 #endif //__SOC_NVIDIA_TEGRA210_MMU_OPERATIONS_H__
diff --git a/src/soc/nvidia/tegra210/mmu_operations.c b/src/soc/nvidia/tegra210/mmu_operations.c
index 2ee6b80..66a93e1 100644
--- a/src/soc/nvidia/tegra210/mmu_operations.c
+++ b/src/soc/nvidia/tegra210/mmu_operations.c
@@ -77,7 +77,7 @@ void tegra210_mmu_init(void)
 	/* Place page tables at the base of the trust zone region. */
 	carveout_range(CARVEOUT_TZ, &tz_base_mib, &tz_size_mib);
 	tz_base_mib *= MiB;
-	ttb_size_mib = TTB_SIZE * MiB;
+	ttb_size_mib = CONFIG_TTB_SIZE_MB * MiB;
 	mmu_init(map, (void *)tz_base_mib, ttb_size_mib);
 	mmu_enable();
 }
diff --git a/src/soc/nvidia/tegra210/secmon.c b/src/soc/nvidia/tegra210/secmon.c
index 66ebed2..c093607 100644
--- a/src/soc/nvidia/tegra210/secmon.c
+++ b/src/soc/nvidia/tegra210/secmon.c
@@ -43,7 +43,7 @@ void soc_get_secmon_base_size(uint64_t *base, size_t *size)
 
 	soc_get_secure_mem(&tz_base, &tz_size);
 
-	ttb_size = TTB_SIZE * MiB;
+	ttb_size = CONFIG_TTB_SIZE_MB * MiB;
 
 	*base = tz_base + ttb_size;
 	*size = tz_size - ttb_size;

