[coreboot-gerrit] New patch to review for coreboot: t210: set CAR2PMC_CPU_ACK_WIDTH to 0

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10841

-gerrit

commit 48a571063c6f702e9c5a5b1542e89908e7590949
Author: Yen Lin <yelin at nvidia.com>
Date:   Wed May 6 13:56:50 2015 -0700

    t210: set CAR2PMC_CPU_ACK_WIDTH to 0
    
    HW team has suggested to set CAR2PMC_CPU_ACK_WIDTH to 0.
    
    BUG=None
    BRANCH=None
    TEST=Tested on Smaug; still boot to kernel
    
    Change-Id: I4d13a4048b73455b16da7a40c408c912fa97e4e7
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 8891a79e72af26d986af9e415149d4ca0aa6fedd
    Original-Change-Id: I850a6756d7743993802fb85aad403e4cbef7a661
    Original-Signed-off-by: Yen Lin <yelin at nvidia.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/282416
    Original-Reviewed-by: Furquan Shaikh <furquan at chromium.org>
---
 src/soc/nvidia/tegra210/ccplex.c              | 17 +++++++++++++++++
 src/soc/nvidia/tegra210/include/soc/clk_rst.h |  3 +++
 2 files changed, 20 insertions(+)

diff --git a/src/soc/nvidia/tegra210/ccplex.c b/src/soc/nvidia/tegra210/ccplex.c
index f3c61cb..a3c6722 100644
--- a/src/soc/nvidia/tegra210/ccplex.c
+++ b/src/soc/nvidia/tegra210/ccplex.c
@@ -92,9 +92,26 @@ static void request_ram_repair(void)
 		stopwatch_duration_usecs(&sw));
 }
 
+static void set_cpu_ack_width(uint32_t val)
+{
+	uint32_t reg;
+
+	reg = read32(CLK_RST_REG(cpu_softrst_ctrl2));
+	reg &= ~CAR2PMC_CPU_ACK_WIDTH_MASK;
+	reg |= val;
+	write32(CLK_RST_REG(cpu_softrst_ctrl2), reg);
+}
+
 void ccplex_cpu_prepare(void)
 {
 	enable_cpu_clocks();
+
+	/*
+	 * The POR value of CAR2PMC_CPU_ACK_WIDTH is 0x200.
+	 * The recommended value is 0.
+	 */
+	set_cpu_ack_width(0);
+
 	enable_cpu_power_partitions();
 
 	mainboard_configure_pmc();
diff --git a/src/soc/nvidia/tegra210/include/soc/clk_rst.h b/src/soc/nvidia/tegra210/include/soc/clk_rst.h
index 817a041..87790d5 100644
--- a/src/soc/nvidia/tegra210/include/soc/clk_rst.h
+++ b/src/soc/nvidia/tegra210/include/soc/clk_rst.h
@@ -534,6 +534,9 @@ enum {
 #define PCLK_DIVISOR_SHIFT    		0
 #define PCLK_DIVISOR_MASK     		(3 << AHB_RATE_SHIFT)
 
+/* CPU_SOFTRST_CTRL2_0 0x388 */
+#define CAR2PMC_CPU_ACK_WIDTH_MASK	0xfff
+
 /* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */
 #define MSELECT_CLK_SRC_PLLP_OUT0	(0 << 29)