[coreboot-gerrit] Patch set updated for coreboot: timestamp: remove conditional #if CONFIG_COLLECT_TIMESTAMPS

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10742

-gerrit

commit f2cd189a7a849b00019ac6ede9aff0670211dce4
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Nov 6 09:58:07 2014 -0600

    timestamp: remove conditional #if CONFIG_COLLECT_TIMESTAMPS
    
    Empty functions are provided when !CONFIG_COLLECT_TIMESTAMPS
    so stop guarding the compilation.
    
    BUG=None
    BRANCH=None
    TEST=Built
    
    Original-Change-Id: Ib0f23e1204e048a9b928568da02e9661f6aa0a35
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/228190
    Original-Reviewed-by: Furquan Shaikh <furquan at chromium.org>
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
    
    (cherry picked from commit 9aa69fd43d77f5f7acdc9f361016c595dd16104e)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: I14418c8ef3ccb57ac6fce05b422e1c21b1d38392
---
 src/arch/x86/boot/acpi.c                      | 4 ----
 src/southbridge/intel/bd82x6x/bootblock.c     | 3 +--
 src/southbridge/intel/fsp_bd82x6x/bootblock.c | 3 +--
 src/southbridge/intel/i82801gx/bootblock.c    | 3 +--
 src/southbridge/intel/lynxpoint/bootblock.c   | 3 +--
 5 files changed, 4 insertions(+), 12 deletions(-)

diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c
index cf33e40..134e437 100644
--- a/src/arch/x86/boot/acpi.c
+++ b/src/arch/x86/boot/acpi.c
@@ -34,9 +34,7 @@
 #include <cpu/x86/lapic_def.h>
 #include <cpu/cpu.h>
 #include <cbfs.h>
-#if CONFIG_COLLECT_TIMESTAMPS
 #include <timestamp.h>
-#endif
 #include <romstage_handoff.h>
 
 /* FIXME: Kconfig doesn't support overridable defaults :-( */
@@ -1124,9 +1122,7 @@ void acpi_jump_to_wakeup(void *vector)
 	/* Copy wakeup trampoline in place. */
 	memcpy((void *)WAKEUP_BASE, &__wakeup, __wakeup_size);
 
-#if CONFIG_COLLECT_TIMESTAMPS
 	timestamp_add_now(TS_ACPI_WAKE_JUMP);
-#endif
 
 	acpi_do_wakeup((u32)vector, acpi_backup_memory, CONFIG_RAMBASE,
 		       HIGH_MEMORY_SAVE);
diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c
index 4df6bb5..18532df 100644
--- a/src/southbridge/intel/bd82x6x/bootblock.c
+++ b/src/southbridge/intel/bd82x6x/bootblock.c
@@ -86,9 +86,8 @@ static void set_spi_speed(void)
 
 static void bootblock_southbridge_init(void)
 {
-#if CONFIG_COLLECT_TIMESTAMPS
 	store_initial_timestamp();
-#endif
+
 	enable_spi_prefetch();
 	enable_port80_on_lpc();
 	set_spi_speed();
diff --git a/src/southbridge/intel/fsp_bd82x6x/bootblock.c b/src/southbridge/intel/fsp_bd82x6x/bootblock.c
index 46aa58f..8f6ddbc 100644
--- a/src/southbridge/intel/fsp_bd82x6x/bootblock.c
+++ b/src/southbridge/intel/fsp_bd82x6x/bootblock.c
@@ -87,9 +87,8 @@ static void set_spi_speed(void)
 
 static void bootblock_southbridge_init(void)
 {
-#if CONFIG_COLLECT_TIMESTAMPS
 	store_initial_timestamp();
-#endif
+
 	enable_spi_prefetch();
 	enable_port80_on_lpc();
 	set_spi_speed();
diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c
index 64c4410..dde1ae9 100644
--- a/src/southbridge/intel/i82801gx/bootblock.c
+++ b/src/southbridge/intel/i82801gx/bootblock.c
@@ -47,9 +47,8 @@ static void enable_spi_prefetch(void)
 
 static void bootblock_southbridge_init(void)
 {
-#if CONFIG_COLLECT_TIMESTAMPS
 	store_initial_timestamp();
-#endif
+
         enable_spi_prefetch();
 
 	/* Enable RCBA */
diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c
index 6727173..8c2133b 100644
--- a/src/southbridge/intel/lynxpoint/bootblock.c
+++ b/src/southbridge/intel/lynxpoint/bootblock.c
@@ -87,9 +87,8 @@ static void set_spi_speed(void)
 
 static void bootblock_southbridge_init(void)
 {
-#if CONFIG_COLLECT_TIMESTAMPS
 	store_initial_timestamp();
-#endif
+
 	map_rcba();
 	enable_spi_prefetch();
 	enable_port80_on_lpc();