[coreboot-gerrit] New patch to review for coreboot: T210: UTMIP: Correct UTMIP PLL programming as per Mark Kuo

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10814

-gerrit

commit 0c53b0f9a7f03098517f065b8ffa8253af9603e8
Author: Tom Warren <twarren at nvidia.com>
Date:   Tue Jun 30 10:22:12 2015 -0700

    T210: UTMIP: Correct UTMIP PLL programming as per Mark Kuo
    
    BUG=chrome-os-partner:39603
    BRANCH=none
    TEST=Built OK for Smaug.
    
    Change-Id: Iba170d8ad6f1dff111421fd61f71da19de57efaa
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 1bf1c1442dacf45bac5d55b05ada99a2c96f2e45
    Original-Change-Id: Iecf04691a637b56e2f2287ab7d4d0cdda0382421
    Original-Signed-off-by: Tom Warren <twarren at nvidia.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/282720
    Original-Reviewed-by: Andrew Bresticker <abrestic at chromium.org>
    Original-Reviewed-by: Mark Kuo <mkuo at nvidia.com>
---
 src/soc/nvidia/tegra210/clock.c               | 36 ++++++++++++++-------------
 src/soc/nvidia/tegra210/include/soc/clk_rst.h |  9 +++++--
 2 files changed, 26 insertions(+), 19 deletions(-)

diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c
index aa72340..394c781 100644
--- a/src/soc/nvidia/tegra210/clock.c
+++ b/src/soc/nvidia/tegra210/clock.c
@@ -328,19 +328,9 @@ static void init_utmip_pll(void)
 {
 	int khz = clock_get_pll_input_khz();
 
-	/* Shut off PLL crystal clock while we mess with it */
-	clrbits_le32(CLK_RST_REG(utmip_pll_cfg2), UTMIP_CFG2_PHY_XTAL_CLOCKEN);
-	udelay(1);
-
-	/* CFG0 */
-	u32 div_n = div_round_up(960000, khz);
-	write32(CLK_RST_REG(utmip_pll_cfg0), /* 960 MHz VCO */
-		1 << UTMIP_CFG0_PLL_MDIV_SHIFT |
-		div_n << UTMIP_CFG0_PLL_NDIV_SHIFT);
-
 	/* CFG1 */
-	u32 pllu_enb_ct = div_round_up(khz, 8000); /* pllu_enb_ct / 8 (1us) */
-	u32 phy_stb_ct = div_round_up(khz, 102);  /* phy_stb_ct / 256(2.5ms) */
+	u32 pllu_enb_ct = 0;
+	u32 phy_stb_ct = div_round_up(khz, 300);  /* phy_stb_ct = 128 */
 	write32(CLK_RST_REG(utmip_pll_cfg1),
 		pllu_enb_ct << UTMIP_CFG1_PLLU_ENABLE_DLY_COUNT_SHIFT |
 		UTMIP_CFG1_FORCE_PLLU_POWERDOWN_ENABLE |
@@ -350,16 +340,28 @@ static void init_utmip_pll(void)
 		phy_stb_ct << UTMIP_CFG1_XTAL_FREQ_COUNT_SHIFT);
 
 	/* CFG2 */
-	u32 pllu_stb_ct = div_round_up(khz, 256); /* pllu_stb_ct / 256 (1ms) */
-	u32 phy_act_ct = div_round_up(khz, 3200); /* phy_act_ct / 16 (5us) */
+	u32 pllu_stb_ct = 0;
+	u32 phy_act_ct = div_round_up(khz, 6400); /* phy_act_ct = 6 */
 	write32(CLK_RST_REG(utmip_pll_cfg2),
 		phy_act_ct << UTMIP_CFG2_PLL_ACTIVE_DLY_COUNT_SHIFT |
 		pllu_stb_ct << UTMIP_CFG2_PLLU_STABLE_COUNT_SHIFT |
+		UTMIP_CFG2_FORCE_PD_SAMP_D_POWERDOWN_DISABLE |
 		UTMIP_CFG2_FORCE_PD_SAMP_C_POWERDOWN_DISABLE |
 		UTMIP_CFG2_FORCE_PD_SAMP_B_POWERDOWN_DISABLE |
-		UTMIP_CFG2_FORCE_PD_SAMP_A_POWERDOWN_DISABLE);
-
-	setbits_le32(CLK_RST_REG(utmip_pll_cfg2), UTMIP_CFG2_PHY_XTAL_CLOCKEN);
+		UTMIP_CFG2_FORCE_PD_SAMP_A_POWERDOWN_DISABLE |
+		UTMIP_CFG2_FORCE_PD_SAMP_D_POWERUP_ENABLE |
+		UTMIP_CFG2_FORCE_PD_SAMP_C_POWERUP_ENABLE |
+		UTMIP_CFG2_FORCE_PD_SAMP_B_POWERUP_ENABLE |
+		UTMIP_CFG2_FORCE_PD_SAMP_A_POWERUP_ENABLE);
+
+	printk(BIOS_DEBUG, "%s: UTMIPLL_HW_PWRDN_CFG0:0x%08x\n",
+		__func__, read32(CLK_RST_REG(utmipll_hw_pwrdn_cfg0)));
+	printk(BIOS_DEBUG, "%s: UTMIP_PLL_CFG0:0x%08x\n",
+		__func__, read32(CLK_RST_REG(utmip_pll_cfg0)));
+	printk(BIOS_DEBUG, "%s: UTMIP_PLL_CFG1:0x%08x\n",
+		__func__, read32(CLK_RST_REG(utmip_pll_cfg1)));
+	printk(BIOS_DEBUG, "%s: UTMIP_PLL_CFG2:0x%08x\n",
+		__func__, read32(CLK_RST_REG(utmip_pll_cfg2)));
 }
 
 /* Graphics just has to be different. There's a few more bits we
diff --git a/src/soc/nvidia/tegra210/include/soc/clk_rst.h b/src/soc/nvidia/tegra210/include/soc/clk_rst.h
index 60ee112..817a041 100644
--- a/src/soc/nvidia/tegra210/include/soc/clk_rst.h
+++ b/src/soc/nvidia/tegra210/include/soc/clk_rst.h
@@ -428,14 +428,19 @@ enum {
 #define UTMIP_CFG1_FORCE_PLL_ACTIVE_POWERDOWN_DISABLE	(0 << 12)
 #define UTMIP_CFG1_FORCE_PLL_ENABLE_POWERDOWN_DISABLE	(0 << 14)
 #define UTMIP_CFG1_FORCE_PLL_ENABLE_POWERUP_ENABLE	(1 << 15)
-#define UTMIP_CFG1_FORCE_PLLU_POWERDOWN_ENABLE	(1 << 16)
+#define UTMIP_CFG1_FORCE_PLLU_POWERDOWN_ENABLE		(1 << 16)
 #define UTMIP_CFG1_PLLU_ENABLE_DLY_COUNT_SHIFT		(27)
 #define UTMIP_CFG2_FORCE_PD_SAMP_A_POWERDOWN_DISABLE	(0 << 0)
+#define UTMIP_CFG2_FORCE_PD_SAMP_A_POWERUP_ENABLE	(1 << 1)
 #define UTMIP_CFG2_FORCE_PD_SAMP_B_POWERDOWN_DISABLE	(0 << 2)
+#define UTMIP_CFG2_FORCE_PD_SAMP_B_POWERUP_ENABLE	(1 << 3)
 #define UTMIP_CFG2_FORCE_PD_SAMP_C_POWERDOWN_DISABLE	(0 << 4)
+#define UTMIP_CFG2_FORCE_PD_SAMP_C_POWERUP_ENABLE	(1 << 5)
+#define UTMIP_CFG2_FORCE_PD_SAMP_D_POWERDOWN_DISABLE	(0 << 24)
+#define UTMIP_CFG2_FORCE_PD_SAMP_D_POWERUP_ENABLE	(1 << 25)
 #define UTMIP_CFG2_PLLU_STABLE_COUNT_SHIFT		(6)
 #define UTMIP_CFG2_PLL_ACTIVE_DLY_COUNT_SHIFT		(18)
-#define UTMIP_CFG2_PHY_XTAL_CLOCKEN		(1U << 30)
+#define UTMIP_CFG2_PHY_XTAL_CLOCKEN			(1U << 30)
 
 /* Generic, indiscriminate divisor mask. May catch some innocent bystander bits
  * on the side that we don't particularly care about. */