[coreboot-gerrit] Patch set updated for coreboot: Revert "sandy/ivybridge: use LAPIC timer in SMM"

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10811

-gerrit

commit fc820995a75d463a95995e3b64ef0adbbf4206f8
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Mon Jul 6 18:18:22 2015 +0200

    Revert "sandy/ivybridge: use LAPIC timer in SMM"
    
    This reverts commit a3aa8da2acec28670b724b7897ae054592746674.
    There's still a problem for Chrome OS builds, but we need to fix it in a way
    that doesn't make everything else explode.
    
    Change-Id: If4d69a122b020e5b2d2316b8da225435f6b2bef0
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 src/cpu/x86/lapic/Makefile.inc                 |  3 --
 src/northbridge/intel/sandybridge/Makefile.inc |  1 +
 src/northbridge/intel/sandybridge/udelay.c     | 55 ++++++++++++++++++++++++++
 3 files changed, 56 insertions(+), 3 deletions(-)

diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc
index baa8292..3061024 100644
--- a/src/cpu/x86/lapic/Makefile.inc
+++ b/src/cpu/x86/lapic/Makefile.inc
@@ -3,8 +3,5 @@ ramstage-y += lapic_cpu_init.c
 ramstage-y += secondary.S
 romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
 ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
-ifeq ($(CONFIG_LAPIC_MONOTONIC_TIMER),y)
-smm-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
-endif
 romstage-y += boot_cpu.c
 ramstage-y += boot_cpu.c
diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc
index 60765f2..cf79459 100644
--- a/src/northbridge/intel/sandybridge/Makefile.inc
+++ b/src/northbridge/intel/sandybridge/Makefile.inc
@@ -42,6 +42,7 @@ romstage-y += early_init.c
 romstage-y += report_platform.c
 romstage-y += ../../../arch/x86/lib/walkcbfs.S
 
+smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
 # We don't ship that, but booting without it is bound to fail
diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c
new file mode 100644
index 0000000..b150253
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/udelay.c
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <delay.h>
+#include <stdint.h>
+#include <cpu/x86/tsc.h>
+#include <cpu/x86/msr.h>
+
+/**
+ * Intel Sandy Bridge/Ivy Bridge CPUs always run the TSC at BCLK=100MHz
+ */
+
+void udelay(u32 us)
+{
+	u32 dword;
+	tsc_t tsc, tsc1, tscd;
+	msr_t msr;
+	u32 fsb = 100, divisor;
+	u32 d;			/* ticks per us */
+
+	msr = rdmsr(0xce);
+	divisor = (msr.lo >> 8) & 0xff;
+
+	d = fsb * divisor;	/* On Core/Core2 this is divided by 4 */
+	multiply_to_tsc(&tscd, us, d);
+
+	tsc1 = rdtsc();
+	dword = tsc1.lo + tscd.lo;
+	if ((dword < tsc1.lo) || (dword < tscd.lo)) {
+		tsc1.hi++;
+	}
+	tsc1.lo = dword;
+	tsc1.hi += tscd.hi;
+
+	do {
+		tsc = rdtsc();
+	} while ((tsc.hi < tsc1.hi)
+		 || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
+}