[coreboot-gerrit] New patch to review for coreboot: nvidia/l1_2pvv: whitespace: remove spaces that are followed by tab

Jonathan A. Kollasch (jakllsch@kollasch.net) gerrit at coreboot.org
Sun Jul 5 01:50:18 CEST 2015


Jonathan A. Kollasch (jakllsch at kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10796

-gerrit

commit f2715a1fde775284a4ae083dcd0109a9ca44dffc
Author: Jonathan A. Kollasch <jakllsch at kollasch.net>
Date:   Sat Jul 4 18:44:56 2015 -0500

    nvidia/l1_2pvv: whitespace: remove spaces that are followed by tab
    
    Change-Id: Ia84df2f4467e102fd5f675dba6432996584d78c1
    Signed-off-by: Jonathan A. Kollasch <jakllsch at kollasch.net>
---
 src/mainboard/nvidia/l1_2pvv/resourcemap.c | 2 +-
 src/mainboard/nvidia/l1_2pvv/romstage.c    | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/nvidia/l1_2pvv/resourcemap.c b/src/mainboard/nvidia/l1_2pvv/resourcemap.c
index b1a6309..62b927b 100644
--- a/src/mainboard/nvidia/l1_2pvv/resourcemap.c
+++ b/src/mainboard/nvidia/l1_2pvv/resourcemap.c
@@ -270,7 +270,7 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the highest bus number in configuration region i
 		 */
 //		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */
-//		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 	*/
+//		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 */
 		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
 
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index 21112fb..b5731c8 100644
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -176,7 +176,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	// fidvid change will issue one LDTSTOP and the HT change will be effective too
 	if (needs_reset) {
 		printk(BIOS_INFO, "ht reset -\n");
-	      	soft_reset();
+		soft_reset();
 	}
 	allow_all_aps_stop(bsp_apicid);
 



More information about the coreboot-gerrit mailing list