[coreboot-gerrit] Patch set updated for coreboot: Braswell: Update the ACPI tables

[Leroy P Leahy (leroy.p.leahy@intel.com)]

Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10748

-gerrit

commit d17a5cd6001bc425bfbac5084dea6449cbd20b74
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Tue Jun 30 15:25:44 2015 -0700

    Braswell: Update the ACPI tables
    
    Build the GNVS pointer and add it to the DSDT.
    Add the opregion for GOP support.
    Build the SSDT entry and add it to the RSDP.
    The arch/x86/boot/acpi.c module adds the HPET entry, remove the
    acpi_create_intel_hpet routine.
    
    BRANCH=none
    BUG=None
    TEST=Build and run on cyan
    
    Change-Id: I8c7ae36b24da583928ad2532f611a855268b51f9
    Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
 src/soc/intel/braswell/acpi.c             | 100 +++++++++++++++++++++---------
 src/soc/intel/braswell/include/soc/acpi.h |   5 +-
 src/soc/intel/braswell/southcluster.c     |   4 ++
 3 files changed, 77 insertions(+), 32 deletions(-)

diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c
index 47d7f4f..e1065e2 100644
--- a/src/soc/intel/braswell/acpi.c
+++ b/src/soc/intel/braswell/acpi.c
@@ -27,6 +27,7 @@
 #include <cbfs.h>
 #include <cbmem.h>
 #include <console/console.h>
+#include <cpu/cpu.h>
 #include <cpu/intel/turbo.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/smm.h>
@@ -142,37 +143,6 @@ static int acpi_sci_irq(void)
 	return sci_irq;
 }
 
-void acpi_create_intel_hpet(acpi_hpet_t *hpet)
-{
-	acpi_header_t *header = &(hpet->header);
-	acpi_addr_t *addr = &(hpet->addr);
-
-	memset((void *) hpet, 0, sizeof(acpi_hpet_t));
-
-	/* fill out header fields */
-	memcpy(header->signature, "HPET", 4);
-	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
-	memcpy(header->asl_compiler_id, ASLC, 4);
-
-	header->length = sizeof(acpi_hpet_t);
-	header->revision = 1;
-
-	/* fill out HPET address */
-	addr->space_id = 0;	/* Memory */
-	addr->bit_width = 64;
-	addr->bit_offset = 0;
-	addr->addrl = (unsigned long long)HPET_BASE_ADDRESS & 0xffffffff;
-	addr->addrh = (unsigned long long)HPET_BASE_ADDRESS >> 32;
-
-	hpet->id = 0x8086a201;	/* Intel */
-	hpet->number = 0x00;
-	hpet->min_tick = 0x0080;
-
-	header->checksum =
-	    acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
-}
-
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
 	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
@@ -506,6 +476,74 @@ unsigned long acpi_madt_irq_overrides(unsigned long current)
 	return current;
 }
 
+#define ALIGN_CURRENT current = (ALIGN(current, 16))
+
+unsigned long southcluster_write_acpi_tables(device_t device,
+					     unsigned long current,
+					     struct acpi_rsdp *rsdp)
+{
+	acpi_header_t *ssdt2;
+
+	current = acpi_write_hpet(device, current, rsdp);
+	ALIGN_CURRENT;
+
+#if CONFIG_GOP_SUPPORT
+	igd_opregion_t *opregion;
+
+	printk(BIOS_DEBUG, "ACPI:    * IGD OpRegion\n");
+	opregion = (igd_opregion_t *)current;
+	init_igd_opregion(opregion);
+	current += sizeof(igd_opregion_t);
+	ALIGN_CURRENT;
+#endif
+
+	ssdt2 = (acpi_header_t *)current;
+	memset(ssdt2, 0, sizeof(acpi_header_t));
+	acpi_create_serialio_ssdt(ssdt2);
+	if (ssdt2->length) {
+		current += ssdt2->length;
+		acpi_add_table(rsdp, ssdt2);
+		printk(BIOS_DEBUG, "ACPI:     * SSDT2 @ %p Length %x\n",ssdt2,
+		       ssdt2->length);
+		ALIGN_CURRENT;
+	} else {
+		ssdt2 = NULL;
+		printk(BIOS_DEBUG, "ACPI:     * SSDT2 not generated.\n");
+	}
+
+	printk(BIOS_DEBUG, "current = %lx\n", current);
+
+	return current;
+}
+
+void southcluster_inject_dsdt(device_t device)
+{
+	global_nvs_t *gnvs;
+
+	gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
+	if (!gnvs) {
+		gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs));
+		if (gnvs)
+			memset(gnvs, 0, sizeof(*gnvs));
+	}
+
+	if (gnvs) {
+		acpi_create_gnvs(gnvs);
+		acpi_save_gnvs((unsigned long)gnvs);
+		/* And tell SMI about it */
+		smm_setup_structures(gnvs, NULL, NULL);
+
+		/* Add it to DSDT.  */
+		acpigen_write_scope("\\");
+		acpigen_write_name_dword("NVSA", (u32) gnvs);
+		acpigen_pop_len();
+	}
+}
+
+__attribute__((weak)) void acpi_create_serialio_ssdt(acpi_header_t *ssdt)
+{
+}
+
 #if CONFIG_GOP_SUPPORT
 /* Reading VBT table from flash */
 static void get_fsp_vbt(igd_opregion_t *opregion)
diff --git a/src/soc/intel/braswell/include/soc/acpi.h b/src/soc/intel/braswell/include/soc/acpi.h
index 7f0d5d8..e694961 100644
--- a/src/soc/intel/braswell/include/soc/acpi.h
+++ b/src/soc/intel/braswell/include/soc/acpi.h
@@ -29,10 +29,13 @@
 int init_igd_opregion(igd_opregion_t *igd_opregion);
 #endif
 
-void acpi_create_intel_hpet(acpi_hpet_t *hpet);
+void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
 void acpi_fill_in_fadt(acpi_fadt_t *fadt);
 unsigned long acpi_madt_irq_overrides(unsigned long current);
 void acpi_init_gnvs(global_nvs_t *gnvs);
+void southcluster_inject_dsdt(device_t device);
+unsigned long southcluster_write_acpi_tables(device_t device,
+	unsigned long current, struct acpi_rsdp *rsdp);
 
 #endif /* _SOC_ACPI_H_ */
 
diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c
index 5a3ad9d..a3877d6 100644
--- a/src/soc/intel/braswell/southcluster.c
+++ b/src/soc/intel/braswell/southcluster.c
@@ -21,6 +21,7 @@
 
 #include <arch/io.h>
 #include <arch/acpi.h>
+#include <arch/acpigen.h>
 #include <bootstate.h>
 #include <cbmem.h>
 #include "chip.h"
@@ -31,6 +32,7 @@
 #include <device/pci_ids.h>
 #include <pc80/mc146818rtc.h>
 #include <romstage_handoff.h>
+#include <soc/acpi.h>
 #include <soc/iomap.h>
 #include <soc/irq.h>
 #include <soc/lpc.h>
@@ -449,6 +451,8 @@ static struct device_operations device_ops = {
 	.read_resources		= sc_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= NULL,
+	.acpi_inject_dsdt_generator = southcluster_inject_dsdt,
+	.write_acpi_tables	= southcluster_write_acpi_tables,
 	.init			= sc_init,
 	.enable			= southcluster_enable_dev,
 	.scan_bus		= scan_lpc_bus,