[coreboot-gerrit] New patch to review for coreboot: sandy/ivybridge: use LAPIC timer in SMM

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10762

-gerrit

commit bb55a5d116b55f024286889d0f1a86d3a83c7f23
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Wed Jul 1 16:58:36 2015 -0700

    sandy/ivybridge: use LAPIC timer in SMM
    
    This fixes an issue with using the flash driver in SMM for writing
    the event log through an SMM call.
    
    Change-Id: If18c77634cca4563f770f09b0f0797ece24308ce
    Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
---
 src/cpu/x86/lapic/Makefile.inc                 |  3 ++
 src/northbridge/intel/sandybridge/Makefile.inc |  1 -
 src/northbridge/intel/sandybridge/udelay.c     | 55 --------------------------
 3 files changed, 3 insertions(+), 56 deletions(-)

diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc
index 3061024..baa8292 100644
--- a/src/cpu/x86/lapic/Makefile.inc
+++ b/src/cpu/x86/lapic/Makefile.inc
@@ -3,5 +3,8 @@ ramstage-y += lapic_cpu_init.c
 ramstage-y += secondary.S
 romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
 ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
+ifeq ($(CONFIG_LAPIC_MONOTONIC_TIMER),y)
+smm-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
+endif
 romstage-y += boot_cpu.c
 ramstage-y += boot_cpu.c
diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc
index cf79459..60765f2 100644
--- a/src/northbridge/intel/sandybridge/Makefile.inc
+++ b/src/northbridge/intel/sandybridge/Makefile.inc
@@ -42,7 +42,6 @@ romstage-y += early_init.c
 romstage-y += report_platform.c
 romstage-y += ../../../arch/x86/lib/walkcbfs.S
 
-smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
 # We don't ship that, but booting without it is bound to fail
diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c
deleted file mode 100644
index b150253..0000000
--- a/src/northbridge/intel/sandybridge/udelay.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <delay.h>
-#include <stdint.h>
-#include <cpu/x86/tsc.h>
-#include <cpu/x86/msr.h>
-
-/**
- * Intel Sandy Bridge/Ivy Bridge CPUs always run the TSC at BCLK=100MHz
- */
-
-void udelay(u32 us)
-{
-	u32 dword;
-	tsc_t tsc, tsc1, tscd;
-	msr_t msr;
-	u32 fsb = 100, divisor;
-	u32 d;			/* ticks per us */
-
-	msr = rdmsr(0xce);
-	divisor = (msr.lo >> 8) & 0xff;
-
-	d = fsb * divisor;	/* On Core/Core2 this is divided by 4 */
-	multiply_to_tsc(&tscd, us, d);
-
-	tsc1 = rdtsc();
-	dword = tsc1.lo + tscd.lo;
-	if ((dword < tsc1.lo) || (dword < tscd.lo)) {
-		tsc1.hi++;
-	}
-	tsc1.lo = dword;
-	tsc1.hi += tscd.hi;
-
-	do {
-		tsc = rdtsc();
-	} while ((tsc.hi < tsc1.hi)
-		 || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
-}