[coreboot-gerrit] New patch to review for coreboot: t132: Add timestamp collection support in t132
Marc Jones (marc.jones@se-eng.com)
gerrit at coreboot.org
Wed Jul 1 00:16:35 CEST 2015
Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10736
-gerrit
commit 25425ec066c291ffe5e25b6a613584aac6871809
Author: Furquan Shaikh <furquan at google.com>
Date: Mon Oct 13 14:50:08 2014 -0700
t132: Add timestamp collection support in t132
Add a region TIMESTAMP to store all the timestamps starting from bootblock to
end of romstage. At the end of romstage take all the timestamps in TIMESTAMP
region and put it into cbmem
BUG=chrome-os-partner:32973
BRANCH=None
TEST=Compiles successfully and cbmem -t prints all timestamps
Original-Change-Id: I856564de80589bede660ca6bc1275193f8a2fa4b
Original-Signed-off-by: Furquan Shaikh <furquan at google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/223110
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Original-Tested-by: Furquan Shaikh <furquan at chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan at chromium.org>
(cherry picked from commit b8ccf5731df9ca149a2a0661362e7745515bfe5e)
Signed-off-by: Marc Jones <marc.jones at se-eng.com>
Change-Id: I266e46ed691ebe5f0a20ed28b89e6e74399487a1
---
src/soc/nvidia/tegra132/Kconfig | 87 ++++++++++++++++------
src/soc/nvidia/tegra132/bootblock.c | 4 +
.../tegra132/include/soc/memlayout_vboot2.ld | 3 +-
src/soc/nvidia/tegra132/romstage.c | 5 ++
src/soc/nvidia/tegra132/verstage.c | 2 +
5 files changed, 79 insertions(+), 22 deletions(-)
diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig
index a5df92a..4c77068 100644
--- a/src/soc/nvidia/tegra132/Kconfig
+++ b/src/soc/nvidia/tegra132/Kconfig
@@ -1,37 +1,27 @@
config SOC_NVIDIA_TEGRA132
bool
default n
- select ARCH_BOOTBLOCK_ARMV4
- select ARCH_VERSTAGE_ARMV4
- select ARCH_ROMSTAGE_ARMV4
- select ARCH_RAMSTAGE_ARMV8_64
+ select ARCH_BOOTBLOCK_ARM_V4
+ select ARCH_VERSTAGE_ARM_V4
+ select ARCH_ROMSTAGE_ARM_V4
+ select ARCH_RAMSTAGE_ARM_V8_64
select BOOTBLOCK_CONSOLE
select GIC
select HAVE_MONOTONIC_TIMER
select GENERIC_UDELAY
select HAVE_HARD_RESET
select HAVE_UART_SPECIAL
+ select HAVE_UART_MEMORY_MAPPED
+ select EARLY_CONSOLE
select ARM_BOOTBLOCK_CUSTOM
+ select DYNAMIC_CBMEM
select SMP
- select ARM64_USE_SECURE_MONITOR
- select GENERIC_GPIO_LIB
+ select ARCH_USE_SECURE_MONITOR
+ select COLLECT_TIMESTAMPS
+ select HAS_PRECBMEM_TIMESTAMP_REGION
if SOC_NVIDIA_TEGRA132
-config MAINBOARD_DO_DSI_INIT
- bool "Use dsi graphics interface"
- depends on MAINBOARD_DO_NATIVE_VGA_INIT
- default n
- help
- Initialize dsi display
-
-config MAINBOARD_DO_SOR_INIT
- bool "Use dp graphics interface"
- depends on MAINBOARD_DO_NATIVE_VGA_INIT
- default n
- help
- Initialize dp display
-
config BOOTBLOCK_CPU_INIT
string
default "soc/nvidia/tegra132/bootblock.c"
@@ -40,13 +30,68 @@ config BOOTBLOCK_CPU_INIT
bootblock must load microcode or copy data from ROM before
searching for the bootblock.
+config BOOTBLOCK_ROM_OFFSET
+ hex
+ default 0x0
+
config MAX_CPUS
int
default 2
+config CBFS_HEADER_ROM_OFFSET
+ hex "offset of master CBFS header in ROM"
+ default 0x22000
+
+config CBFS_ROM_OFFSET
+ hex "offset of CBFS data in ROM"
+ default 0x22080
+
+choice CONSOLE_SERIAL_TEGRA132_UART_CHOICES
+ prompt "Serial Console UART"
+ default CONSOLE_SERIAL_TEGRA132_UARTA
+ depends on CONSOLE_SERIAL_UART
+
+config CONSOLE_SERIAL_TEGRA132_UARTA
+ bool "UARTA"
+ help
+ Serial console on UART A.
+
+config CONSOLE_SERIAL_TEGRA132_UARTB
+ bool "UARTB"
+ help
+ Serial console on UART B.
+
+config CONSOLE_SERIAL_TEGRA132_UARTC
+ bool "UARTC"
+ help
+ Serial console on UART C.
+
+config CONSOLE_SERIAL_TEGRA132_UARTD
+ bool "UARTD"
+ help
+ Serial console on UART D.
+
+config CONSOLE_SERIAL_TEGRA132_UARTE
+ bool "UARTE"
+ help
+ Serial console on UART E.
+
+endchoice
+
+config CONSOLE_SERIAL_TEGRA132_UART_ADDRESS
+ hex
+ depends on CONSOLE_SERIAL_UART
+ default 0x70006000 if CONSOLE_SERIAL_TEGRA132_UARTA
+ default 0x70006040 if CONSOLE_SERIAL_TEGRA132_UARTB
+ default 0x70006200 if CONSOLE_SERIAL_TEGRA132_UARTC
+ default 0x70006300 if CONSOLE_SERIAL_TEGRA132_UARTD
+ default 0x70006400 if CONSOLE_SERIAL_TEGRA132_UARTE
+ help
+ Map the UART names to the respective MMIO addres.
+
config MTS_DIRECTORY
string "Directory where MTS microcode files are located"
- default "3rdparty/blobs/cpu/nvidia/tegra132/current/prod"
+ default "."
help
Path to directory where MTS microcode files are located.
diff --git a/src/soc/nvidia/tegra132/bootblock.c b/src/soc/nvidia/tegra132/bootblock.c
index b19cf49..bb8a393 100644
--- a/src/soc/nvidia/tegra132/bootblock.c
+++ b/src/soc/nvidia/tegra132/bootblock.c
@@ -26,6 +26,7 @@
#include <soc/clock.h>
#include <soc/nvidia/tegra/apbmisc.h>
#include <soc/power.h>
+#include <timestamp.h>
#define BCT_OFFSET_IN_BIT 0x50
#define ODMDATA_OFFSET_IN_BCT 0x6A8
@@ -57,6 +58,9 @@ void __attribute__((weak)) bootblock_mainboard_early_init(void)
void main(void)
{
+ timestamp_early_init(0);
+ timestamp_add_now(TS_START_BOOTBLOCK);
+
// enable JTAG at the earliest stage
enable_jtag();
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
index a834f99..5f59f8d 100644
--- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
@@ -36,7 +36,8 @@ SECTIONS
PRERAM_CBFS_CACHE(0x40002000, 72K)
VBOOT2_WORK(0x40014000, 16K)
STACK(0x40018000, 2K)
- BOOTBLOCK(0x40019000, 24K)
+ TIMESTAMP(0x40018800, 2K)
+ BOOTBLOCK(0x40019000, 22K)
VERSTAGE(0x4001f000, 60K)
ROMSTAGE(0x4002e000, 72K)
SRAM_END(0x40040000)
diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c
index 6476e06..ae295c0 100644
--- a/src/soc/nvidia/tegra132/romstage.c
+++ b/src/soc/nvidia/tegra132/romstage.c
@@ -31,6 +31,7 @@
#include <soc/sdram_configs.h>
#include <soc/romstage.h>
#include <timer.h>
+#include <timestamp.h>
void __attribute__((weak)) romstage_mainboard_init(void)
{
@@ -39,6 +40,8 @@ void __attribute__((weak)) romstage_mainboard_init(void)
void romstage(void)
{
+ timestamp_add_now(TS_START_ROMSTAGE);
+
console_init();
exception_init();
@@ -52,6 +55,8 @@ void romstage(void)
printk(BIOS_INFO, "T132 romstage: sdram_init done\n");
#endif
+ timestamp_add_now(TS_AFTER_INITRAM);
+
/*
* Trust Zone needs to be initialized after the DRAM initialization
* because carveout registers are programmed during DRAM init.
diff --git a/src/soc/nvidia/tegra132/verstage.c b/src/soc/nvidia/tegra132/verstage.c
index b70028a..d6eba9a 100644
--- a/src/soc/nvidia/tegra132/verstage.c
+++ b/src/soc/nvidia/tegra132/verstage.c
@@ -24,6 +24,7 @@
#include <console/console.h>
#include <soc/verstage.h>
#include <program_loading.h>
+#include <timestamp.h>
void __attribute__((weak)) verstage_mainboard_init(void)
{
@@ -33,6 +34,7 @@ void __attribute__((weak)) verstage_mainboard_init(void)
static void verstage(void)
{
console_init();
+ timestamp_add_now(TS_START_VBOOT);
exception_init();
verstage_mainboard_init();
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