[coreboot-gerrit] Patch merged into coreboot/master: e1e11e6 intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit e1e11e63afab8e461ac7e6466c9a7f9f47a10702
Author: York Yang <york.yang at intel.com>
Date:   Mon Jan 5 10:04:45 2015 -0700

    intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP
    
    Rangeley POST-GOLD 2 FSP added PCIe ports de-emphasis configuration
    by UPD input. Update UPD_DATA_REGION structure for matching up this
    FSP change.
    
    PcdCustomerRevision is a debugging aid that will be output to debug
    message in FSP. When needed, it can be customized by BCT tool for tracking
    BCT configurations.
    
    Change-Id: I6d4138c9d8bbb9c89f24c77f976dbc760d626a9b
    Signed-off-by: York Yang <york.yang at intel.com>
    Reviewed-on: http://review.coreboot.org/8107
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <gaumless at gmail.com>


See http://review.coreboot.org/8107 for details.

-gerrit