[coreboot-gerrit] New patch to review for coreboot: 859f412 bd82x6x/xhci: Set mask of ports switchable between USB2 and USB3.

[Vladimir Serbinenko (phcoder@gmail.com)]

Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8312

-gerrit

commit 859f4127a39496d850d2dd8bc6999d4d42947d47
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date:   Sat Jan 31 17:45:50 2015 +0100

    bd82x6x/xhci: Set mask of ports switchable between USB2 and USB3.
    
    Change-Id: Ica1cc90715c1810668e3f4f7282e5757a5688483
    Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
 src/southbridge/intel/bd82x6x/chip.h     | 2 ++
 src/southbridge/intel/bd82x6x/usb_xhci.c | 4 ++++
 2 files changed, 6 insertions(+)

diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index 290bb05..e4453d1 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -89,6 +89,8 @@ struct southbridge_intel_bd82x6x_config {
 	int docking_supported;
 
 	uint8_t pcie_hotplug_map[8];
+
+	uint32_t usb2_3_os_switchable_map;
 };
 
 #endif				/* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */
diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c
index 19c419f..1956f8a 100644
--- a/src/southbridge/intel/bd82x6x/usb_xhci.c
+++ b/src/southbridge/intel/bd82x6x/usb_xhci.c
@@ -29,6 +29,7 @@
 static void usb_xhci_init(struct device *dev)
 {
 	u32 reg32;
+	struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
 
 	printk(BIOS_DEBUG, "XHCI: Setting up controller.. ");
 
@@ -37,6 +38,9 @@ static void usb_xhci_init(struct device *dev)
 	reg32 |= 1;
 	pci_write_config32(dev, 0x44, reg32);
 
+	pci_write_config32(dev, 0xd4, config->usb2_3_os_switchable_map);
+	pci_write_config32(dev, 0xdc, config->usb2_3_os_switchable_map);
+
 	/* Enable clock gating */
 	reg32 = pci_read_config32(dev, 0x40);
 	reg32 &= ~((1 << 20) | (1 << 21));