[coreboot-gerrit] Patch set updated for coreboot: 8b668f2 intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP

[York Yang (york.yang@intel.com)]

York Yang (york.yang at intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8107

-gerrit

commit 8b668f2f2318f8d8f5162e247c20115fb6969158
Author: York Yang <york.yang at intel.com>
Date:   Mon Jan 5 10:04:45 2015 -0700

    intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP
    
    Rangeley POST-GOLD 2 FSP added PCIe ports de-emphasis configuration
    by UPD input. Update UPD_DATA_REGION structure for matching up this
    FSP change.
    
    PcdCustomerRevision is a debugging aid that will be output to debug
    message in FSP. It intend to be customized by BCT tool for tracking
    BCT configurations.
    
    Change-Id: I6d4138c9d8bbb9c89f24c77f976dbc760d626a9b
    Signed-off-by: York Yang <york.yang at intel.com>
---
 src/northbridge/intel/fsp_rangeley/chip.h                 | 10 ++++++++++
 src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c |  7 +++++++
 src/southbridge/intel/fsp_rangeley/chip.h                 |  0
 src/vendorcode/intel/fsp/rangeley/include/fspvpd.h        | 15 ++++++++++-----
 4 files changed, 27 insertions(+), 5 deletions(-)

diff --git a/src/northbridge/intel/fsp_rangeley/chip.h b/src/northbridge/intel/fsp_rangeley/chip.h
old mode 100644
new mode 100755
index 80a22bf..d3828c7
--- a/src/northbridge/intel/fsp_rangeley/chip.h
+++ b/src/northbridge/intel/fsp_rangeley/chip.h
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2015 Intel Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -57,6 +58,15 @@ struct northbridge_intel_fsp_rangeley_config {
 #define BIFURCATION_8_8     3
 #define BIFURCATION_16      4
 	uint8_t Bifurcation;
+
+	/* PCIe port de-emphasis control */
+	#define  DE_EMPHASIS_DEFAULT            0
+	#define  DE_EMPHASIS_MINUS_6_0_DB       1
+	#define  DE_EMPHASIS_MINUS_3_5_DB       2
+	uint8_t  PcdPcieRootPort1DeEmphasis;
+	uint8_t  PcdPcieRootPort2DeEmphasis;
+	uint8_t  PcdPcieRootPort3DeEmphasis;
+	uint8_t  PcdPcieRootPort4DeEmphasis;
 };
 
 #endif
diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
old mode 100644
new mode 100755
index ae95087..3f8690a
--- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
+++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015 Intel Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -143,6 +144,12 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData)
 				break;
 		}
 	}
+
+	/* Set PCIe de-emphasis */
+	UPD_DEFAULT_CHECK(PcdPcieRootPort1DeEmphasis);
+	UPD_DEFAULT_CHECK(PcdPcieRootPort2DeEmphasis);
+	UPD_DEFAULT_CHECK(PcdPcieRootPort3DeEmphasis);
+	UPD_DEFAULT_CHECK(PcdPcieRootPort4DeEmphasis);
 }
 
 /* Set up the Rangeley specific structures for the call into the FSP */
diff --git a/src/southbridge/intel/fsp_rangeley/chip.h b/src/southbridge/intel/fsp_rangeley/chip.h
old mode 100644
new mode 100755
diff --git a/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h b/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h
old mode 100644
new mode 100755
index 12ac2be..fba38a0
--- a/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h
+++ b/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h
@@ -1,6 +1,6 @@
 /** @file
 
-Copyright (C) 2013, Intel Corporation
+Copyright (C) 2013-2014 Intel Corporation
 
 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
@@ -57,16 +57,21 @@ typedef struct _UPD_DATA_REGION {
   UINT8                       PcdEnableIQAT;                 /* Offset 0x0033 */
   UINT8                       PcdEnableUsb20;                /* Offset 0x0034 */
   UINT8                       PcdBifurcation;                /* Offset 0x0035 */
-  UINT8                       UnusedUpdSpace2[10];           /* Offset 0x0036 */
+  UINT8                       PcdPcieRootPort1DeEmphasis;    /* Offset 0x0036 */
+  UINT8                       PcdPcieRootPort2DeEmphasis;    /* Offset 0x0037 */
+  UINT8                       PcdPcieRootPort3DeEmphasis;    /* Offset 0x0038 */
+  UINT8                       PcdPcieRootPort4DeEmphasis;    /* Offset 0x0039 */
+  UINT8                       UnusedUpdSpace2[6];            /* Offset 0x003A */
   UINT8                       PcdPrintDebugMessages;         /* Offset 0x0040 */
   UINT8                       PcdFastboot;                   /* Offset 0x0041 */
   UINT8                       PcdEccSupport;                 /* Offset 0x0042 */
-  UINT8                       UnusedUpdSpace3[13];           /* Offset 0x0043 */
-  UINT16                      PcdRegionTerminator;           /* Offset 0x0050 */
+  UINT8                       PcdCustomerRevision[32];       /* Offset 0x0043 */
+  UINT8                       UnusedUpdSpace3[13];           /* Offset 0x0063 */
+  UINT16                      PcdRegionTerminator;           /* Offset 0x0070 */
 } UPD_DATA_REGION;
 
 #define VPD_IMAGE_ID    0x562D474E524E5641        /* 'AVNRNG-V' */
-#define VPD_IMAGE_REV   0x00000101
+#define VPD_IMAGE_REV   0x00000102
 
 typedef struct _VPD_DATA_REGION {
   UINT64                      PcdVpdRegionSign;              /* Offset 0x0000 */