[coreboot-gerrit] Patch set updated for coreboot: 2c1cdba FSP platforms: Clear area in CAR for cbmem

[Martin Roth (gaumless@gmail.com)]

Martin Roth (gaumless at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8195

-gerrit

commit 2c1cdba6ac682623e14354e51dea0887571ec124
Author: Martin Roth <gaumless at gmail.com>
Date:   Sun Jan 11 14:58:47 2015 -0700

    FSP platforms: Clear area in CAR for cbmem
    
    cbmem requires that the memory at _car_data_start be cleared or it
    does not get used.
    
    This patch clears the CAR area used by cbmem.  Most of the CAR
    implementations clear the entire area when setting up the CAR area.
    The FSP loads the entire are with a pattern instead, so the cbmem
    area needs to be cleared.
    
    Change-Id: I829ddc26133353a784dfc01729af9b3bf427e889
    Signed-off-by: Martin Roth <gaumless at gmail.com>
---
 src/drivers/intel/fsp/cache_as_ram.inc | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/drivers/intel/fsp/cache_as_ram.inc b/src/drivers/intel/fsp/cache_as_ram.inc
index 9e8b2a2..8c04dc7 100644
--- a/src/drivers/intel/fsp/cache_as_ram.inc
+++ b/src/drivers/intel/fsp/cache_as_ram.inc
@@ -42,6 +42,8 @@
 #ifndef CONFIG_CPU_MICROCODE_CBFS_LOC
 # error "CONFIG_CPU_MICROCODE_CBFS_LOC must be set."
 #endif
+.extern _car_data_start
+.extern _car_data_end
 
 #define LHLT_DELAY	0x50000		/* I/O delay between post codes on failure */
 
@@ -95,6 +97,14 @@ CAR_init_done:
 	movl  %esp, %ebp
 	pushl %ebx
 
+	/* Clear the cbmem CAR memory region. */
+	movl	$_car_data_start, %edi
+	movl	$_car_data_end, %ecx
+	sub	%edi, %ecx
+	shr	$2, %ecx
+	xorl	%eax, %eax
+	rep	stosl
+
 before_romstage:
 	post_code(0x23)