[coreboot-gerrit] New patch to review for coreboot: b97267e intel/cpu: >= nehalem: add comments to msr finalize's

[Alexander Couzens (lynxis@fe80.eu)]

Alexander Couzens (lynxis at fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8294

-gerrit

commit b97267e47b7e9b14513898e105d5dc32dcc887c9
Author: Alexander Couzens <lynxis at fe80.eu>
Date:   Wed Jan 28 01:51:04 2015 +0100

    intel/cpu: >= nehalem: add comments to msr finalize's
    
    Improve documentation of lock down MSRs in finalize().
    Most of these aren't documented in public MSRs
    
    Change-Id: I4fc47bb9b71bdd7907aae65fc18b419a17ae8547
    Signed-off-by: Alexander Couzens <lynxis at fe80.eu>
---
 src/cpu/intel/fsp_model_206ax/finalize.c |  5 +++++
 src/cpu/intel/haswell/finalize.c         |  5 +++++
 src/cpu/intel/model_2065x/finalize.c     | 23 +++++------------------
 src/cpu/intel/model_2065x/model_2065x.h  | 10 ----------
 src/cpu/intel/model_206ax/finalize.c     |  5 +++++
 5 files changed, 20 insertions(+), 28 deletions(-)

diff --git a/src/cpu/intel/fsp_model_206ax/finalize.c b/src/cpu/intel/fsp_model_206ax/finalize.c
index 4ed5d1e..179d978 100644
--- a/src/cpu/intel/fsp_model_206ax/finalize.c
+++ b/src/cpu/intel/fsp_model_206ax/finalize.c
@@ -43,6 +43,8 @@ static void msr_set_bit(unsigned reg, unsigned bit)
 
 void intel_model_206ax_finalize_smm(void)
 {
+	/* Look into Bios Writer's Guide for the meaning of these MSR */
+	/* Lock C-State MSR */
 	msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
 
 	/* Lock AES-NI only if supported */
@@ -67,6 +69,9 @@ void intel_model_206ax_finalize_smm(void)
 	msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
 #endif
 
+	/* Lock TM interupts - route thermal events to all processors */
 	msr_set_bit(MSR_MISC_PWR_MGMT, 22);
+
+	/* Lock memory configuration to protect SMM */
 	msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
 }
diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c
index 1731322..0a53a25 100644
--- a/src/cpu/intel/haswell/finalize.c
+++ b/src/cpu/intel/haswell/finalize.c
@@ -46,6 +46,8 @@ static void msr_set_bit(unsigned reg, unsigned bit)
 void intel_cpu_haswell_finalize_smm(void)
 {
 #if 0
+	/* Look into Bios Writer's Guide for the meaning of these MSR */
+	/* Lock C-State MSR */
 	msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
 
 	/* Lock AES-NI only if supported */
@@ -70,7 +72,10 @@ void intel_cpu_haswell_finalize_smm(void)
 	msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
 #endif
 
+	/* Lock TM interupts - route thermal events to all processors */
 	msr_set_bit(MSR_MISC_PWR_MGMT, 22);
+
+	/* Lock memory configuration to protect SMM */
 	msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
 #endif
 }
diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c
index b37a84c..94a02c0 100644
--- a/src/cpu/intel/model_2065x/finalize.c
+++ b/src/cpu/intel/model_2065x/finalize.c
@@ -44,30 +44,17 @@ static void msr_set_bit(unsigned reg, unsigned bit)
 
 void intel_model_2065x_finalize_smm(void)
 {
+	/* Look into Bios Writer's Guide for the meaning of these MSR */
+	/* Lock C-State MSR */
 	msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
 
 	/* Lock AES-NI only if supported */
 	if (cpuid_ecx(1) & (1 << 25))
 		msr_set_bit(MSR_FEATURE_CONFIG, 0);
 
-#ifdef LOCK_POWER_CONTROL_REGISTERS
-	/*
-	 * Lock the power control registers.
-	 *
-	 * These registers can be left unlocked if modifying power
-	 * limits from the OS is desirable. Modifying power limits
-	 * from the OS can be especially useful for experimentation
-	 * during  early phases of system bringup while the thermal
-	 * power envelope is being proven.
-	 */
-
-	msr_set_bit(MSR_PP0_CURRENT_CONFIG, 31);
-	msr_set_bit(MSR_PP1_CURRENT_CONFIG, 31);
-	msr_set_bit(MSR_PKG_POWER_LIMIT, 63);
-	msr_set_bit(MSR_PP0_POWER_LIMIT, 31);
-	msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
-#endif
-
+	/* Lock TM interupts - route thermal events to all processors */
 	msr_set_bit(MSR_MISC_PWR_MGMT, 22);
+
+	/* Lock memory configuration to protect SMM */
 	msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
 }
diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h
index f9dc7e8..454f7be 100644
--- a/src/cpu/intel/model_2065x/model_2065x.h
+++ b/src/cpu/intel/model_2065x/model_2065x.h
@@ -74,16 +74,6 @@
 #define  PKG_POWER_LIMIT_TIME_SHIFT	17
 #define  PKG_POWER_LIMIT_TIME_MASK	0x7f
 
-#define MSR_PP0_CURRENT_CONFIG		0x601
-#define  PP0_CURRENT_LIMIT		(112 << 3) /* 112 A */
-#define MSR_PP1_CURRENT_CONFIG		0x602
-#define  PP1_CURRENT_LIMIT_SNB		(35 << 3) /* 35 A */
-#define  PP1_CURRENT_LIMIT_IVB		(50 << 3) /* 50 A */
-#define MSR_PKG_POWER_SKU_UNIT		0x606
-#define MSR_PKG_POWER_SKU		0x614
-#define MSR_PP0_POWER_LIMIT		0x638
-#define MSR_PP1_POWER_LIMIT		0x640
-
 #define IVB_CONFIG_TDP_MIN_CPUID	0x306a2
 #define MSR_CONFIG_TDP_NOMINAL		0x648
 #define MSR_CONFIG_TDP_LEVEL1		0x649
diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c
index 2c215a4..6d16c95 100644
--- a/src/cpu/intel/model_206ax/finalize.c
+++ b/src/cpu/intel/model_206ax/finalize.c
@@ -44,6 +44,8 @@ static void msr_set_bit(unsigned reg, unsigned bit)
 
 void intel_model_206ax_finalize_smm(void)
 {
+	/* Look into Bios Writer's Guide for the meaning of these MSR */
+	/* Lock C-State MSR */
 	msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
 
 	/* Lock AES-NI only if supported */
@@ -68,6 +70,9 @@ void intel_model_206ax_finalize_smm(void)
 	msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
 #endif
 
+	/* Lock TM interupts - route thermal events to all processors */
 	msr_set_bit(MSR_MISC_PWR_MGMT, 22);
+
+	/* Lock memory configuration to protect SMM */
 	msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
 }