[coreboot-gerrit] Patch set updated for coreboot: 19bb78c CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEM
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Tue Jan 27 20:00:14 CET 2015
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7888
-gerrit
commit 19bb78c2fda2c495dec95b700f384ed3659fa071
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Mon Dec 22 12:28:07 2014 +0200
CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEM
The name was always obscure and confusing. Instead define cbmem_top()
directly in the chipset code for x86 like on ARMs.
TODO: Check TSEG alignment, it used for MTRR programming.
Change-Id: Ibbe5f05ab9c7d87d09caa673766cd17d192cd045
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/arch/x86/boot/cbmem.c | 9 ++---
src/cpu/intel/haswell/romstage.c | 4 +-
src/include/cbmem.h | 4 +-
src/mainboard/emulation/qemu-i440fx/memory.c | 4 +-
src/northbridge/intel/fsp_rangeley/raminit.c | 14 ++++---
src/northbridge/intel/fsp_sandybridge/Makefile.inc | 2 +
.../intel/fsp_sandybridge/northbridge.c | 10 -----
src/northbridge/intel/fsp_sandybridge/ram_calc.c | 38 +++++++++++++++++
src/northbridge/intel/fsp_sandybridge/raminit.c | 8 ----
src/northbridge/intel/gm45/ram_calc.c | 7 +++-
src/northbridge/intel/haswell/ram_calc.c | 11 +++--
src/northbridge/intel/i945/ram_calc.c | 11 +++--
src/northbridge/intel/nehalem/ram_calc.c | 11 +++--
src/northbridge/intel/sandybridge/ram_calc.c | 11 +++--
src/soc/intel/baytrail/baytrail/smm.h | 2 +-
src/soc/intel/baytrail/memmap.c | 8 ++--
src/soc/intel/broadwell/memmap.c | 13 ++++--
src/soc/intel/fsp_baytrail/Makefile.inc | 2 -
src/soc/intel/fsp_baytrail/baytrail/smm.h | 2 +-
src/soc/intel/fsp_baytrail/memmap.c | 22 +++++++++-
src/soc/intel/fsp_baytrail/raminit.c | 47 ----------------------
21 files changed, 131 insertions(+), 109 deletions(-)
diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c
index 80588c3..a145223 100644
--- a/src/arch/x86/boot/cbmem.c
+++ b/src/arch/x86/boot/cbmem.c
@@ -57,23 +57,20 @@ void set_top_of_ram(uint64_t ramtop)
}
#endif /* !__PRE_RAM__ */
-#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
unsigned long __attribute__((weak)) get_top_of_ram(void)
{
printk(BIOS_WARNING, "WARNING: you need to define get_top_of_ram() for your chipset\n");
return 0;
}
-#endif
-
-#else
+#if IS_ENABLED(CONFIG_DYNAMIC_CBMEM)
void *cbmem_top(void)
{
/* Top of cbmem is at lowest usable DRAM address below 4GiB. */
return (void *)get_top_of_ram();
}
-
-#endif /* DYNAMIC_CBMEM */
+#endif
+#endif /* !DYNAMIC_CBMEM */
void cbmem_run_init_hooks(void)
{
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index bd2513f..1af5259 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -133,7 +133,7 @@ static void *setup_romstage_stack_after_car(void)
slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK);
num_mtrrs++;
- top_of_ram = get_top_of_ram();
+ top_of_ram = (uint32_t)cbmem_top();
/* Cache 8MiB below the top of ram. On haswell systems the top of
* ram under 4GiB is the start of the TSEG region. It is required to
* be 8MiB aligned. Set this area as cacheable so it can be used later
@@ -318,7 +318,7 @@ struct ramstage_cache *ramstage_cache_location(long *size)
/* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
* The top of ram is defined to be the TSEG base address. */
*size = RESERVED_SMM_SIZE;
- return (void *)(get_top_of_ram() + RESERVED_SMM_OFFSET);
+ return (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET);
}
void ramstage_cache_invalid(struct ramstage_cache *cache)
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 88d2bfe..05708da 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -190,6 +190,8 @@ void backup_top_of_ram(uint64_t ramtop);
void cbmem_late_set_table(uint64_t base, uint64_t size);
#endif
+unsigned long get_top_of_ram(void);
+
void get_cbmem_table(uint64_t *base, uint64_t *size);
struct cbmem_entry *get_cbmem_toc(void);
@@ -201,8 +203,6 @@ static inline const struct cbmem_entry *cbmem_entry_find(uint32_t id)
/* Common API between cbmem and dynamic cbmem. */
-unsigned long get_top_of_ram(void);
-
/* Returns 0 if old cbmem was recovered. Recovery is only attempted if
* s3resume is non-zero. */
int cbmem_recovery(int s3resume);
diff --git a/src/mainboard/emulation/qemu-i440fx/memory.c b/src/mainboard/emulation/qemu-i440fx/memory.c
index a189d75..d43b4e9 100644
--- a/src/mainboard/emulation/qemu-i440fx/memory.c
+++ b/src/mainboard/emulation/qemu-i440fx/memory.c
@@ -40,7 +40,7 @@ static unsigned long qemu_get_memory_size(void)
return tomk;
}
-unsigned long get_top_of_ram(void)
+void *cbmem_top(void)
{
- return qemu_get_memory_size() * 1024;
+ return (void *) (qemu_get_memory_size() * 1024);
}
diff --git a/src/northbridge/intel/fsp_rangeley/raminit.c b/src/northbridge/intel/fsp_rangeley/raminit.c
index 3513c0f..9626745 100644
--- a/src/northbridge/intel/fsp_rangeley/raminit.c
+++ b/src/northbridge/intel/fsp_rangeley/raminit.c
@@ -26,19 +26,23 @@
#include "northbridge.h"
#include <drivers/intel/fsp/fsp_util.h>
-unsigned long get_top_of_ram(void)
+static uintptr_t smm_region_start(void)
{
/*
* Calculate the top of usable (low) DRAM.
* The FSP's reserved memory sits just below the SMM region,
* allowing calculation of the top of usable memory.
*/
- u32 tom = sideband_read(B_UNIT, BMBOUND);
- u32 bsmmrrl = sideband_read(B_UNIT, BSMMRRL) << 20;
+ uintptr_t tom = sideband_read(B_UNIT, BMBOUND);
+ uintptr_t bsmmrrl = sideband_read(B_UNIT, BSMMRRL) << 20;
if (bsmmrrl) {
tom = bsmmrrl;
}
- tom -= FSP_RESERVE_MEMORY_SIZE;
- return (unsigned long) tom;
+ return tom;
+}
+
+void *cbmem_top(void)
+{
+ return (void *) (smm_region_start() - FSP_RESERVE_MEMORY_SIZE);
}
diff --git a/src/northbridge/intel/fsp_sandybridge/Makefile.inc b/src/northbridge/intel/fsp_sandybridge/Makefile.inc
index 080a7f4..ca6f345 100644
--- a/src/northbridge/intel/fsp_sandybridge/Makefile.inc
+++ b/src/northbridge/intel/fsp_sandybridge/Makefile.inc
@@ -20,11 +20,13 @@
subdirs-y += fsp
ramstage-y += northbridge.c
+ramstage-y += ram_calc.c
ramstage-y += gma.c
ramstage-y += acpi.c
romstage-y += raminit.c
+romstage-y += ram_calc.c
romstage-y += early_init.c
romstage-y += report_platform.c
romstage-y += ../../../arch/x86/lib/walkcbfs.S
diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c
index a95d736..b39f4c9 100644
--- a/src/northbridge/intel/fsp_sandybridge/northbridge.c
+++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c
@@ -245,16 +245,6 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(dev->link_list);
}
-unsigned long get_top_of_ram(void)
-{
- struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
-
- /* Base of TSEG is top of usable DRAM */
- u32 tom = pci_read_config32(dev, TSEG) & ~(1UL << 0);
- tom -= 0x200000; /* 2MB for FSP HOB */
- return (unsigned long) tom;
-}
-
/* TODO We could determine how many PCIe busses we need in
* the bar. For now that number is hardcoded to a max of 64.
* See e7525/northbridge.c for an example.
diff --git a/src/northbridge/intel/fsp_sandybridge/ram_calc.c b/src/northbridge/intel/fsp_sandybridge/ram_calc.c
new file mode 100644
index 0000000..43a1105
--- /dev/null
+++ b/src/northbridge/intel/fsp_sandybridge/ram_calc.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define __SIMPLE_DEVICE__
+
+#include <arch/io.h>
+#include <cbmem.h>
+#include <fsp_util.h>
+#include "northbridge.h"
+
+static uintptr_t smm_region_start(void)
+{
+ /* Base of TSEG is top of usable DRAM */
+ uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG) & ~(1UL << 0);
+ return tom;
+}
+
+void *cbmem_top(void)
+{
+ return (void *) (smm_region_start() - FSP_RESERVE_MEMORY_SIZE);
+}
diff --git a/src/northbridge/intel/fsp_sandybridge/raminit.c b/src/northbridge/intel/fsp_sandybridge/raminit.c
index 19b48ca..8689274 100644
--- a/src/northbridge/intel/fsp_sandybridge/raminit.c
+++ b/src/northbridge/intel/fsp_sandybridge/raminit.c
@@ -74,11 +74,3 @@ void report_memory_config(void)
((ch_conf >> 16) & 1) ? ", selected" : "");
}
}
-
-unsigned long get_top_of_ram(void)
-{
- /* Base of TSEG is top of usable DRAM */
- u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG) & ~(1UL << 0);
- tom -= 0x200000; /* 2MB for FSP HOB */
- return (unsigned long) tom;
-}
diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c
index c8c15d3..d9d3357 100644
--- a/src/northbridge/intel/gm45/ram_calc.c
+++ b/src/northbridge/intel/gm45/ram_calc.c
@@ -86,7 +86,7 @@ u32 decode_igd_gtt_size(const u32 gsm)
}
}
-unsigned long get_top_of_ram(void)
+static uintptr_t smm_region_start(void)
{
const pci_devfn_t dev = PCI_DEV(0, 0, 0);
@@ -105,3 +105,8 @@ unsigned long get_top_of_ram(void)
}
return tor;
}
+
+void *cbmem_top(void)
+{
+ return (void *) smm_region_start();
+}
diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c
index 99e7d67..01ad50d 100644
--- a/src/northbridge/intel/haswell/ram_calc.c
+++ b/src/northbridge/intel/haswell/ram_calc.c
@@ -24,12 +24,17 @@
#include <cbmem.h>
#include "haswell.h"
-unsigned long get_top_of_ram(void)
+static uintptr_t smm_region_start(void)
{
/*
* Base of TSEG is top of usable DRAM below 4GiB. The register has
* 1 MiB alignement.
*/
- u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
- return (unsigned long) tom & ~((1 << 20) - 1);
+ uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
+ return tom & ~((1 << 20) - 1);
+}
+
+void *cbmem_top(void)
+{
+ return (void *)smm_region_start();
}
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c
index d09b2e1..4b7d895 100644
--- a/src/northbridge/intel/i945/ram_calc.c
+++ b/src/northbridge/intel/i945/ram_calc.c
@@ -24,9 +24,9 @@
#include <cbmem.h>
#include "i945.h"
-unsigned long get_top_of_ram(void)
+static uintptr_t smm_region_start(void)
{
- u32 tom;
+ uintptr_t tom;
if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) {
/* IGD enabled, get top of Memory from BSM register */
@@ -53,5 +53,10 @@ unsigned long get_top_of_ram(void)
/* TSEG either disabled or invalid */
break;
}
- return (unsigned long) tom;
+ return tom;
+}
+
+void *cbmem_top(void)
+{
+ return (void *) smm_region_start();
}
diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c
index db57a3d..d36684e 100644
--- a/src/northbridge/intel/nehalem/ram_calc.c
+++ b/src/northbridge/intel/nehalem/ram_calc.c
@@ -23,9 +23,14 @@
#include <cbmem.h>
#include "nehalem.h"
-unsigned long get_top_of_ram(void)
+static uintptr_t smm_region_start(void)
{
/* Base of TSEG is top of usable DRAM */
- u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
- return (unsigned long) tom;
+ uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
+ return tom;
+}
+
+void *cbmem_top(void)
+{
+ return (void *) smm_region_start();
}
diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c
index 3693a07..e147909 100644
--- a/src/northbridge/intel/sandybridge/ram_calc.c
+++ b/src/northbridge/intel/sandybridge/ram_calc.c
@@ -23,9 +23,14 @@
#include <cbmem.h>
#include "sandybridge.h"
-unsigned long get_top_of_ram(void)
+static uintptr_t smm_region_start(void)
{
/* Base of TSEG is top of usable DRAM */
- u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
- return (unsigned long) tom;
+ uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
+ return tom;
+}
+
+void *cbmem_top(void)
+{
+ return (void *) smm_region_start();
}
diff --git a/src/soc/intel/baytrail/baytrail/smm.h b/src/soc/intel/baytrail/baytrail/smm.h
index 5ead89f..0d920fb 100644
--- a/src/soc/intel/baytrail/baytrail/smm.h
+++ b/src/soc/intel/baytrail/baytrail/smm.h
@@ -31,7 +31,7 @@ static inline int smm_region_size(void)
return CONFIG_SMM_TSEG_SIZE;
}
-void *smm_region_start(void);
+uintptr_t smm_region_start(void);
#if !defined(__PRE_RAM__) && !defined(__SMM___)
#include <stdint.h>
diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c
index f383d82..f2e14b3 100644
--- a/src/soc/intel/baytrail/memmap.c
+++ b/src/soc/intel/baytrail/memmap.c
@@ -22,12 +22,12 @@
#include <baytrail/iosf.h>
#include <baytrail/smm.h>
-void *smm_region_start(void)
+uintptr_t smm_region_start(void)
{
- return (void *)(iosf_bunit_read(BUNIT_SMRRL) << 20);
+ return (iosf_bunit_read(BUNIT_SMRRL) << 20);
}
-unsigned long get_top_of_ram(void)
+void *cbmem_top(void)
{
- return (unsigned long)smm_region_start();
+ return (void *) smm_region_start();
}
diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c
index 046cc1d..28f4062 100644
--- a/src/soc/intel/broadwell/memmap.c
+++ b/src/soc/intel/broadwell/memmap.c
@@ -23,19 +23,24 @@
#include <broadwell/pci_devs.h>
#include <broadwell/systemagent.h>
-unsigned long get_top_of_ram(void)
+static uintptr_t dpr_region_start(void)
{
/*
* Base of DPR is top of usable DRAM below 4GiB. The register has
* 1 MiB alignment and reports the TOP of the range, the base
* must be calculated from the size in MiB in bits 11:4.
*/
- u32 dpr = pci_read_config32(SA_DEV_ROOT, DPR);
- u32 tom = dpr & ~((1 << 20) - 1);
+ uintptr_t dpr = pci_read_config32(SA_DEV_ROOT, DPR);
+ uintptr_t tom = dpr & ~((1 << 20) - 1);
/* Subtract DMA Protected Range size if enabled */
if (dpr & DPR_EPM)
tom -= (dpr & DPR_SIZE_MASK) << 16;
- return (unsigned long)tom;
+ return tom;
+}
+
+void *cbmem_top(void)
+{
+ return (void *) dpr_region_start();
}
diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc
index fcbe6e7..3896e85 100644
--- a/src/soc/intel/fsp_baytrail/Makefile.inc
+++ b/src/soc/intel/fsp_baytrail/Makefile.inc
@@ -44,8 +44,6 @@ ramstage-y += ramstage.c
ramstage-y += gpio.c
romstage-y += gpio.c
ramstage-y += pmutil.c
-romstage-y += raminit.c
-ramstage-y += raminit.c
ramstage-y += southcluster.c
romstage-y += reset.c
ramstage-y += reset.c
diff --git a/src/soc/intel/fsp_baytrail/baytrail/smm.h b/src/soc/intel/fsp_baytrail/baytrail/smm.h
index 0208c9f..136c2ca 100644
--- a/src/soc/intel/fsp_baytrail/baytrail/smm.h
+++ b/src/soc/intel/fsp_baytrail/baytrail/smm.h
@@ -36,7 +36,7 @@ static inline int smm_region_size(void)
return CONFIG_SMM_TSEG_SIZE;
}
-void *smm_region_start(void);
+uintptr_t smm_region_start(void);
#if !defined(__PRE_RAM__) && !defined(__SMM___)
#include <stdint.h>
diff --git a/src/soc/intel/fsp_baytrail/memmap.c b/src/soc/intel/fsp_baytrail/memmap.c
index 83858b8..615916b 100644
--- a/src/soc/intel/fsp_baytrail/memmap.c
+++ b/src/soc/intel/fsp_baytrail/memmap.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -21,8 +22,25 @@
#include <cbmem.h>
#include <baytrail/iosf.h>
#include <baytrail/smm.h>
+#include <drivers/intel/fsp/fsp_util.h>
-void *smm_region_start(void)
+uintptr_t smm_region_start(void)
{
- return (void *)(iosf_bunit_read(BUNIT_SMRRL) << 20);
+ return (iosf_bunit_read(BUNIT_SMRRL) << 20);
+}
+
+/*
+ * Calculate the top of usable (low) DRAM.
+ * The FSP's reserved memory sits just below the SMM region,
+ * allowing calculation of the top of usable memory.
+ *
+ * The entire memory map is shown in northcluster.c
+ */
+
+void *cbmem_top(void)
+{
+ uintptr_t tom = smm_region_start();
+ if (!tom)
+ tom = iosf_bunit_read(BUNIT_BMBOUND);
+ return (void *) tom - FSP_RESERVE_MEMORY_SIZE;
}
diff --git a/src/soc/intel/fsp_baytrail/raminit.c b/src/soc/intel/fsp_baytrail/raminit.c
deleted file mode 100644
index 55692d2..0000000
--- a/src/soc/intel/fsp_baytrail/raminit.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <cbmem.h>
-#include <device/device.h>
-#include <baytrail/baytrail.h>
-#include <baytrail/iosf.h>
-#include <cpu/x86/msr.h>
-#include <drivers/intel/fsp/fsp_util.h>
-
-unsigned long get_top_of_ram(void)
-{
- /*
- * Calculate the top of usable (low) DRAM.
- * The FSP's reserved memory sits just below the SMM region,
- * allowing calculation of the top of usable memory.
- *
- * The entire memory map is shown in northcluster.c
- */
- u32 tom = iosf_bunit_read(BUNIT_BMBOUND);
- u32 bsmmrrl = iosf_bunit_read(BUNIT_SMRRL) << 20;
- if (bsmmrrl) {
- tom = bsmmrrl;
- }
- tom -= FSP_RESERVE_MEMORY_SIZE;
-
- return (unsigned long) tom;
-}
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