[coreboot-gerrit] Patch set updated for coreboot: 9e12143 device/device.c: Correct PCI register space location

[Timothy Pearson (tpearson@raptorengineeringinc.com)]

Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8261

-gerrit

commit 9e12143ae5486700037b3b77bb05e3dccb64128f
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Fri Jan 23 20:20:56 2015 -0600

    device/device.c: Correct PCI register space location
    
    Fix the incorrect PCI register space location causing corruption
    with more than ~3.5GB physical RAM on AMD Family 10h systems.
    
    Change-Id: I66d1bfa1e977a6b492c1909079087a801c7e6a3a
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
 src/device/device.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/src/device/device.c b/src/device/device.c
index 00e323a..94390b7 100644
--- a/src/device/device.c
+++ b/src/device/device.c
@@ -13,6 +13,7 @@
  * (Written by Yinghai Lu <yhlu at tyan.com> for Tyan)
  * Copyright (C) 2005-2006 Stefan Reinauer <stepan at openbios.org>
  * Copyright (C) 2009 Myles Watson <mylesgw at gmail.com>
+ * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>, Raptor Engineering
  */
 
 /*
@@ -685,6 +686,25 @@ static void constrain_resources(struct device *dev, struct constraints* limits)
 	}
 }
 
+/*
+ * In this function there is a provision to shrink the potential PCI address
+ * space to the resource specified value.
+ *
+ * Without this the PCI address space attempts to reserve roughly all 32-bit
+ * addressable RAM, leading to allocation below the AMD fixed resource window
+ * instead of above it.  When allocated below the fixed resource window it
+ * is not protected by the e820 map and the PCI configuration is overwritten,
+ * causing all PCI devices to become unusable!
+ *
+ * This bug is only exposed when the top of system RAM touches the bottom of
+ * the fixed resource window.  If less than ~3.5GB of memory is installed there
+ * is a gap between system RAM and the fixed resource window which protects
+ * the incorrectly allocated PCI configuration registers and hides this bug.
+ *
+ * On non-AMD systems this may not matter as much, but the code below is generic
+ * and should not harm other systems.
+ */
+
 static void avoid_fixed_resources(struct device *dev)
 {
 	struct constraints limits;
@@ -712,6 +732,12 @@ static void avoid_fixed_resources(struct device *dev)
 		if ((res->flags & MEM_MASK) == MEM_TYPE &&
 		    (res->limit < limits.mem.limit))
 			limits.mem.limit = res->limit;
+		/* Shrink PCI address space */
+		if ((res->flags & MEM_MASK) == MEM_TYPE &&
+		    (res->size < (limits.mem.limit - limits.mem.base + 1))) {
+			limits.mem.base = (limits.mem.limit - res->size + 1);
+			limits.mem.size = res->size;
+		}
 		if ((res->flags & IO_MASK) == IO_TYPE &&
 		    (res->limit < limits.io.limit))
 			limits.io.limit = res->limit;