[coreboot-gerrit] Patch set updated for coreboot: 885c4d2 Fix FTBFS with AMD Family 10h systems Add ability to bypass register 0x78 initialization (needed for certain systems) Add ability to override CK804 base unit ID (needed at power-up for certain sytems)
Timothy Pearson (tpearson@raptorengineeringinc.com)
gerrit at coreboot.org
Sat Jan 24 09:41:12 CET 2015
Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8269
-gerrit
commit 885c4d2e85956279b85a447cc1950a9da867d692
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date: Fri Jan 23 20:29:46 2015 -0600
Fix FTBFS with AMD Family 10h systems
Add ability to bypass register 0x78 initialization (needed for certain systems)
Add ability to override CK804 base unit ID (needed at power-up for certain sytems)
Change-Id: I85d005edba44c503c49917d4b928e5c9c5900059
Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
src/southbridge/nvidia/ck804/bootblock.c | 4 ++++
src/southbridge/nvidia/ck804/early_setup.c | 4 ++++
src/southbridge/nvidia/ck804/early_setup_car.c | 14 ++++++++++++++
src/southbridge/nvidia/ck804/enable_usbdebug.c | 3 +++
4 files changed, 25 insertions(+)
diff --git a/src/southbridge/nvidia/ck804/bootblock.c b/src/southbridge/nvidia/ck804/bootblock.c
index 6e68404..45db5cb 100644
--- a/src/southbridge/nvidia/ck804/bootblock.c
+++ b/src/southbridge/nvidia/ck804/bootblock.c
@@ -1,6 +1,8 @@
/*
* This file is part of the coreboot project.
*
+ * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>, Raptor Engineering
+ *
* Copyright (C) 2004 Tyan Computer
* Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
*
@@ -20,11 +22,13 @@
#include <arch/io.h>
+#ifndef CK804_DEVN_BASE
#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
#else
#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
#endif
+#endif
static void ck804_enable_rom(void)
{
diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c
index 84b6bfb..792644e 100644
--- a/src/southbridge/nvidia/ck804/early_setup.c
+++ b/src/southbridge/nvidia/ck804/early_setup.c
@@ -1,6 +1,8 @@
/*
* This file is part of the coreboot project.
*
+ * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>, Raptor Engineering
+ *
* Copyright (C) 2004 Tyan Computer
* Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
*
@@ -76,11 +78,13 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control,
#define CK804_CHIP_REV 3
+#ifndef CK804_DEVN_BASE
#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
#else
#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
#endif
+#endif
#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
#define CK804B_DEVN_BASE 1
diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c
index 9ba98c9..3aa11ab 100644
--- a/src/southbridge/nvidia/ck804/early_setup_car.c
+++ b/src/southbridge/nvidia/ck804/early_setup_car.c
@@ -1,6 +1,8 @@
/*
* This file is part of the coreboot project.
*
+ * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>, Raptor Engineering
+ *
* Copyright (C) 2004 Tyan Computer
* Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
*
@@ -18,6 +20,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#if CONFIG_NORTHBRIDGE_AMD_AMDK8
static int set_ht_link_ck804(u8 ht_c_num)
{
unsigned vendorid = 0x10de;
@@ -46,6 +49,7 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control,
val |= 1;
outl(val, control);
}
+#endif
#define ANACTRL_IO_BASE 0x3000
#define ANACTRL_REG_POS 0x68
@@ -66,11 +70,13 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control,
#define CK804_CHIP_REV 3
+#ifndef CK804_DEVN_BASE
#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
#else
#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
#endif
+#endif
#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
#define CK804B_DEVN_BASE 1
@@ -147,7 +153,9 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn,
CK804_MB_SETUP
#endif
+#ifndef CK804_SKIP_PCI_REG_78_INIT
RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xc0ffffff, 0x19000000,
+#endif
RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe0), 0xfffffeff, 0x00000100,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
@@ -297,6 +305,7 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn,
PCI_DEV(busn[j], CK804B_DEVN_BASE, 0), io_base[j]);
}
+#if CONFIG_NORTHBRIDGE_AMD_AMDK8
for (j = 0; j < ck804_num; j++) {
/* PCI-E (XSPLL) SS table 0x40, x044, 0x48 */
/* SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8 */
@@ -314,6 +323,7 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn,
io_base[j] + ANACTRL_IO_BASE + 0xc8,
cpu_ss_tbl, 64);
}
+#endif
}
static int ck804_early_setup_x(void)
@@ -340,7 +350,11 @@ static int ck804_early_setup_x(void)
ck804_early_setup(ck804_num, busn, io_base);
ck804_early_clear_port(ck804_num, busn, io_base);
+#if CONFIG_NORTHBRIDGE_AMD_AMDK8
return set_ht_link_ck804(4);
+#else
+ return 0;
+#endif
}
void hard_reset(void)
diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c
index 97e8ecb..5bb16a3 100644
--- a/src/southbridge/nvidia/ck804/enable_usbdebug.c
+++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c
@@ -5,6 +5,7 @@
* Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
* Copyright (C) 2006,2007 AMD
* Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>, Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -30,11 +31,13 @@
#include <device/pci_def.h>
#include "ck804.h"
+#ifndef CK804_DEVN_BASE
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
#else
#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
#endif
+#endif
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
{
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