[coreboot-gerrit] New patch to review for coreboot: 5ca5f55 Fix incorrect PCI register space location causing corruption with more than ~3.5GB physical RAM on AMD Family 10h systems Tested with 8GB physical RAM

[Timothy Pearson (tpearson@raptorengineeringinc.com)]

Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8261

-gerrit

commit 5ca5f55b182fdbb08bda646033c2fb80ed67b69d
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Fri Jan 23 20:20:56 2015 -0600

    Fix incorrect PCI register space location causing corruption with more than ~3.5GB physical RAM on AMD Family 10h systems
    Tested with 8GB physical RAM
    
    Change-Id: I66d1bfa1e977a6b492c1909079087a801c7e6a3a
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
 src/device/device.c | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/src/device/device.c b/src/device/device.c
index 00e323a..a251568 100644
--- a/src/device/device.c
+++ b/src/device/device.c
@@ -13,6 +13,7 @@
  * (Written by Yinghai Lu <yhlu at tyan.com> for Tyan)
  * Copyright (C) 2005-2006 Stefan Reinauer <stepan at openbios.org>
  * Copyright (C) 2009 Myles Watson <mylesgw at gmail.com>
+ * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>, Raptor Engineering
  */
 
 /*
@@ -669,11 +670,14 @@ static void constrain_resources(struct device *dev, struct constraints* limits)
 		 * signed so that "negative" amounts of space are handled
 		 * correctly.
 		 */
+
 		if ((signed long long)(lim->limit - (res->base + res->size -1))
-		    > (signed long long)(res->base - lim->base))
+		    > (signed long long)(res->base - lim->base)) {
 			lim->base = res->base + res->size;
-		else
+		}
+		else {
 			lim->limit = res->base -1;
+		}
 	}
 
 	/* Descend into every enabled child and look for fixed resources. */
@@ -712,6 +716,20 @@ static void avoid_fixed_resources(struct device *dev)
 		if ((res->flags & MEM_MASK) == MEM_TYPE &&
 		    (res->limit < limits.mem.limit))
 			limits.mem.limit = res->limit;
+		// Shrink possible PCI address space to the resource specified value
+		// Without this the PCI address space attempts to reserve roughly all 32-bit addressable RAM,
+		// leading to allocation below the AMD fixed resource window instead of above it.  When allocated
+		// below the fixed resource window it is not protected by the e820 map and the PCI configuration
+		// is overwritten, causing all PCI devices to become unusable!
+		// This bug is only exposed when the top of system RAM touches the bottom of the fixed resource window.
+		// If less than ~3.5GB of memory is installed there is a gap between system RAM and the fixed resource window
+		// which protects the incorrectly allocated PCI configuration registers and hides this bug.
+		// On non-AMD systems this may not matter as much, but the code below is generic and should not harm other systems.
+		if ((res->flags & MEM_MASK) == MEM_TYPE &&
+		    (res->size < (limits.mem.limit - limits.mem.base + 1))) {
+			limits.mem.base = (limits.mem.limit - res->size + 1);
+			limits.mem.size = res->size;
+		}
 		if ((res->flags & IO_MASK) == IO_TYPE &&
 		    (res->limit < limits.io.limit))
 			limits.io.limit = res->limit;