[coreboot-gerrit] New patch to review for coreboot: a5b979b asrock/e350m1: Fix PCIe slot for x4 cards

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8229

-gerrit

commit a5b979b61699b1377fedd953e0941cc4190821a5
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Thu Jan 15 17:42:53 2015 +0200

    asrock/e350m1: Fix PCIe slot for x4 cards
    
    Configuration for GNB GPP was incorrect, only PCIe x1 cards worked.
    
    Change-Id: I369bf6382080e6034ff138ac664c76b03280ca69
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/mainboard/asrock/e350m1/PlatformGnbPcie.c | 22 +---------------------
 1 file changed, 1 insertion(+), 21 deletions(-)

diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c
index 76e5ade..a704c4b 100644
--- a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c
+++ b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c
@@ -58,29 +58,9 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
         // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
         {
           0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
-          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
+          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),
           PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0)
         },
-	#if 1
-        // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
-        {
-          0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
-          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
-          PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 0)
-        },
-        // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
-        {
-          0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
-          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
-          PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 0)
-        },
-        // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
-        {
-          0,
-          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
-          PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0)
-        },
-	#endif
         // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
         {
           DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array