[coreboot-gerrit] Patch set updated for coreboot: fedb3b0 x86: Change MMIO addr in readN(addr)/writeN(addr, val) to a pointer
Kevin Paul Herbert (kph@meraki.net)
gerrit at coreboot.org
Wed Jan 14 05:30:46 CET 2015
Kevin Paul Herbert (kph at meraki.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7784
-gerrit
commit fedb3b08f0d5602fca3c0d24cd34676c0bb6631d
Author: Kevin Paul Herbert <kph at meraki.net>
Date: Wed Dec 24 18:43:20 2014 -0800
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to a pointer
On x86, change the type of the address parameter in read8()/read16/read32()/
write8()/write16()/write32() to be a pointer, instead of unsigned long.
Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph at meraki.net>
---
src/arch/x86/boot/mpspec.c | 2 +-
src/arch/x86/include/arch/ebda.h | 6 +-
src/arch/x86/include/arch/io.h | 12 +-
src/arch/x86/include/arch/ioapic.h | 11 +-
src/arch/x86/include/arch/pci_mmio_cfg.h | 24 +-
src/arch/x86/include/arch/smp/mpspec.h | 4 +-
src/arch/x86/lib/ebda.c | 2 +-
src/arch/x86/lib/ioapic.c | 18 +-
src/arch/x86/lib/pci_ops_mmconf.c | 18 +-
src/device/azalia_device.c | 21 +-
src/device/oprom/realmode/x86.c | 2 +-
src/drivers/ati/ragexl/atyfb.h | 2 +-
src/drivers/ati/ragexl/fb.h | 2 +-
src/drivers/ati/ragexl/xlinit.c | 6 +-
src/drivers/generic/ioapic/chip.h | 2 +-
src/drivers/generic/ioapic/ioapic.c | 6 +-
src/drivers/intel/gma/edid.c | 4 +-
src/drivers/intel/gma/edid.h | 2 +-
src/drivers/usb/ehci_debug.c | 106 ++---
src/drivers/usb/pci_ehci.c | 6 +-
src/include/device/pci_ehci.h | 2 +-
src/include/device/resource.h | 6 +
src/lib/reg_script.c | 12 +-
src/mainboard/advansus/a785e-i/mptable.c | 2 +-
src/mainboard/amd/bimini_fam10/mptable.c | 2 +-
src/mainboard/amd/dbm690t/mptable.c | 3 +-
src/mainboard/amd/dinar/mptable.c | 6 +-
src/mainboard/amd/inagua/mptable.c | 6 +-
src/mainboard/amd/mahogany/mptable.c | 3 +-
src/mainboard/amd/mahogany_fam10/mptable.c | 3 +-
src/mainboard/amd/olivehill/mptable.c | 8 +-
src/mainboard/amd/olivehillplus/mptable.c | 8 +-
src/mainboard/amd/parmer/mptable.c | 6 +-
src/mainboard/amd/persimmon/mptable.c | 6 +-
src/mainboard/amd/pistachio/mptable.c | 3 +-
src/mainboard/amd/serengeti_cheetah/mptable.c | 14 +-
.../amd/serengeti_cheetah_fam10/mptable.c | 14 +-
src/mainboard/amd/south_station/mptable.c | 6 +-
src/mainboard/amd/thatcher/mptable.c | 6 +-
src/mainboard/amd/tilapia_fam10/mptable.c | 3 +-
src/mainboard/amd/torpedo/mptable.c | 6 +-
src/mainboard/amd/union_station/mptable.c | 6 +-
src/mainboard/apple/macbook21/mptable.c | 2 +-
src/mainboard/arima/hdama/mptable.c | 8 +-
src/mainboard/asrock/939a785gmh/mptable.c | 3 +-
src/mainboard/asrock/e350m1/mptable.c | 6 +-
src/mainboard/asrock/imb-a180/mptable.c | 8 +-
src/mainboard/asus/a8n_e/mptable.c | 2 +-
src/mainboard/asus/a8v-e_deluxe/mptable.c | 4 +-
src/mainboard/asus/a8v-e_se/mptable.c | 4 +-
src/mainboard/asus/dsbf/devicetree.cb | 4 +-
src/mainboard/asus/dsbf/romstage.c | 4 +-
src/mainboard/asus/f2a85-m/mptable.c | 6 +-
src/mainboard/asus/k8v-x/mptable.c | 4 +-
src/mainboard/asus/m2n-e/mptable.c | 3 +-
src/mainboard/asus/m2v/mptable.c | 4 +-
src/mainboard/asus/m4a78-em/mptable.c | 3 +-
src/mainboard/asus/m4a785-m/mptable.c | 3 +-
src/mainboard/asus/m5a88-v/mptable.c | 2 +-
src/mainboard/asus/p2b-d/mptable.c | 2 +-
src/mainboard/asus/p2b-ds/mptable.c | 2 +-
src/mainboard/avalue/eax-785e/mptable.c | 2 +-
src/mainboard/broadcom/blast/mptable.c | 4 +-
src/mainboard/getac/p470/mptable.c | 2 +-
src/mainboard/gigabyte/ga_2761gxdk/mptable.c | 3 +-
src/mainboard/gigabyte/m57sli/mptable.c | 3 +-
src/mainboard/gigabyte/ma785gm/mptable.c | 3 +-
src/mainboard/gigabyte/ma785gmt/mptable.c | 3 +-
src/mainboard/gigabyte/ma78gm/mptable.c | 3 +-
src/mainboard/gizmosphere/gizmo/mptable.c | 6 +-
src/mainboard/gizmosphere/gizmo2/mptable.c | 6 +-
src/mainboard/google/bolt/romstage.c | 6 +-
src/mainboard/google/butterfly/romstage.c | 6 +-
src/mainboard/google/falco/romstage.c | 6 +-
src/mainboard/google/link/romstage.c | 6 +-
src/mainboard/google/panther/romstage.c | 6 +-
src/mainboard/google/parrot/romstage.c | 6 +-
src/mainboard/google/peppy/romstage.c | 6 +-
src/mainboard/google/slippy/romstage.c | 6 +-
src/mainboard/google/stout/romstage.c | 6 +-
src/mainboard/hp/abm/mptable.c | 8 +-
src/mainboard/hp/dl145_g1/mptable.c | 8 +-
src/mainboard/hp/dl145_g3/mptable.c | 3 +-
src/mainboard/hp/dl165_g6_fam10/mptable.c | 3 +-
src/mainboard/hp/pavilion_m6_1035dx/mptable.c | 6 +-
src/mainboard/ibase/mb899/mptable.c | 2 +-
src/mainboard/ibm/e325/mptable.c | 8 +-
src/mainboard/ibm/e326/mptable.c | 8 +-
src/mainboard/iei/kino-780am2-fam10/mptable.c | 3 +-
src/mainboard/intel/baskingridge/romstage.c | 6 +-
src/mainboard/intel/d945gclf/mptable.c | 2 +-
src/mainboard/intel/eagleheights/mptable.c | 6 +-
src/mainboard/intel/eagleheights/romstage.c | 2 +-
src/mainboard/intel/emeraldlake2/romstage.c | 6 +-
src/mainboard/intel/mohonpeak/romstage.c | 2 +-
src/mainboard/intel/mtarvon/mptable.c | 2 +-
src/mainboard/intel/truxton/mptable.c | 2 +-
src/mainboard/iwave/iWRainbowG6/mptable.c | 2 +-
src/mainboard/iwill/dk8_htx/mptable.c | 14 +-
src/mainboard/iwill/dk8s2/mptable.c | 8 +-
src/mainboard/iwill/dk8x/mptable.c | 8 +-
src/mainboard/jetway/nf81-t56n-lf/mptable.c | 6 +-
src/mainboard/jetway/pa78vm5/mptable.c | 3 +-
src/mainboard/kontron/986lcd-m/mptable.c | 2 +-
src/mainboard/kontron/kt690/mptable.c | 3 +-
src/mainboard/kontron/ktqm77/romstage.c | 6 +-
src/mainboard/lenovo/g505s/mptable.c | 6 +-
src/mainboard/lenovo/t60/mptable.c | 2 +-
src/mainboard/lenovo/x200/devicetree.cb | 2 +-
src/mainboard/lenovo/x60/mptable.c | 2 +-
src/mainboard/lippert/frontrunner-af/mptable.c | 6 +-
src/mainboard/lippert/toucan-af/mptable.c | 6 +-
src/mainboard/msi/ms7135/mptable.c | 2 +-
src/mainboard/msi/ms7260/mptable.c | 3 +-
src/mainboard/msi/ms9185/mptable.c | 3 +-
src/mainboard/msi/ms9282/mptable.c | 3 +-
src/mainboard/msi/ms9652_fam10/mptable.c | 3 +-
src/mainboard/newisys/khepri/mptable.c | 8 +-
src/mainboard/nvidia/l1_2pvv/mptable.c | 6 +-
src/mainboard/roda/rk886ex/mptable.c | 2 +-
src/mainboard/roda/rk9/devicetree.cb | 2 +-
src/mainboard/samsung/lumpy/devicetree.cb | 2 +-
src/mainboard/samsung/lumpy/romstage.c | 6 +-
src/mainboard/samsung/stumpy/romstage.c | 6 +-
src/mainboard/siemens/sitemp_g1p1/mptable.c | 3 +-
src/mainboard/sunw/ultra40/mptable.c | 12 +-
src/mainboard/supermicro/h8dme/mptable.c | 3 +-
src/mainboard/supermicro/h8dmr/mptable.c | 3 +-
src/mainboard/supermicro/h8dmr_fam10/mptable.c | 3 +-
src/mainboard/supermicro/h8qgi/mptable.c | 10 +-
src/mainboard/supermicro/h8qme_fam10/mptable.c | 3 +-
src/mainboard/supermicro/h8scm/mptable.c | 12 +-
src/mainboard/supermicro/h8scm_fam10/mptable.c | 14 +-
src/mainboard/supermicro/x7db8/romstage.c | 4 +-
src/mainboard/technexion/tim5690/mptable.c | 3 +-
src/mainboard/technexion/tim8690/mptable.c | 3 +-
src/mainboard/thomson/ip1000/mainboard.c | 6 +-
src/mainboard/tyan/s2735/mptable.c | 8 +-
src/mainboard/tyan/s2850/mptable.c | 2 +-
src/mainboard/tyan/s2875/mptable.c | 2 +-
src/mainboard/tyan/s2880/mptable.c | 8 +-
src/mainboard/tyan/s2881/mptable.c | 8 +-
src/mainboard/tyan/s2882/mptable.c | 8 +-
src/mainboard/tyan/s2885/mptable.c | 8 +-
src/mainboard/tyan/s2891/mptable.c | 9 +-
src/mainboard/tyan/s2892/mptable.c | 9 +-
src/mainboard/tyan/s2895/mptable.c | 12 +-
src/mainboard/tyan/s2912/mptable.c | 3 +-
src/mainboard/tyan/s2912_fam10/mptable.c | 3 +-
src/mainboard/tyan/s4880/mptable.c | 8 +-
src/mainboard/tyan/s4882/mptable.c | 8 +-
src/mainboard/tyan/s8226/mptable.c | 10 +-
src/mainboard/via/epia-m850/devicetree.cb | 4 +-
src/mainboard/via/pc2500e/mptable.c | 2 +-
src/mainboard/via/vt8454c/mptable.c | 2 +-
src/mainboard/winent/mb6047/mptable.c | 3 +-
src/northbridge/amd/cimx/rd890/late.c | 4 +-
src/northbridge/intel/e7501/raminit.c | 11 +-
src/northbridge/intel/e7505/raminit.c | 10 +-
src/northbridge/intel/fsp_sandybridge/acpi.c | 2 +-
src/northbridge/intel/fsp_sandybridge/early_init.c | 8 +-
.../intel/fsp_sandybridge/northbridge.h | 7 +-
src/northbridge/intel/gm45/early_init.c | 4 +-
src/northbridge/intel/gm45/gm45.h | 7 +-
src/northbridge/intel/gm45/gma.c | 10 +-
src/northbridge/intel/gm45/pcie.c | 6 +-
src/northbridge/intel/gm45/raminit.c | 12 +-
.../intel/gm45/raminit_read_write_training.c | 12 +-
.../gm45/raminit_receive_enable_calibration.c | 2 +-
src/northbridge/intel/haswell/acpi.c | 2 +-
src/northbridge/intel/haswell/early_init.c | 4 +-
src/northbridge/intel/haswell/gma.c | 4 +-
src/northbridge/intel/haswell/haswell.h | 4 +
src/northbridge/intel/haswell/minihd.c | 7 +-
src/northbridge/intel/i3100/i3100.h | 2 +-
src/northbridge/intel/i3100/raminit.c | 9 +-
src/northbridge/intel/i3100/raminit_ep80579.c | 4 +-
src/northbridge/intel/i440bx/raminit.c | 5 +-
src/northbridge/intel/i5000/raminit.h | 2 +-
src/northbridge/intel/i82810/raminit.c | 10 +-
src/northbridge/intel/i82830/raminit.c | 8 +-
src/northbridge/intel/i82830/smihandler.c | 2 +-
src/northbridge/intel/i855/raminit.c | 2 +-
src/northbridge/intel/i945/early_init.c | 12 +-
src/northbridge/intel/i945/i945.h | 5 +
src/northbridge/intel/i945/raminit.c | 2 +-
src/northbridge/intel/i945/rcven.c | 4 +-
src/northbridge/intel/nehalem/acpi.c | 2 +-
src/northbridge/intel/nehalem/early_init.c | 12 +-
src/northbridge/intel/nehalem/gma.c | 14 +-
src/northbridge/intel/nehalem/nehalem.h | 9 +-
src/northbridge/intel/nehalem/raminit.c | 158 ++++----
src/northbridge/intel/sandybridge/acpi.c | 2 +-
src/northbridge/intel/sandybridge/early_init.c | 10 +-
src/northbridge/intel/sandybridge/gma.c | 9 +-
src/northbridge/intel/sandybridge/gma.h | 2 +-
.../intel/sandybridge/gma_ivybridge_lvds.c | 8 +-
.../intel/sandybridge/gma_sandybridge_lvds.c | 6 +-
src/northbridge/intel/sandybridge/raminit_native.c | 128 +++---
src/northbridge/intel/sandybridge/sandybridge.h | 7 +-
src/northbridge/intel/sch/early_init.c | 3 +-
src/northbridge/intel/sch/sch.h | 2 +-
src/northbridge/via/cn700/raminit.c | 8 +-
src/northbridge/via/cx700/lpc.c | 2 +-
src/northbridge/via/cx700/raminit.c | 152 +++----
src/northbridge/via/vx900/lpc.c | 6 +-
src/northbridge/via/vx900/traf_ctrl.c | 12 +-
src/soc/intel/baytrail/acpi.c | 2 +-
src/soc/intel/baytrail/baytrail/gpio.h | 22 +-
src/soc/intel/baytrail/gfx.c | 4 +-
src/soc/intel/baytrail/gpio.c | 16 +-
src/soc/intel/baytrail/hda.c | 6 +-
src/soc/intel/baytrail/iosf.c | 4 +-
src/soc/intel/baytrail/lpe.c | 12 +-
src/soc/intel/baytrail/pmutil.c | 8 +-
src/soc/intel/baytrail/romstage/romstage.c | 10 +-
src/soc/intel/baytrail/sata.c | 2 +-
src/soc/intel/baytrail/smm.c | 2 +-
src/soc/intel/baytrail/southcluster.c | 30 +-
src/soc/intel/baytrail/spi.c | 18 +-
src/soc/intel/broadwell/adsp.c | 7 +-
src/soc/intel/broadwell/hda.c | 10 +-
src/soc/intel/broadwell/igd.c | 4 +-
src/soc/intel/broadwell/lpc.c | 8 +-
src/soc/intel/broadwell/me.c | 6 +-
src/soc/intel/broadwell/minihd.c | 6 +-
src/soc/intel/broadwell/sata.c | 7 +-
src/soc/intel/broadwell/serialio.c | 36 +-
src/soc/intel/broadwell/spi.c | 24 +-
src/soc/intel/broadwell/xhci.c | 18 +-
src/soc/intel/common/hda_verb.c | 12 +-
src/soc/intel/common/hda_verb.h | 6 +-
src/soc/intel/fsp_baytrail/acpi.c | 2 +-
src/soc/intel/fsp_baytrail/baytrail/baytrail.h | 5 +-
src/soc/intel/fsp_baytrail/baytrail/gpio.h | 16 +-
src/soc/intel/fsp_baytrail/bootblock/bootblock.c | 2 +-
src/soc/intel/fsp_baytrail/gpio.c | 30 +-
src/soc/intel/fsp_baytrail/iosf.c | 4 +-
src/soc/intel/fsp_baytrail/pmutil.c | 8 +-
src/soc/intel/fsp_baytrail/romstage/romstage.c | 16 +-
src/soc/intel/fsp_baytrail/smm.c | 2 +-
src/soc/intel/fsp_baytrail/southcluster.c | 32 +-
src/soc/intel/fsp_baytrail/spi.c | 18 +-
src/southbridge/amd/agesa/hudson/enable_usbdebug.c | 4 +-
src/southbridge/amd/agesa/hudson/hudson.c | 8 +-
src/southbridge/amd/agesa/hudson/imc.c | 22 +-
src/southbridge/amd/agesa/hudson/sm.c | 2 +-
src/southbridge/amd/agesa/hudson/smi.h | 8 +-
src/southbridge/amd/agesa/hudson/spi.c | 4 +-
src/southbridge/amd/amd8111/lpc.c | 2 +-
src/southbridge/amd/amd8111/nic.c | 6 +-
src/southbridge/amd/cimx/sb700/late.c | 6 +-
src/southbridge/amd/cimx/sb800/late.c | 9 +-
src/southbridge/amd/cimx/sb800/spi.c | 20 +-
src/southbridge/amd/cimx/sb900/gpio_oem.h | 2 +-
src/southbridge/amd/cs5536/cs5536.c | 12 +-
src/southbridge/amd/pi/avalon/enable_usbdebug.c | 2 +-
src/southbridge/amd/pi/avalon/hudson.c | 8 +-
src/southbridge/amd/pi/avalon/sm.c | 2 +-
src/southbridge/amd/pi/avalon/smi.h | 8 +-
src/southbridge/amd/sb600/hda.c | 18 +-
src/southbridge/amd/sb600/sata.c | 6 +-
src/southbridge/amd/sb600/sm.c | 2 +-
src/southbridge/amd/sb600/usb.c | 6 +-
src/southbridge/amd/sb700/enable_usbdebug.c | 2 +-
src/southbridge/amd/sb700/hda.c | 18 +-
src/southbridge/amd/sb700/sata.c | 6 +-
src/southbridge/amd/sb700/sm.c | 4 +-
src/southbridge/amd/sb700/usb.c | 6 +-
src/southbridge/amd/sb800/enable_usbdebug.c | 2 +-
src/southbridge/amd/sb800/hda.c | 18 +-
src/southbridge/amd/sb800/sata.c | 6 +-
src/southbridge/amd/sb800/sm.c | 2 +-
src/southbridge/amd/sb800/usb.c | 6 +-
src/southbridge/amd/sr5650/ht.c | 2 +-
src/southbridge/broadcom/bcm5785/sata.c | 9 +-
src/southbridge/intel/bd82x6x/azalia.c | 21 +-
src/southbridge/intel/bd82x6x/bootblock.c | 2 +-
src/southbridge/intel/bd82x6x/early_pch_native.c | 446 ++++++++++-----------
src/southbridge/intel/bd82x6x/early_thermal.c | 39 +-
src/southbridge/intel/bd82x6x/early_usb_native.c | 16 +-
src/southbridge/intel/bd82x6x/lpc.c | 8 +-
src/southbridge/intel/bd82x6x/me.c | 18 +-
src/southbridge/intel/bd82x6x/me_8.x.c | 18 +-
src/southbridge/intel/bd82x6x/pch.h | 4 +
src/southbridge/intel/bd82x6x/sata.c | 6 +-
src/southbridge/intel/bd82x6x/usb_ehci.c | 5 +-
src/southbridge/intel/common/spi.c | 30 +-
src/southbridge/intel/esb6300/lpc.c | 2 +-
src/southbridge/intel/esb6300/pic.c | 2 +-
src/southbridge/intel/fsp_bd82x6x/azalia.c | 21 +-
src/southbridge/intel/fsp_bd82x6x/bootblock.c | 2 +-
src/southbridge/intel/fsp_bd82x6x/early_init.c | 2 +-
src/southbridge/intel/fsp_bd82x6x/me.c | 18 +-
src/southbridge/intel/fsp_bd82x6x/me_8.x.c | 18 +-
src/southbridge/intel/fsp_bd82x6x/pch.h | 4 +
src/southbridge/intel/fsp_bd82x6x/sata.c | 10 +-
src/southbridge/intel/fsp_rangeley/early_init.c | 11 +-
src/southbridge/intel/fsp_rangeley/gpio.c | 26 +-
src/southbridge/intel/fsp_rangeley/lpc.c | 24 +-
src/southbridge/intel/fsp_rangeley/romstage.c | 2 +-
src/southbridge/intel/fsp_rangeley/sata.c | 10 +-
src/southbridge/intel/fsp_rangeley/soc.h | 4 +
src/southbridge/intel/fsp_rangeley/spi.c | 22 +-
src/southbridge/intel/i3100/lpc.c | 2 +-
src/southbridge/intel/i82801ax/lpc.c | 4 +-
src/southbridge/intel/i82801bx/lpc.c | 4 +-
src/southbridge/intel/i82801cx/lpc.c | 4 +-
src/southbridge/intel/i82801dx/lpc.c | 4 +-
src/southbridge/intel/i82801ex/lpc.c | 2 +-
src/southbridge/intel/i82801gx/azalia.c | 18 +-
src/southbridge/intel/i82801gx/bootblock.c | 2 +-
src/southbridge/intel/i82801gx/i82801gx.h | 4 +
src/southbridge/intel/i82801gx/lpc.c | 4 +-
src/southbridge/intel/i82801gx/usb_ehci.c | 4 +-
src/southbridge/intel/i82801ix/dmi_setup.c | 2 +-
src/southbridge/intel/i82801ix/early_init.c | 2 +-
src/southbridge/intel/i82801ix/hdaudio.c | 18 +-
src/southbridge/intel/i82801ix/i82801ix.h | 7 +-
src/southbridge/intel/i82801ix/lpc.c | 2 +-
src/southbridge/intel/i82801ix/sata.c | 6 +-
src/southbridge/intel/i82801ix/thermal.c | 2 +-
src/southbridge/intel/ibexpeak/azalia.c | 21 +-
src/southbridge/intel/ibexpeak/early_thermal.c | 7 +-
src/southbridge/intel/ibexpeak/lpc.c | 10 +-
src/southbridge/intel/ibexpeak/me.c | 18 +-
src/southbridge/intel/ibexpeak/pch.h | 4 +
src/southbridge/intel/ibexpeak/sata.c | 18 +-
src/southbridge/intel/ibexpeak/thermal.c | 17 +-
src/southbridge/intel/ibexpeak/usb_ehci.c | 5 +-
src/southbridge/intel/lynxpoint/azalia.c | 10 +-
src/southbridge/intel/lynxpoint/bootblock.c | 2 +-
src/southbridge/intel/lynxpoint/early_pch.c | 2 +-
src/southbridge/intel/lynxpoint/hda_verb.c | 12 +-
src/southbridge/intel/lynxpoint/hda_verb.h | 6 +-
src/southbridge/intel/lynxpoint/lpc.c | 12 +-
src/southbridge/intel/lynxpoint/me_9.x.c | 18 +-
src/southbridge/intel/lynxpoint/pch.h | 4 +
src/southbridge/intel/lynxpoint/sata.c | 16 +-
src/southbridge/intel/lynxpoint/serialio.c | 32 +-
src/southbridge/intel/lynxpoint/usb_ehci.c | 8 +-
src/southbridge/intel/lynxpoint/usb_xhci.c | 22 +-
src/southbridge/intel/sch/audio.c | 18 +-
src/southbridge/nvidia/ck804/lpc.c | 2 +-
src/southbridge/nvidia/ck804/nic.c | 10 +-
src/southbridge/nvidia/mcp55/azalia.c | 19 +-
src/southbridge/nvidia/mcp55/lpc.c | 4 +-
src/southbridge/nvidia/mcp55/nic.c | 15 +-
src/southbridge/sis/sis966/aza.c | 18 +-
src/southbridge/sis/sis966/lpc.c | 4 +-
src/southbridge/sis/sis966/nic.c | 28 +-
src/southbridge/sis/sis966/usb2.c | 8 +-
src/southbridge/via/vt8237r/lpc.c | 2 +-
353 files changed, 1901 insertions(+), 1686 deletions(-)
diff --git a/src/arch/x86/boot/mpspec.c b/src/arch/x86/boot/mpspec.c
index 8049be4..299a383 100644
--- a/src/arch/x86/boot/mpspec.c
+++ b/src/arch/x86/boot/mpspec.c
@@ -222,7 +222,7 @@ static void smp_write_bus(struct mp_config_table *mc,
* APIC Flags:EN, Address
*/
void smp_write_ioapic(struct mp_config_table *mc,
- u8 id, u8 ver, u32 apicaddr)
+ u8 id, u8 ver, void *apicaddr)
{
struct mpc_config_ioapic *mpc;
mpc = smp_next_mpc_entry(mc);
diff --git a/src/arch/x86/include/arch/ebda.h b/src/arch/x86/include/arch/ebda.h
index 1de6097..9ecb822 100644
--- a/src/arch/x86/include/arch/ebda.h
+++ b/src/arch/x86/include/arch/ebda.h
@@ -23,9 +23,9 @@
#define __ARCH_EBDA_H
#define X86_BDA_SIZE 0x200
-#define X86_BDA_BASE 0x400
-#define X86_EBDA_SEGMENT 0x40e
-#define X86_EBDA_LOWMEM 0x413
+#define X86_BDA_BASE (void *)0x400
+#define X86_EBDA_SEGMENT (void *)0x40e
+#define X86_EBDA_LOWMEM (void *)0x413
#define DEFAULT_EBDA_LOWMEM (1024 << 10)
#define DEFAULT_EBDA_SEGMENT 0xF600
diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h
index d5cdf35..9987578 100644
--- a/src/arch/x86/include/arch/io.h
+++ b/src/arch/x86/include/arch/io.h
@@ -142,32 +142,32 @@ static inline void insl(uint16_t port, void *addr, unsigned long count)
);
}
-static inline __attribute__((always_inline)) uint8_t read8(unsigned long addr)
+static inline __attribute__((always_inline)) uint8_t read8(const volatile void *addr)
{
return *((volatile uint8_t *)(addr));
}
-static inline __attribute__((always_inline)) uint16_t read16(unsigned long addr)
+static inline __attribute__((always_inline)) uint16_t read16(const volatile void *addr)
{
return *((volatile uint16_t *)(addr));
}
-static inline __attribute__((always_inline)) uint32_t read32(unsigned long addr)
+static inline __attribute__((always_inline)) uint32_t read32(const volatile void *addr)
{
return *((volatile uint32_t *)(addr));
}
-static inline __attribute__((always_inline)) void write8(unsigned long addr, uint8_t value)
+static inline __attribute__((always_inline)) void write8(volatile void *addr, uint8_t value)
{
*((volatile uint8_t *)(addr)) = value;
}
-static inline __attribute__((always_inline)) void write16(unsigned long addr, uint16_t value)
+static inline __attribute__((always_inline)) void write16(volatile void *addr, uint16_t value)
{
*((volatile uint16_t *)(addr)) = value;
}
-static inline __attribute__((always_inline)) void write32(unsigned long addr, uint32_t value)
+static inline __attribute__((always_inline)) void write32(volatile void *addr, uint32_t value)
{
*((volatile uint32_t *)(addr)) = value;
}
diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h
index bb0a35e..8dfa883 100644
--- a/src/arch/x86/include/arch/ioapic.h
+++ b/src/arch/x86/include/arch/ioapic.h
@@ -21,6 +21,7 @@
#define __I386_ARCH_IOAPIC_H
#define IO_APIC_ADDR 0xfec00000
+#define VIO_APIC_VADDR ((u8 *)IO_APIC_ADDR)
#define IO_APIC_INTERRUPTS 24
#ifndef __ACPI__
@@ -42,11 +43,11 @@
#define SMI (2 << 8)
#define INT (1 << 8)
-u32 io_apic_read(u32 ioapic_base, u32 reg);
-void io_apic_write(u32 ioapic_base, u32 reg, u32 value);
-void set_ioapic_id(u32 ioapic_base, u8 ioapic_id);
-void setup_ioapic(u32 ioapic_base, u8 ioapic_id);
-void clear_ioapic(u32 ioapic_base);
+u32 io_apic_read(u8 *ioapic_base, u32 reg);
+void io_apic_write(u8 *ioapic_base, u32 reg, u32 value);
+void set_ioapic_id(u8 *ioapic_base, u8 ioapic_id);
+void setup_ioapic(u8 *ioapic_base, u8 ioapic_id);
+void clear_ioapic(u8 *ioapic_base);
#endif
#endif
diff --git a/src/arch/x86/include/arch/pci_mmio_cfg.h b/src/arch/x86/include/arch/pci_mmio_cfg.h
index b62a2166b..7966903 100644
--- a/src/arch/x86/include/arch/pci_mmio_cfg.h
+++ b/src/arch/x86/include/arch/pci_mmio_cfg.h
@@ -28,48 +28,48 @@
static inline __attribute__ ((always_inline))
u8 pcie_read_config8(pci_devfn_t dev, unsigned int where)
{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | where;
+ void *addr;
+ addr = (void *)(DEFAULT_PCIEXBAR | dev | where);
return read8(addr);
}
static inline __attribute__ ((always_inline))
u16 pcie_read_config16(pci_devfn_t dev, unsigned int where)
{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | (where & ~1);
+ void *addr;
+ addr = (void *)(DEFAULT_PCIEXBAR | dev | (where & ~1));
return read16(addr);
}
static inline __attribute__ ((always_inline))
u32 pcie_read_config32(pci_devfn_t dev, unsigned int where)
{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | (where & ~3);
+ void *addr;
+ addr = (void *)(DEFAULT_PCIEXBAR | dev | (where & ~3));
return read32(addr);
}
static inline __attribute__ ((always_inline))
void pcie_write_config8(pci_devfn_t dev, unsigned int where, u8 value)
{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | where;
+ void *addr;
+ addr = (void *)(DEFAULT_PCIEXBAR | dev | where);
write8(addr, value);
}
static inline __attribute__ ((always_inline))
void pcie_write_config16(pci_devfn_t dev, unsigned int where, u16 value)
{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | (where & ~1);
+ void *addr;
+ addr = (void *)(DEFAULT_PCIEXBAR | dev | (where & ~1));
write16(addr, value);
}
static inline __attribute__ ((always_inline))
void pcie_write_config32(pci_devfn_t dev, unsigned int where, u32 value)
{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | (where & ~3);
+ void *addr;
+ addr = (void *)(DEFAULT_PCIEXBAR | dev | (where & ~3));
write32(addr, value);
}
diff --git a/src/arch/x86/include/arch/smp/mpspec.h b/src/arch/x86/include/arch/smp/mpspec.h
index 8e74e46..481d8a5 100644
--- a/src/arch/x86/include/arch/smp/mpspec.h
+++ b/src/arch/x86/include/arch/smp/mpspec.h
@@ -123,7 +123,7 @@ struct mpc_config_ioapic
u8 mpc_apicver;
u8 mpc_flags;
#define MPC_APIC_USABLE 0x01
- u32 mpc_apicaddr;
+ void *mpc_apicaddr;
} __attribute__((packed));
struct mpc_config_intsrc
@@ -260,7 +260,7 @@ void smp_write_processor(struct mp_config_table *mc,
u32 featureflag);
void smp_write_processors(struct mp_config_table *mc);
void smp_write_ioapic(struct mp_config_table *mc,
- u8 id, u8 ver, u32 apicaddr);
+ u8 id, u8 ver, void *apicaddr);
void smp_write_intsrc(struct mp_config_table *mc,
u8 irqtype, u16 irqflag, u8 srcbus, u8 srcbusirq,
u8 dstapic, u8 dstirq);
diff --git a/src/arch/x86/lib/ebda.c b/src/arch/x86/lib/ebda.c
index 7efc662..c6fa4a6 100644
--- a/src/arch/x86/lib/ebda.c
+++ b/src/arch/x86/lib/ebda.c
@@ -42,7 +42,7 @@ void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size)
/* Set up EBDA */
memset((void *)(ebda_segment << 4), 0, ebda_size);
- write16((ebda_segment << 4), (ebda_size >> 10));
+ write16((void*)(ebda_segment << 4), (ebda_size >> 10));
}
void setup_default_ebda(void)
diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c
index 7fb25ba..5c1969f 100644
--- a/src/arch/x86/lib/ioapic.c
+++ b/src/arch/x86/lib/ioapic.c
@@ -22,19 +22,19 @@
#include <console/console.h>
#include <cpu/x86/lapic.h>
-u32 io_apic_read(u32 ioapic_base, u32 reg)
+u32 io_apic_read(u8 *ioapic_base, u32 reg)
{
write32(ioapic_base, reg);
return read32(ioapic_base + 0x10);
}
-void io_apic_write(u32 ioapic_base, u32 reg, u32 value)
+void io_apic_write(u8 *ioapic_base, u32 reg, u32 value)
{
write32(ioapic_base, reg);
write32(ioapic_base + 0x10, value);
}
-static int ioapic_interrupt_count(int ioapic_base)
+static int ioapic_interrupt_count(u8 *ioapic_base)
{
/* Read the available number of interrupts. */
int ioapic_interrupts = (io_apic_read(ioapic_base, 0x01) >> 16) & 0xff;
@@ -48,12 +48,12 @@ static int ioapic_interrupt_count(int ioapic_base)
return ioapic_interrupts;
}
-void clear_ioapic(u32 ioapic_base)
+void clear_ioapic(u8 *ioapic_base)
{
u32 low, high;
u32 i, ioapic_interrupts;
- printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at 0x%08x\n", ioapic_base);
+ printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at 0x%p\n", ioapic_base);
ioapic_interrupts = ioapic_interrupt_count(ioapic_base);
@@ -74,12 +74,12 @@ void clear_ioapic(u32 ioapic_base)
}
}
-void set_ioapic_id(u32 ioapic_base, u8 ioapic_id)
+void set_ioapic_id(u8 *ioapic_base, u8 ioapic_id)
{
u32 bsp_lapicid = lapicid();
int i;
- printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n",
+ printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%p\n",
ioapic_base);
printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n",
bsp_lapicid);
@@ -99,7 +99,7 @@ void set_ioapic_id(u32 ioapic_base, u8 ioapic_id)
}
-static void load_vectors(u32 ioapic_base)
+static void load_vectors(u8 *ioapic_base)
{
u32 bsp_lapicid = lapicid();
u32 low, high;
@@ -146,7 +146,7 @@ static void load_vectors(u32 ioapic_base)
}
}
-void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
+void setup_ioapic(u8 *ioapic_base, u8 ioapic_id)
{
set_ioapic_id(ioapic_base, ioapic_id);
load_vectors(ioapic_base);
diff --git a/src/arch/x86/lib/pci_ops_mmconf.c b/src/arch/x86/lib/pci_ops_mmconf.c
index 4eaf297..1ce1aa8 100644
--- a/src/arch/x86/lib/pci_ops_mmconf.c
+++ b/src/arch/x86/lib/pci_ops_mmconf.c
@@ -9,46 +9,46 @@
* Functions for accessing PCI configuration space with mmconf accesses
*/
-#define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE) \
- (CONFIG_MMCONF_BASE_ADDRESS |\
+#define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE, MASK) \
+ ((void *)((CONFIG_MMCONF_BASE_ADDRESS | \
(((SEGBUS) & 0xFFF) << 20) |\
(((DEVFN) & 0xFF) << 12) |\
- ((WHERE) & 0xFFF))
+ ((WHERE) & 0xFFF)) & ~MASK))
static uint8_t pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn,
int where)
{
- return (read8(PCI_MMIO_ADDR(bus, devfn, where)));
+ return read8(PCI_MMIO_ADDR(bus, devfn, where, 0));
}
static uint16_t pci_mmconf_read_config16(struct bus *pbus, int bus, int devfn,
int where)
{
- return (read16(PCI_MMIO_ADDR(bus, devfn, where) & ~1));
+ return read16(PCI_MMIO_ADDR(bus, devfn, where, 1));
}
static uint32_t pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn,
int where)
{
- return (read32(PCI_MMIO_ADDR(bus, devfn, where) & ~3));
+ return read32(PCI_MMIO_ADDR(bus, devfn, where, 3));
}
static void pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn,
int where, uint8_t value)
{
- write8(PCI_MMIO_ADDR(bus, devfn, where), value);
+ write8(PCI_MMIO_ADDR(bus, devfn, where, 0), value);
}
static void pci_mmconf_write_config16(struct bus *pbus, int bus, int devfn,
int where, uint16_t value)
{
- write16(PCI_MMIO_ADDR(bus, devfn, where) & ~1, value);
+ write16(PCI_MMIO_ADDR(bus, devfn, where, 1), value);
}
static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn,
int where, uint32_t value)
{
- write32(PCI_MMIO_ADDR(bus, devfn, where) & ~3, value);
+ write32(PCI_MMIO_ADDR(bus, devfn, where, 3), value);
}
const struct pci_bus_operations pci_ops_mmconf = {
diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c
index b250f3d..d93fb3a 100644
--- a/src/device/azalia_device.c
+++ b/src/device/azalia_device.c
@@ -30,7 +30,7 @@
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
@@ -59,7 +59,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
return 0;
}
-static int codec_detect(u32 base)
+static int codec_detect(u8 *base)
{
u32 reg32;
int count;
@@ -136,7 +136,7 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
* no response would imply that the codec is non-operative
*/
-static int wait_for_ready(u32 base)
+static int wait_for_ready(u8 *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -159,14 +159,15 @@ static int wait_for_ready(u32 base)
* is non-operative
*/
-static int wait_for_valid(u32 base)
+static int wait_for_valid(u8 *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
int timeout = 25;
- write32(base + HDA_ICII_REG, HDA_ICII_VALID | HDA_ICII_BUSY);
+ write32(base + HDA_ICII_REG,
+ HDA_ICII_VALID | HDA_ICII_BUSY);
while (timeout--) {
udelay(1);
}
@@ -182,7 +183,7 @@ static int wait_for_valid(u32 base)
return -1;
}
-static void codec_init(struct device *dev, u32 base, int addr)
+static void codec_init(struct device *dev, u8 *base, int addr)
{
u32 reg32;
const u32 *verb;
@@ -226,7 +227,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n");
}
-static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
+static void codecs_init(struct device *dev, u8 *base, u32 codec_mask)
{
int i;
@@ -238,7 +239,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
void azalia_audio_init(struct device *dev)
{
- u32 base;
+ u8 *base;
struct resource *res;
u32 codec_mask;
@@ -248,8 +249,8 @@ void azalia_audio_init(struct device *dev)
// NOTE this will break as soon as the azalia_audio get's a bar above
// 4G. Is there anything we can do about it?
- base = (u32) res->base;
- printk(BIOS_DEBUG, "azalia_audio: base = %08x\n", (u32) base);
+ base = res2mmio(res, 0, 0);
+ printk(BIOS_DEBUG, "azalia_audio: base = %p\n", base);
codec_mask = codec_detect(base);
if (codec_mask) {
diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c
index fc3c40c..c3f87a8 100644
--- a/src/device/oprom/realmode/x86.c
+++ b/src/device/oprom/realmode/x86.c
@@ -80,7 +80,7 @@ static void setup_rombios(void)
memcpy((void *)0xfffd9, &ident, 7);
/* system model: IBM-AT */
- write8(0xffffe, 0xfc);
+ write8((void *)0xffffe, 0xfc);
}
static int (*intXX_handler[256])(void) = { NULL };
diff --git a/src/drivers/ati/ragexl/atyfb.h b/src/drivers/ati/ragexl/atyfb.h
index 94f31fe..df8dd3d 100644
--- a/src/drivers/ati/ragexl/atyfb.h
+++ b/src/drivers/ati/ragexl/atyfb.h
@@ -104,7 +104,7 @@ struct fb_info_aty {
struct fb_info_aty *next;
unsigned long ati_regbase_phys;
#endif
- unsigned long ati_regbase;
+ u8 *ati_regbase;
#if 0
unsigned long frame_buffer_phys;
#endif
diff --git a/src/drivers/ati/ragexl/fb.h b/src/drivers/ati/ragexl/fb.h
index 48d0f01..f112d0e 100644
--- a/src/drivers/ati/ragexl/fb.h
+++ b/src/drivers/ati/ragexl/fb.h
@@ -124,7 +124,7 @@ struct fb_fix_screeninfo {
u16 ypanstep; /* zero if no hardware panning */
u16 ywrapstep; /* zero if no hardware ywrap */
u32 line_length; /* length of a line in bytes */
- unsigned long mmio_start; /* Start of Memory Mapped I/O */
+ u8 *mmio_start; /* Start of Memory Mapped I/O */
/* (physical address) */
u32 mmio_len; /* Length of Memory Mapped I/O */
u32 accel; /* Type of acceleration available */
diff --git a/src/drivers/ati/ragexl/xlinit.c b/src/drivers/ati/ragexl/xlinit.c
index 41cea72..1929180 100644
--- a/src/drivers/ati/ragexl/xlinit.c
+++ b/src/drivers/ati/ragexl/xlinit.c
@@ -537,13 +537,13 @@ static void ati_ragexl_init(struct device *dev)
#endif /* CONFIG_CONSOLE_BTEXT */
#if USE_AUX_REG==0
- info->ati_regbase = res->base+0x7ff000+0xc00;
+ info->ati_regbase = res2mmio(res, 0x7ff000+0xc00, 0);
#else
/* Fix this to look for the correct index. */
//if (dev->resource_list && dev->resource_list->next)
res = dev->resource_list->next->next;
if(res->flags & IORESOURCE_MEM) {
- info->ati_regbase = res->base+0x400; //using auxiliary register
+ info->ati_regbase = res2mmio(res, 0x400, 0); //using auxiliary register
}
#endif
@@ -553,7 +553,7 @@ static void ati_ragexl_init(struct device *dev)
#endif
#if 0
- printk(BIOS_DEBUG, "ati_regbase = 0x%08x, frame_buffer = 0x%08x\n", info->ati_regbase, info->frame_buffer);
+ printk(BIOS_DEBUG, "ati_regbase = 0x%p, frame_buffer = 0x%08x\n", info->ati_regbase, info->frame_buffer);
#endif
chip_id = aty_ld_le32(CONFIG_CHIP_ID, info);
diff --git a/src/drivers/generic/ioapic/chip.h b/src/drivers/generic/ioapic/chip.h
index 665e926..e74c60c 100644
--- a/src/drivers/generic/ioapic/chip.h
+++ b/src/drivers/generic/ioapic/chip.h
@@ -27,7 +27,7 @@ typedef struct drivers_generic_ioapic_config {
u8 irq_on_fsb;
u8 enable_virtual_wire;
u8 have_isa_interrupts;
- u32 base;
+ void *base;
} ioapic_config_t;
#endif
diff --git a/src/drivers/generic/ioapic/ioapic.c b/src/drivers/generic/ioapic/ioapic.c
index 463474a..44f1b02 100644
--- a/src/drivers/generic/ioapic/ioapic.c
+++ b/src/drivers/generic/ioapic/ioapic.c
@@ -18,7 +18,7 @@ static void ioapic_init(struct device *dev)
u32 bsp_lapicid = lapicid();
u32 low, high;
u32 i, ioapic_interrupts;
- u32 ioapic_base;
+ void *ioapic_base;
u8 ioapic_id;
if (!dev->enabled || !config)
@@ -27,7 +27,7 @@ static void ioapic_init(struct device *dev)
ioapic_base = config->base;
ioapic_id = config->apicid;
- printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n",
+ printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%p\n",
ioapic_base);
printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n",
bsp_lapicid);
@@ -93,7 +93,7 @@ static void ioapic_read_resources(struct device *dev)
struct resource *res;
res = new_resource(dev, 0);
- res->base = config->base;
+ res->base = (resource_t)(uintptr_t)config->base;
res->size = 0x1000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c
index 91ad742..36d8813 100644
--- a/src/drivers/intel/gma/edid.c
+++ b/src/drivers/intel/gma/edid.c
@@ -26,7 +26,7 @@
#include "i915_reg.h"
#include "edid.h"
-static void wait_rdy(u32 mmio)
+static void wait_rdy(u8 *mmio)
{
unsigned try = 100;
@@ -37,7 +37,7 @@ static void wait_rdy(u32 mmio)
}
}
-void intel_gmbus_read_edid(u32 mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size)
+void intel_gmbus_read_edid(u8 *mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size)
{
int i;
diff --git a/src/drivers/intel/gma/edid.h b/src/drivers/intel/gma/edid.h
index cb54b46..c476391 100644
--- a/src/drivers/intel/gma/edid.h
+++ b/src/drivers/intel/gma/edid.h
@@ -1 +1 @@
-void intel_gmbus_read_edid(u32 gmbus_mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size);
+void intel_gmbus_read_edid(u8 *gmbus_mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size);
diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c
index 83c23a3..379a1bd 100644
--- a/src/drivers/usb/ehci_debug.c
+++ b/src/drivers/usb/ehci_debug.c
@@ -78,7 +78,7 @@ static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug)
int loop = 0;
do {
- ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = read32(&ehci_debug->control);
/* Stop when the transaction is finished */
if (ctrl & DBGP_DONE)
break;
@@ -92,7 +92,7 @@ static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug)
/* Now that we have observed the completed transaction,
* clear the done bit.
*/
- write32((unsigned long)&ehci_debug->control, ctrl | DBGP_DONE);
+ write32(&ehci_debug->control, ctrl | DBGP_DONE);
return (ctrl & DBGP_ERROR) ? -DBGP_ERRCODE(ctrl) : DBGP_LEN(ctrl);
}
@@ -122,10 +122,10 @@ host_retry:
if (loop == 1 || host_retries > 1)
dprintk(BIOS_SPEW, "dbgp: start (@ %3d,%d) ctrl=%08x\n",
loop, host_retries, ctrl | DBGP_GO);
- write32((unsigned long)&ehci_debug->control, ctrl | DBGP_GO);
+ write32(&ehci_debug->control, ctrl | DBGP_GO);
ret = dbgp_wait_until_complete(ehci_debug);
- rd_ctrl = read32((unsigned long)&ehci_debug->control);
- rd_pids = read32((unsigned long)&ehci_debug->pids);
+ rd_ctrl = read32(&ehci_debug->control);
+ rd_pids = read32(&ehci_debug->pids);
if (rd_ctrl != ctrl_prev || rd_pids != pids_prev || (ret<0)) {
ctrl_prev = rd_ctrl;
@@ -184,8 +184,8 @@ static void dbgp_set_data(struct ehci_dbg_port *ehci_debug, const void *buf, int
lo |= bytes[i] << (8*i);
for (; i < 8 && i < size; i++)
hi |= bytes[i] << (8*(i - 4));
- write32((unsigned long)&ehci_debug->data03, lo);
- write32((unsigned long)&ehci_debug->data47, hi);
+ write32(&ehci_debug->data03, lo);
+ write32(&ehci_debug->data47, hi);
}
static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size)
@@ -194,8 +194,8 @@ static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size)
u32 lo, hi;
int i;
- lo = read32((unsigned long)&ehci_debug->data03);
- hi = read32((unsigned long)&ehci_debug->data47);
+ lo = read32(&ehci_debug->data03);
+ hi = read32(&ehci_debug->data47);
for (i = 0; i < 4 && i < size; i++)
bytes[i] = (lo >> (8*i)) & 0xff;
for (; i < 8 && i < size; i++)
@@ -205,9 +205,9 @@ static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size)
#if CONFIG_DEBUG_USBDEBUG
static void dbgp_print_data(struct ehci_dbg_port *ehci_debug)
{
- u32 ctrl = read32((unsigned long)&ehci_debug->control);
- u32 lo = read32((unsigned long)&ehci_debug->data03);
- u32 hi = read32((unsigned long)&ehci_debug->data47);
+ u32 ctrl = read32(&ehci_debug->control);
+ u32 lo = read32(&ehci_debug->data03);
+ u32 hi = read32(&ehci_debug->data47);
int len = DBGP_LEN(ctrl);
if (len) {
int i;
@@ -233,13 +233,13 @@ static int dbgp_bulk_write(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *p
addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint);
pids = DBGP_PID_SET(pipe->pid, USB_PID_OUT);
- ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = read32(&ehci_debug->control);
ctrl = DBGP_LEN_UPDATE(ctrl, size);
ctrl |= DBGP_OUT;
dbgp_set_data(ehci_debug, bytes, size);
- write32((unsigned long)&ehci_debug->address, addr);
- write32((unsigned long)&ehci_debug->pids, pids);
+ write32(&ehci_debug->address, addr);
+ write32(&ehci_debug->pids, pids);
ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout);
@@ -264,12 +264,12 @@ static int dbgp_bulk_read(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pi
addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint);
pids = DBGP_PID_SET(pipe->pid, USB_PID_IN);
- ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = read32(&ehci_debug->control);
ctrl = DBGP_LEN_UPDATE(ctrl, size);
ctrl &= ~DBGP_OUT;
- write32((unsigned long)&ehci_debug->address, addr);
- write32((unsigned long)&ehci_debug->pids, pids);
+ write32(&ehci_debug->address, addr);
+ write32(&ehci_debug->pids, pids);
ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout);
if (ret < 0)
return ret;
@@ -324,14 +324,14 @@ int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, int requ
addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint);
pids = DBGP_PID_SET(pipe->pid, USB_PID_SETUP);
- ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = read32(&ehci_debug->control);
ctrl = DBGP_LEN_UPDATE(ctrl, sizeof(req));
ctrl |= DBGP_OUT;
/* Setup stage */
dbgp_set_data(ehci_debug, &req, sizeof(req));
- write32((unsigned long)&ehci_debug->address, addr);
- write32((unsigned long)&ehci_debug->pids, pids);
+ write32(&ehci_debug->address, addr);
+ write32(&ehci_debug->pids, pids);
ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, 1);
if (ret < 0)
return ret;
@@ -344,7 +344,7 @@ int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, int requ
/* Status stage in opposite direction */
pipe->pid = USB_PID_DATA1;
- ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = read32(&ehci_debug->control);
ctrl = DBGP_LEN_UPDATE(ctrl, 0);
if (read) {
pids = DBGP_PID_SET(pipe->pid, USB_PID_OUT);
@@ -354,7 +354,7 @@ int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, int requ
ctrl &= ~DBGP_OUT;
}
- write32((unsigned long)&ehci_debug->pids, pids);
+ write32(&ehci_debug->pids, pids);
ret2 = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout);
if (ret2 < 0)
return ret2;
@@ -368,21 +368,21 @@ static int ehci_reset_port(struct ehci_regs *ehci_regs, int port)
int loop;
/* Reset the usb debug port */
- portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]);
+ portsc = read32(&ehci_regs->port_status[port - 1]);
portsc &= ~PORT_PE;
portsc |= PORT_RESET;
- write32((unsigned long)&ehci_regs->port_status[port - 1], portsc);
+ write32(&ehci_regs->port_status[port - 1], portsc);
dbgp_mdelay(HUB_ROOT_RESET_TIME);
- portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]);
- write32((unsigned long)&ehci_regs->port_status[port - 1],
+ portsc = read32(&ehci_regs->port_status[port - 1]);
+ write32(&ehci_regs->port_status[port - 1],
portsc & ~(PORT_RWC_BITS | PORT_RESET));
loop = 100;
do {
dbgp_mdelay(1);
- portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]);
+ portsc = read32(&ehci_regs->port_status[port - 1]);
} while ((portsc & PORT_RESET) && (--loop > 0));
/* Device went away? */
@@ -407,7 +407,7 @@ static int ehci_wait_for_port(struct ehci_regs *ehci_regs, int port)
for (reps = 0; reps < 3; reps++) {
dbgp_mdelay(100);
- status = read32((unsigned long)&ehci_regs->status);
+ status = read32(&ehci_regs->status);
if (status & STS_PCD) {
ret = ehci_reset_port(ehci_regs, port);
if (ret == 0)
@@ -440,7 +440,7 @@ static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_
ehci_caps = (struct ehci_caps *)ehci_bar;
ehci_regs = (struct ehci_regs *)(ehci_bar +
- HC_LENGTH(read32((unsigned long)&ehci_caps->hc_capbase)));
+ HC_LENGTH(read32(&ehci_caps->hc_capbase)));
struct ehci_dbg_port *ehci_debug = info->ehci_debug;
@@ -453,7 +453,7 @@ try_next_time:
port_map_tried = 0;
try_next_port:
- hcs_params = read32((unsigned long)&ehci_caps->hcs_params);
+ hcs_params = read32(&ehci_caps->hcs_params);
debug_port = HCS_DEBUG_PORT(hcs_params);
n_ports = HCS_N_PORTS(hcs_params);
@@ -461,7 +461,7 @@ try_next_port:
dprintk(BIOS_INFO, "n_ports: %d\n", n_ports);
for (i = 1; i <= n_ports; i++) {
- portsc = read32((unsigned long)&ehci_regs->port_status[i-1]);
+ portsc = read32(&ehci_regs->port_status[i-1]);
dprintk(BIOS_INFO, "PORTSC #%d: %08x\n", i, portsc);
}
@@ -474,15 +474,15 @@ try_next_port:
}
/* Wait until the controller is halted */
- status = read32((unsigned long)&ehci_regs->status);
+ status = read32(&ehci_regs->status);
if (!(status & STS_HALT)) {
- cmd = read32((unsigned long)&ehci_regs->command);
+ cmd = read32(&ehci_regs->command);
cmd &= ~CMD_RUN;
- write32((unsigned long)&ehci_regs->command, cmd);
+ write32(&ehci_regs->command, cmd);
loop = 100;
do {
dbgp_mdelay(10);
- status = read32((unsigned long)&ehci_regs->status);
+ status = read32(&ehci_regs->status);
} while (!(status & STS_HALT) && (--loop > 0));
if (status & STS_HALT)
dprintk(BIOS_INFO, "EHCI controller halted successfully.\n");
@@ -492,12 +492,12 @@ try_next_port:
loop = 100;
/* Reset the EHCI controller */
- cmd = read32((unsigned long)&ehci_regs->command);
+ cmd = read32(&ehci_regs->command);
cmd |= CMD_RESET;
- write32((unsigned long)&ehci_regs->command, cmd);
+ write32(&ehci_regs->command, cmd);
do {
dbgp_mdelay(10);
- cmd = read32((unsigned long)&ehci_regs->command);
+ cmd = read32(&ehci_regs->command);
} while ((cmd & CMD_RESET) && (--loop > 0));
if(!loop) {
@@ -509,25 +509,25 @@ try_next_port:
}
/* Claim ownership, but do not enable yet */
- ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = read32(&ehci_debug->control);
ctrl |= DBGP_OWNER;
ctrl &= ~(DBGP_ENABLED | DBGP_INUSE);
- write32((unsigned long)&ehci_debug->control, ctrl);
+ write32(&ehci_debug->control, ctrl);
/* Start EHCI controller */
- cmd = read32((unsigned long)&ehci_regs->command);
+ cmd = read32(&ehci_regs->command);
cmd &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE | CMD_ASE | CMD_RESET);
cmd |= CMD_RUN;
- write32((unsigned long)&ehci_regs->command, cmd);
+ write32(&ehci_regs->command, cmd);
/* Ensure everything is routed to the EHCI */
- write32((unsigned long)&ehci_regs->configured_flag, FLAG_CF);
+ write32(&ehci_regs->configured_flag, FLAG_CF);
/* Wait until the controller is no longer halted */
loop = 10;
do {
dbgp_mdelay(10);
- status = read32((unsigned long)&ehci_regs->status);
+ status = read32(&ehci_regs->status);
} while ((status & STS_HALT) && (--loop > 0));
if(!loop) {
@@ -546,13 +546,13 @@ try_next_port:
/* Enable the debug port */
- ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = read32(&ehci_debug->control);
ctrl |= DBGP_CLAIM;
- write32((unsigned long)&ehci_debug->control, ctrl);
- ctrl = read32((unsigned long)&ehci_debug->control);
+ write32(&ehci_debug->control, ctrl);
+ ctrl = read32(&ehci_debug->control);
if ((ctrl & DBGP_CLAIM) != DBGP_CLAIM) {
dprintk(BIOS_INFO, "No device in EHCI debug port.\n");
- write32((unsigned long)&ehci_debug->control, ctrl & ~DBGP_CLAIM);
+ write32(&ehci_debug->control, ctrl & ~DBGP_CLAIM);
ret = -4;
goto err;
}
@@ -560,9 +560,9 @@ try_next_port:
#if 0
/* Completely transfer the debug device to the debug controller */
- portsc = read32((unsigned long)&ehci_regs->port_status[debug_port - 1]);
+ portsc = read32(&ehci_regs->port_status[debug_port - 1]);
portsc &= ~PORT_PE;
- write32((unsigned long)&ehci_regs->port_status[debug_port - 1], portsc);
+ write32(&ehci_regs->port_status[debug_port - 1], portsc);
#endif
dbgp_mdelay(100);
@@ -577,9 +577,9 @@ try_next_port:
return 0;
err:
/* Things didn't work so remove my claim */
- ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = read32(&ehci_debug->control);
ctrl &= ~(DBGP_CLAIM | DBGP_OUT);
- write32((unsigned long)(unsigned long)&ehci_debug->control, ctrl);
+ write32(&ehci_debug->control, ctrl);
//return ret;
next_debug_port:
diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c
index 8fe78b1..04f8232 100644
--- a/src/drivers/usb/pci_ehci.c
+++ b/src/drivers/usb/pci_ehci.c
@@ -103,13 +103,13 @@ void pci_ehci_read_resources(struct device *dev)
}
#endif
-unsigned long pci_ehci_base_regs(pci_devfn_t sdev)
+u8 *pci_ehci_base_regs(pci_devfn_t sdev)
{
#ifdef __SIMPLE_DEVICE__
- unsigned long base = pci_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f;
+ u8 *base = (u8 *)(pci_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f);
#else
device_t dev = dev_find_slot(PCI_DEV2SEGBUS(sdev), PCI_DEV2DEVFN(sdev));
- unsigned long base = pci_read_config32(dev, EHCI_BAR_INDEX) & ~0x0f;
+ u8 *base = (u8 *)(pci_read_config32(dev, EHCI_BAR_INDEX) & ~0x0f);
#endif
return base + HC_LENGTH(read32(base));
}
diff --git a/src/include/device/pci_ehci.h b/src/include/device/pci_ehci.h
index 4d3f746..bd6b969 100644
--- a/src/include/device/pci_ehci.h
+++ b/src/include/device/pci_ehci.h
@@ -28,7 +28,7 @@
#define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */
pci_devfn_t pci_ehci_dbg_dev(unsigned hcd_idx);
-unsigned long pci_ehci_base_regs(pci_devfn_t dev);
+u8 *pci_ehci_base_regs(pci_devfn_t dev);
void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port);
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base);
diff --git a/src/include/device/resource.h b/src/include/device/resource.h
index 2d64c80..c01540a 100644
--- a/src/include/device/resource.h
+++ b/src/include/device/resource.h
@@ -74,4 +74,10 @@ extern void search_global_resources(
#define RESOURCE_TYPE_MAX 20
extern const char *resource_type(struct resource *resource);
+static inline void *res2mmio(struct resource *res, unsigned long offset,
+ unsigned long mask)
+{
+ return (void *)(uintptr_t)((res->base + offset) & ~mask);
+}
+
#endif /* DEVICE_RESOURCE_H */
diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c
index 647723b..2fd943e 100644
--- a/src/lib/reg_script.c
+++ b/src/lib/reg_script.c
@@ -155,11 +155,11 @@ static uint32_t reg_script_read_mmio(struct reg_script_context *ctx)
switch (step->size) {
case REG_SCRIPT_SIZE_8:
- return read8(step->reg);
+ return read8((u8 *)step->reg);
case REG_SCRIPT_SIZE_16:
- return read16(step->reg);
+ return read16((u16 *)step->reg);
case REG_SCRIPT_SIZE_32:
- return read32(step->reg);
+ return read32((u32 *)step->reg);
}
return 0;
}
@@ -170,13 +170,13 @@ static void reg_script_write_mmio(struct reg_script_context *ctx)
switch (step->size) {
case REG_SCRIPT_SIZE_8:
- write8(step->reg, step->value);
+ write8((u8 *)step->reg, step->value);
break;
case REG_SCRIPT_SIZE_16:
- write16(step->reg, step->value);
+ write16((u16 *)step->reg, step->value);
break;
case REG_SCRIPT_SIZE_32:
- write32(step->reg, step->value);
+ write32((u32 *)step->reg, step->value);
break;
}
}
diff --git a/src/mainboard/advansus/a785e-i/mptable.c b/src/mainboard/advansus/a785e-i/mptable.c
index b04cf41..9d4feb8 100644
--- a/src/mainboard/advansus/a785e-i/mptable.c
+++ b/src/mainboard/advansus/a785e-i/mptable.c
@@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
dword &= 0xFFFFFFF0;
- smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword);
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
diff --git a/src/mainboard/amd/bimini_fam10/mptable.c b/src/mainboard/amd/bimini_fam10/mptable.c
index 1d0f5bf..ea3cc72 100644
--- a/src/mainboard/amd/bimini_fam10/mptable.c
+++ b/src/mainboard/amd/bimini_fam10/mptable.c
@@ -66,7 +66,7 @@ static void *smp_write_config_table(void *v)
dword |= (pm_ioread(0x35) & 0xFF) << 8;
dword |= (pm_ioread(0x36) & 0xFF) << 16;
dword |= (pm_ioread(0x37) & 0xFF) << 24;
- smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword);
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
diff --git a/src/mainboard/amd/dbm690t/mptable.c b/src/mainboard/amd/dbm690t/mptable.c
index 09d137a..511db71 100644
--- a/src/mainboard/amd/dbm690t/mptable.c
+++ b/src/mainboard/amd/dbm690t/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb600 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb600, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb600,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c
index 4e481f5..197d1c3 100644
--- a/src/mainboard/amd/dinar/mptable.c
+++ b/src/mainboard/amd/dinar/mptable.c
@@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v)
u32 apicid_sb700;
u32 apicid_rd890;
device_t dev;
- u32 dword;
+ u8 *dword;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
if (dev) {
/* Set sb700 IOAPIC ID */
- dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
+ dword = (u8 *)(pci_read_config32(dev, 0x74) & 0xfffffff0);
smp_write_ioapic(mc, apicid_sb700, 0x20, dword);
/*
@@ -80,7 +80,7 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (dev) {
pci_write_config32(dev, 0xF8, 0x1);
- dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
+ dword = (u8 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
smp_write_ioapic(mc, apicid_rd890, 0x20, dword);
}
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index 7686bd2..44eda71 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -52,8 +52,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -65,7 +65,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
u8 byte;
diff --git a/src/mainboard/amd/mahogany/mptable.c b/src/mainboard/amd/mahogany/mptable.c
index bd31846..4c1946c 100644
--- a/src/mainboard/amd/mahogany/mptable.c
+++ b/src/mainboard/amd/mahogany/mptable.c
@@ -60,7 +60,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb700,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/amd/mahogany_fam10/mptable.c b/src/mainboard/amd/mahogany_fam10/mptable.c
index 11426c2..6786103 100644
--- a/src/mainboard/amd/mahogany_fam10/mptable.c
+++ b/src/mainboard/amd/mahogany_fam10/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb700,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c
index db4a3ff..db3ffb1 100644
--- a/src/mainboard/amd/olivehill/mptable.c
+++ b/src/mainboard/amd/olivehill/mptable.c
@@ -75,8 +75,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -92,9 +92,9 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
- smp_write_ioapic(mc, ioapic_id+1, 0x21, 0xFEC20000);
+ smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00);
diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c
index 80ba5b5..b9675ed 100644
--- a/src/mainboard/amd/olivehillplus/mptable.c
+++ b/src/mainboard/amd/olivehillplus/mptable.c
@@ -75,8 +75,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -92,9 +92,9 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
- smp_write_ioapic(mc, ioapic_id+1, 0x21, 0xFEC20000);
+ smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00);
diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c
index 05da01a..cb0bbba 100644
--- a/src/mainboard/amd/parmer/mptable.c
+++ b/src/mainboard/amd/parmer/mptable.c
@@ -75,8 +75,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -92,7 +92,7 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
index 1227d89..0cf57bd 100644
--- a/src/mainboard/amd/persimmon/mptable.c
+++ b/src/mainboard/amd/persimmon/mptable.c
@@ -41,8 +41,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
/* Intialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -67,7 +67,7 @@ static void *smp_write_config_table(void *v)
* Type 2: I/O APICs:
* APIC ID, Version, APIC Flags:EN, Address
*/
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/*
* Type 3: I/O Interrupt Table Entries:
diff --git a/src/mainboard/amd/pistachio/mptable.c b/src/mainboard/amd/pistachio/mptable.c
index 09d137a..511db71 100644
--- a/src/mainboard/amd/pistachio/mptable.c
+++ b/src/mainboard/amd/pistachio/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb600 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb600, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb600,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c
index 866875d..56df3fa 100644
--- a/src/mainboard/amd/serengeti_cheetah/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah/mptable.c
@@ -29,7 +29,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
+ smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); //8111
{
device_t dev;
struct resource *res;
@@ -37,14 +37,16 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_8132_1, 0x11,
+ res2mmio(res, 0, 0));
}
}
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_8132_2, 0x11,
+ res2mmio(res, 0, 0));
}
}
@@ -60,14 +62,16 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11,
+ res2mmio(res, 0, 0));
}
}
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11,
+ res2mmio(res, 0, 0));
}
}
break;
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
index 5335cb8..56c6fc0 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
@@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
+ smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); //8111
{
device_t dev;
struct resource *res;
@@ -56,14 +56,16 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_8132_1, 0x11,
+ res2mmio(res, 0, 0));
}
}
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_8132_2, 0x11,
+ res2mmio(res, 0, 0));
}
}
@@ -79,14 +81,16 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11,
+ res2mmio(res, 0, 0));
}
}
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11,
+ res2mmio(res, 0, 0));
}
}
break;
diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c
index c2ec4a2..6b35ce8 100644
--- a/src/mainboard/amd/south_station/mptable.c
+++ b/src/mainboard/amd/south_station/mptable.c
@@ -49,8 +49,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
u8 byte;
diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c
index 8ddd1b6..f6d5e6e 100644
--- a/src/mainboard/amd/thatcher/mptable.c
+++ b/src/mainboard/amd/thatcher/mptable.c
@@ -75,8 +75,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -92,7 +92,7 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
diff --git a/src/mainboard/amd/tilapia_fam10/mptable.c b/src/mainboard/amd/tilapia_fam10/mptable.c
index 11426c2..6786103 100644
--- a/src/mainboard/amd/tilapia_fam10/mptable.c
+++ b/src/mainboard/amd/tilapia_fam10/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb700,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c
index 477d97a..02206a9 100644
--- a/src/mainboard/amd/torpedo/mptable.c
+++ b/src/mainboard/amd/torpedo/mptable.c
@@ -107,11 +107,11 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
- u32 dword;
+ u8 *dword;
u8 byte;
- ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
- dword &= 0xFFFFFFF0;
+ ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
+ dword = (u8 *)(((uintptr_t) dword) & 0xFFFFFFF0);
/* Set IO APIC ID onto IO_APIC_ID */
write32 (dword, 0x00);
write32 (dword + 0x10, IO_APIC_ID << 24);
diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c
index c2ec4a2..b6e196a 100644
--- a/src/mainboard/amd/union_station/mptable.c
+++ b/src/mainboard/amd/union_station/mptable.c
@@ -49,8 +49,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
u8 byte;
diff --git a/src/mainboard/apple/macbook21/mptable.c b/src/mainboard/apple/macbook21/mptable.c
index cc97e52..27ab1e0 100644
--- a/src/mainboard/apple/macbook21/mptable.c
+++ b/src/mainboard/apple/macbook21/mptable.c
@@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);
/* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c
index 6ee2704..d6c3d2f 100644
--- a/src/mainboard/arima/hdama/mptable.c
+++ b/src/mainboard/arima/hdama/mptable.c
@@ -125,7 +125,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */
- smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
+ smp_write_ioapic(mc, apicid_8111, 0x11, VIO_APIC_VADDR);
{
device_t dev;
struct resource *res;
@@ -134,7 +134,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_1, 0x11,
+ res2mmio(res, 0, 0));
}
}
/* 8131 apic 4 */
@@ -142,7 +143,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_2, 0x11,
+ res2mmio(res, 0, 0));
}
}
}
diff --git a/src/mainboard/asrock/939a785gmh/mptable.c b/src/mainboard/asrock/939a785gmh/mptable.c
index 790d1da..fe2ebd8 100644
--- a/src/mainboard/asrock/939a785gmh/mptable.c
+++ b/src/mainboard/asrock/939a785gmh/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb700,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
index 14fa316..897a077 100644
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ b/src/mainboard/asrock/e350m1/mptable.c
@@ -50,8 +50,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -63,7 +63,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
u8 byte;
diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c
index d9ca7b7..90fa10d 100644
--- a/src/mainboard/asrock/imb-a180/mptable.c
+++ b/src/mainboard/asrock/imb-a180/mptable.c
@@ -76,8 +76,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -93,9 +93,9 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
- smp_write_ioapic(mc, ioapic_id+1, 0x21, 0xFEC20000);
+ smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00);
diff --git a/src/mainboard/asus/a8n_e/mptable.c b/src/mainboard/asus/a8n_e/mptable.c
index a954d92..56d2150 100644
--- a/src/mainboard/asus/a8n_e/mptable.c
+++ b/src/mainboard/asus/a8n_e/mptable.c
@@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v)
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
smp_write_ioapic(mc, apicid_ck804, 0x11,
- res->base);
+ res2mmio(res, 0, 0));
}
/* Initialize interrupt mapping. */
diff --git a/src/mainboard/asus/a8v-e_deluxe/mptable.c b/src/mainboard/asus/a8v-e_deluxe/mptable.c
index 71e0e1e..ebd15ba 100644
--- a/src/mainboard/asus/a8v-e_deluxe/mptable.c
+++ b/src/mainboard/asus/a8v-e_deluxe/mptable.c
@@ -38,8 +38,8 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR);
- smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE);
+ smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VIO_APIC_VADDR);
+ smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, (void *)K8T890_APIC_BASE);
mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
diff --git a/src/mainboard/asus/a8v-e_se/mptable.c b/src/mainboard/asus/a8v-e_se/mptable.c
index 71e0e1e..ebd15ba 100644
--- a/src/mainboard/asus/a8v-e_se/mptable.c
+++ b/src/mainboard/asus/a8v-e_se/mptable.c
@@ -38,8 +38,8 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR);
- smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE);
+ smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VIO_APIC_VADDR);
+ smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, (void *)K8T890_APIC_BASE);
mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
diff --git a/src/mainboard/asus/dsbf/devicetree.cb b/src/mainboard/asus/dsbf/devicetree.cb
index b4d1b63..0d3b6c8 100644
--- a/src/mainboard/asus/dsbf/devicetree.cb
+++ b/src/mainboard/asus/dsbf/devicetree.cb
@@ -91,13 +91,13 @@ chip northbridge/intel/i5000
register "have_isa_interrupts" = "1"
register "irq_on_fsb" = "1"
register "enable_virtual_wire" = "1"
- register "base" = "0xfec00000"
+ register "base" = "(void *)0xfec00000"
device ioapic 8 on end
end
chip drivers/generic/ioapic
register "irq_on_fsb" = "1"
- register "base" = "0xfec80000"
+ register "base" = "(void *)0xfec80000"
device ioapic 9 on end
end
diff --git a/src/mainboard/asus/dsbf/romstage.c b/src/mainboard/asus/dsbf/romstage.c
index d7bcb89..699aae1 100644
--- a/src/mainboard/asus/dsbf/romstage.c
+++ b/src/mainboard/asus/dsbf/romstage.c
@@ -49,7 +49,7 @@ static void early_config(void)
u32 gcs, rpc, fd;
/* Enable RCBA */
- pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1);
+ pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
/* Disable watchdog */
gcs = read32(DEFAULT_RCBA + RCBA_GCS);
@@ -138,7 +138,7 @@ void main(unsigned long bist)
smbus_write_byte(0x6f, 0x08, 0x06);
smbus_write_byte(0x6f, 0x09, 0x00);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, DEFAULT_RCBA | 1);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, (uintptr_t)DEFAULT_RCBA | 1);
i5000_fbdimm_init();
smbus_write_byte(0x69, 0x01, 0x01);
}
diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c
index cc81819..7509dd0 100644
--- a/src/mainboard/asus/f2a85-m/mptable.c
+++ b/src/mainboard/asus/f2a85-m/mptable.c
@@ -75,8 +75,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -92,7 +92,7 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c
index 794194c..59ff9aa 100644
--- a/src/mainboard/asus/k8v-x/mptable.c
+++ b/src/mainboard/asus/k8v-x/mptable.c
@@ -38,8 +38,8 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR);
- smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE);
+ smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VIO_APIC_VADDR);
+ smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, (void *)K8T890_APIC_BASE);
mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
diff --git a/src/mainboard/asus/m2n-e/mptable.c b/src/mainboard/asus/m2n-e/mptable.c
index 333ec49..824ee31 100644
--- a/src/mainboard/asus/m2n-e/mptable.c
+++ b/src/mainboard/asus/m2n-e/mptable.c
@@ -56,7 +56,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res)
- smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_mcp55, 0x11,
+ res2mmio(res, 0, 0));
pci_write_config32(dev, 0x7c, 0x00000000);
pci_write_config32(dev, 0x80, 0x11002009);
diff --git a/src/mainboard/asus/m2v/mptable.c b/src/mainboard/asus/m2v/mptable.c
index b74a1e3..22c6613 100644
--- a/src/mainboard/asus/m2v/mptable.c
+++ b/src/mainboard/asus/m2v/mptable.c
@@ -48,8 +48,8 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, VT8237R_APIC_ID, 0x3, IO_APIC_ADDR);
- smp_write_ioapic(mc, K8T890_APIC_ID, 0x3, K8T890_APIC_BASE);
+ smp_write_ioapic(mc, VT8237R_APIC_ID, 0x3, VIO_APIC_VADDR);
+ smp_write_ioapic(mc, K8T890_APIC_ID, 0x3, (void*)K8T890_APIC_BASE);
mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
diff --git a/src/mainboard/asus/m4a78-em/mptable.c b/src/mainboard/asus/m4a78-em/mptable.c
index 11426c2..6786103 100644
--- a/src/mainboard/asus/m4a78-em/mptable.c
+++ b/src/mainboard/asus/m4a78-em/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb700,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/asus/m4a785-m/mptable.c b/src/mainboard/asus/m4a785-m/mptable.c
index 11426c2..6786103 100644
--- a/src/mainboard/asus/m4a785-m/mptable.c
+++ b/src/mainboard/asus/m4a785-m/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb700,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/asus/m5a88-v/mptable.c b/src/mainboard/asus/m5a88-v/mptable.c
index 5259dec..4d6bb22 100644
--- a/src/mainboard/asus/m5a88-v/mptable.c
+++ b/src/mainboard/asus/m5a88-v/mptable.c
@@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
dword &= 0xFFFFFFF0;
- smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword);
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
diff --git a/src/mainboard/asus/p2b-d/mptable.c b/src/mainboard/asus/p2b-d/mptable.c
index 51d00a3..ef9301e 100644
--- a/src/mainboard/asus/p2b-d/mptable.c
+++ b/src/mainboard/asus/p2b-d/mptable.c
@@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v)
ioapic_id = 2;
ioapic_ver = 0x11; /* External Intel 82093AA IOAPIC. */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
diff --git a/src/mainboard/asus/p2b-ds/mptable.c b/src/mainboard/asus/p2b-ds/mptable.c
index ee3c20e..359c810 100644
--- a/src/mainboard/asus/p2b-ds/mptable.c
+++ b/src/mainboard/asus/p2b-ds/mptable.c
@@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v)
ioapic_id = 2;
ioapic_ver = 0x11; /* External Intel 82093AA IOAPIC. */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
diff --git a/src/mainboard/avalue/eax-785e/mptable.c b/src/mainboard/avalue/eax-785e/mptable.c
index 9c25da6..9803fab 100644
--- a/src/mainboard/avalue/eax-785e/mptable.c
+++ b/src/mainboard/avalue/eax-785e/mptable.c
@@ -63,7 +63,7 @@ static void *smp_write_config_table(void *v)
ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
dword &= 0xFFFFFFF0;
- smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword);
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c
index d7ae6b7..d283d85 100644
--- a/src/mainboard/broadcom/blast/mptable.c
+++ b/src/mainboard/broadcom/blast/mptable.c
@@ -41,7 +41,9 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_bcm5785[i], 0x11, res->base);
+ smp_write_ioapic(mc, apicid_bcm5785[i],
+ 0x11,
+ res2mmio(res, 0, 0));
}
}
}
diff --git a/src/mainboard/getac/p470/mptable.c b/src/mainboard/getac/p470/mptable.c
index 9b59bb4..05586b9 100644
--- a/src/mainboard/getac/p470/mptable.c
+++ b/src/mainboard/getac/p470/mptable.c
@@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);
/* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
index 0af6cf0..2f1fad8 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, apicid_sis966, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_sis966, 0x11,
+ res2mmio(res, 0, 0));
}
dword = 0x43c6c643;
diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c
index 1536823..673e9e7 100644
--- a/src/mainboard/gigabyte/m57sli/mptable.c
+++ b/src/mainboard/gigabyte/m57sli/mptable.c
@@ -57,7 +57,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_mcp55, 0x11,
+ res2mmio(res, 0, 0));
}
/* set up the interrupt registers of mcp55 */
pci_write_config32(dev, 0x7c, 0xc643c643);
diff --git a/src/mainboard/gigabyte/ma785gm/mptable.c b/src/mainboard/gigabyte/ma785gm/mptable.c
index 11426c2..6786103 100644
--- a/src/mainboard/gigabyte/ma785gm/mptable.c
+++ b/src/mainboard/gigabyte/ma785gm/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb700,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/gigabyte/ma785gmt/mptable.c b/src/mainboard/gigabyte/ma785gmt/mptable.c
index 11426c2..6786103 100644
--- a/src/mainboard/gigabyte/ma785gmt/mptable.c
+++ b/src/mainboard/gigabyte/ma785gmt/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb700,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/gigabyte/ma78gm/mptable.c b/src/mainboard/gigabyte/ma78gm/mptable.c
index 11426c2..6786103 100644
--- a/src/mainboard/gigabyte/ma78gm/mptable.c
+++ b/src/mainboard/gigabyte/ma78gm/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb700,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c
index b98598a..5db689d 100644
--- a/src/mainboard/gizmosphere/gizmo/mptable.c
+++ b/src/mainboard/gizmosphere/gizmo/mptable.c
@@ -50,8 +50,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -63,7 +63,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
u8 byte;
diff --git a/src/mainboard/gizmosphere/gizmo2/mptable.c b/src/mainboard/gizmosphere/gizmo2/mptable.c
index fbf6744..192b0c0 100644
--- a/src/mainboard/gizmosphere/gizmo2/mptable.c
+++ b/src/mainboard/gizmosphere/gizmo2/mptable.c
@@ -40,8 +40,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
/* Intialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -66,7 +66,7 @@ static void *smp_write_config_table(void *v)
* Type 2: I/O APICs:
* APIC ID, Version, APIC Flags:EN, Address
*/
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/*
* Type 3: I/O Interrupt Table Entries:
diff --git a/src/mainboard/google/bolt/romstage.c b/src/mainboard/google/bolt/romstage.c
index a623ae2..91ac6a0 100644
--- a/src/mainboard/google/bolt/romstage.c
+++ b/src/mainboard/google/bolt/romstage.c
@@ -102,15 +102,15 @@ void mainboard_romstage_entry(unsigned long bist)
{
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
- .mchbar = DEFAULT_MCHBAR,
- .dmibar = DEFAULT_DMIBAR,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = DEFAULT_PCIEXBAR,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = HPET_ADDR,
- .rcba = DEFAULT_RCBA,
+ .rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.temp_mmio_base = 0xfed08000,
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index 70a6f44..b117295 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -81,15 +81,15 @@ void main(unsigned long bist)
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
- .mchbar = DEFAULT_MCHBAR,
- .dmibar = DEFAULT_DMIBAR,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = DEFAULT_RCBABASE,
+ .rcba = (uintptr_t)DEFAULT_RCBABASE,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,
diff --git a/src/mainboard/google/falco/romstage.c b/src/mainboard/google/falco/romstage.c
index 470c1cd..fb811da 100644
--- a/src/mainboard/google/falco/romstage.c
+++ b/src/mainboard/google/falco/romstage.c
@@ -111,15 +111,15 @@ void mainboard_romstage_entry(unsigned long bist)
{
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
- .mchbar = DEFAULT_MCHBAR,
- .dmibar = DEFAULT_DMIBAR,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = DEFAULT_PCIEXBAR,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = HPET_ADDR,
- .rcba = DEFAULT_RCBA,
+ .rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.temp_mmio_base = 0xfed08000,
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index 873de91..b5d64b0 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -122,15 +122,15 @@ void main(unsigned long bist)
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
- .mchbar = DEFAULT_MCHBAR,
- .dmibar = DEFAULT_DMIBAR,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = DEFAULT_RCBABASE,
+ .rcba = (uintptr_t)DEFAULT_RCBABASE,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,
diff --git a/src/mainboard/google/panther/romstage.c b/src/mainboard/google/panther/romstage.c
index dcc935b..48da4b2 100644
--- a/src/mainboard/google/panther/romstage.c
+++ b/src/mainboard/google/panther/romstage.c
@@ -81,15 +81,15 @@ void mainboard_romstage_entry(unsigned long bist)
{
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
- .mchbar = DEFAULT_MCHBAR,
- .dmibar = DEFAULT_DMIBAR,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = DEFAULT_PCIEXBAR,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = HPET_ADDR,
- .rcba = DEFAULT_RCBA,
+ .rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.temp_mmio_base = 0xfed08000,
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index 7d67abd..f2e7345 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -81,15 +81,15 @@ void main(unsigned long bist)
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
- .mchbar = DEFAULT_MCHBAR,
- .dmibar = DEFAULT_DMIBAR,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = DEFAULT_RCBABASE,
+ .rcba = (uintptr_t)DEFAULT_RCBABASE,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,
diff --git a/src/mainboard/google/peppy/romstage.c b/src/mainboard/google/peppy/romstage.c
index 9a1fb76..f8d9cb9 100644
--- a/src/mainboard/google/peppy/romstage.c
+++ b/src/mainboard/google/peppy/romstage.c
@@ -122,15 +122,15 @@ void mainboard_romstage_entry(unsigned long bist)
{
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
- .mchbar = DEFAULT_MCHBAR,
- .dmibar = DEFAULT_DMIBAR,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = DEFAULT_PCIEXBAR,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = HPET_ADDR,
- .rcba = DEFAULT_RCBA,
+ .rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.temp_mmio_base = 0xfed08000,
diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c
index 6feebac..8f6df2f 100644
--- a/src/mainboard/google/slippy/romstage.c
+++ b/src/mainboard/google/slippy/romstage.c
@@ -137,15 +137,15 @@ void mainboard_romstage_entry(unsigned long bist)
{
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
- .mchbar = DEFAULT_MCHBAR,
- .dmibar = DEFAULT_DMIBAR,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = DEFAULT_PCIEXBAR,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = HPET_ADDR,
- .rcba = DEFAULT_RCBA,
+ .rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.temp_mmio_base = 0xfed08000,
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index f856c59..714d8f1 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -122,15 +122,15 @@ void main(unsigned long bist)
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
- .mchbar = DEFAULT_MCHBAR,
- .dmibar = DEFAULT_DMIBAR,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = DEFAULT_RCBABASE,
+ .rcba = (uintptr_t)DEFAULT_RCBABASE,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,
diff --git a/src/mainboard/hp/abm/mptable.c b/src/mainboard/hp/abm/mptable.c
index 629888a..4140356 100644
--- a/src/mainboard/hp/abm/mptable.c
+++ b/src/mainboard/hp/abm/mptable.c
@@ -76,8 +76,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -93,9 +93,9 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
- smp_write_ioapic(mc, ioapic_id+1, 0x21, 0xFEC20000);
+ smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00);
diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c
index b9af38b..1a9132e 100644
--- a/src/mainboard/hp/dl145_g1/mptable.c
+++ b/src/mainboard/hp/dl145_g1/mptable.c
@@ -29,7 +29,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, m->apicid_8111, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, m->apicid_8111, 0x20, VIO_APIC_VADDR);
{
device_t dev;
struct resource *res;
@@ -37,14 +37,16 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_8131_1, 0x20, res->base);
+ smp_write_ioapic(mc, m->apicid_8131_1, 0x20,
+ res2mmio(res, 0, 0));
}
}
dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_8131_2, 0x20, res->base);
+ smp_write_ioapic(mc, m->apicid_8131_2, 0x20,
+ res2mmio(res, 0, 0));
}
}
diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c
index 6c71bad..d89352d 100644
--- a/src/mainboard/hp/dl145_g3/mptable.c
+++ b/src/mainboard/hp/dl145_g3/mptable.c
@@ -67,7 +67,8 @@ static void *smp_write_config_table(void *v)
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
printk(BIOS_DEBUG, "APIC %d base address: %llx\n",m->apicid_bcm5785[i], res->base);
- smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11,
+ res2mmio(res, 0, 0));
}
}
}
diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c
index 86f2cc6..5eda558 100644
--- a/src/mainboard/hp/dl165_g6_fam10/mptable.c
+++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c
@@ -68,7 +68,8 @@ static void *smp_write_config_table(void *v)
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
printk(BIOS_DEBUG, "APIC %d base address: %x\n",m->apicid_bcm5785[i], (int)res->base);
- smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11,
+ res2mmio(res, 0, 0));
}
}
}
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
index 65b1279..75730b7 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
@@ -76,8 +76,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -93,7 +93,7 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
diff --git a/src/mainboard/ibase/mb899/mptable.c b/src/mainboard/ibase/mb899/mptable.c
index 1baf728..6079a1d 100644
--- a/src/mainboard/ibase/mb899/mptable.c
+++ b/src/mainboard/ibase/mb899/mptable.c
@@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
ioapic_id = 2;
- smp_write_ioapic(mc, ioapic_id, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, 0x20, VIO_APIC_VADDR);
/* Legacy Interrupts */
diff --git a/src/mainboard/ibm/e325/mptable.c b/src/mainboard/ibm/e325/mptable.c
index 6eb6390..1dad72c 100644
--- a/src/mainboard/ibm/e325/mptable.c
+++ b/src/mainboard/ibm/e325/mptable.c
@@ -58,7 +58,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* Legacy IOAPIC #2 */
- smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 2, 0x11, VIO_APIC_VADDR);
{
device_t dev;
struct resource *res;
@@ -67,7 +67,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, 0x03, 0x11, res->base);
+ smp_write_ioapic(mc, 0x03, 0x11,
+ res2mmio(res, 0, 0));
}
}
/* 8131-2 apic #4 */
@@ -75,7 +76,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, 0x04, 0x11, res->base);
+ smp_write_ioapic(mc, 0x04, 0x11,
+ res2mmio(res, 0, 0));
}
}
}
diff --git a/src/mainboard/ibm/e326/mptable.c b/src/mainboard/ibm/e326/mptable.c
index f271166..46dabd3 100644
--- a/src/mainboard/ibm/e326/mptable.c
+++ b/src/mainboard/ibm/e326/mptable.c
@@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* Legacy IOAPIC #2 */
- smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 2, 0x11, VIO_APIC_VADDR);
{
device_t dev;
struct resource *res;
@@ -66,7 +66,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, 0x03, 0x11, res->base);
+ smp_write_ioapic(mc, 0x03, 0x11,
+ res2mmio(res, 0, 0));
}
}
/* 8131-2 apic #4 */
@@ -74,7 +75,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, 0x04, 0x11, res->base);
+ smp_write_ioapic(mc, 0x04, 0x11,
+ res2mmio(res, 0, 0));
}
}
}
diff --git a/src/mainboard/iei/kino-780am2-fam10/mptable.c b/src/mainboard/iei/kino-780am2-fam10/mptable.c
index 11426c2..6786103 100644
--- a/src/mainboard/iei/kino-780am2-fam10/mptable.c
+++ b/src/mainboard/iei/kino-780am2-fam10/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb700,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c
index 7aea6b6..e1bdb30 100644
--- a/src/mainboard/intel/baskingridge/romstage.c
+++ b/src/mainboard/intel/baskingridge/romstage.c
@@ -71,15 +71,15 @@ void mainboard_romstage_entry(unsigned long bist)
{
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
- .mchbar = DEFAULT_MCHBAR,
- .dmibar = DEFAULT_DMIBAR,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = DEFAULT_PCIEXBAR,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = HPET_ADDR,
- .rcba = DEFAULT_RCBA,
+ .rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.temp_mmio_base = 0xfed08000,
diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c
index b0360bf..ee05919 100644
--- a/src/mainboard/intel/d945gclf/mptable.c
+++ b/src/mainboard/intel/d945gclf/mptable.c
@@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);
/* Legacy Interrupts */
diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c
index 809feec..b9c2fc3 100644
--- a/src/mainboard/intel/eagleheights/mptable.c
+++ b/src/mainboard/intel/eagleheights/mptable.c
@@ -67,14 +67,14 @@ static void *smp_write_config_table(void *v)
uint32_t pin, route;
device_t dev;
struct resource *res;
- unsigned long rcba;
+ u8 *rcba;
dev = dev_find_slot(0, PCI_DEVFN(0x1F,0));
res = find_resource(dev, RCBA);
if (!res) {
return NULL;
}
- rcba = res->base;
+ rcba = res2mmio(res, 0, 0);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -121,7 +121,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);
mptable_add_isa_interrupts(mc, bus_isa, IO_APIC0, 0);
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index 5700162..a45ef7e 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -83,7 +83,7 @@ static void early_config(void)
u32 gcs, rpc, fd;
/* Enable RCBA */
- pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1);
+ pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
/* Disable watchdog */
gcs = read32(DEFAULT_RCBA + RCBA_GCS);
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index adcf175..45d92d8 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -135,15 +135,15 @@ void main(unsigned long bist)
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
- .mchbar = DEFAULT_MCHBAR,
- .dmibar = DEFAULT_DMIBAR,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = DEFAULT_RCBABASE,
+ .rcba = (uintptr_t)DEFAULT_RCBABASE,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,
diff --git a/src/mainboard/intel/mohonpeak/romstage.c b/src/mainboard/intel/mohonpeak/romstage.c
index ba5091a..e06682c 100644
--- a/src/mainboard/intel/mohonpeak/romstage.c
+++ b/src/mainboard/intel/mohonpeak/romstage.c
@@ -32,7 +32,7 @@
static void interrupt_routing_config(void)
{
- u32 ilb_base = pci_read_config32(SOC_LPC_DEV, IBASE) & ~0xf;
+ u8 *ilb_base = (u8 *)(pci_read_config32(SOC_LPC_DEV, IBASE) & ~0xf);
/*
* Initialize Interrupt Routings for each device in ilb_base_address.
diff --git a/src/mainboard/intel/mtarvon/mptable.c b/src/mainboard/intel/mtarvon/mptable.c
index 4dd13f9..fa07fd7 100644
--- a/src/mainboard/intel/mtarvon/mptable.c
+++ b/src/mainboard/intel/mtarvon/mptable.c
@@ -42,7 +42,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */
- smp_write_ioapic(mc, 0x01, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 0x01, 0x20, VIO_APIC_VADDR);
mptable_add_isa_interrupts(mc, bus_isa, 0x1, 0);
diff --git a/src/mainboard/intel/truxton/mptable.c b/src/mainboard/intel/truxton/mptable.c
index 9ad6ea6..87b40dd 100644
--- a/src/mainboard/intel/truxton/mptable.c
+++ b/src/mainboard/intel/truxton/mptable.c
@@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */
- smp_write_ioapic(mc, 0x8, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 0x8, 0x20, VIO_APIC_VADDR);
mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0);
diff --git a/src/mainboard/iwave/iWRainbowG6/mptable.c b/src/mainboard/iwave/iWRainbowG6/mptable.c
index 87de022..218f4f8 100644
--- a/src/mainboard/iwave/iWRainbowG6/mptable.c
+++ b/src/mainboard/iwave/iWRainbowG6/mptable.c
@@ -34,7 +34,7 @@ void *smp_write_config_table(void *v)
smp_write_processors(mc);
mptable_write_buses(mc, NULL, &isa_bus);
- smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);
{
device_t dev;
struct resource *res;
diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c
index ff6e582..eecad5c 100644
--- a/src/mainboard/iwill/dk8_htx/mptable.c
+++ b/src/mainboard/iwill/dk8_htx/mptable.c
@@ -29,7 +29,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
+ smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); //8111
{
device_t dev;
struct resource *res;
@@ -37,14 +37,16 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_8132_1, 0x11,
+ res2mmio(res, 0, 0));
}
}
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_8132_2, 0x11,
+ res2mmio(res, 0, 0));
}
}
@@ -60,14 +62,16 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11,
+ res2mmio(res, 0, 0));
}
}
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11,
+ res2mmio(res, 0, 0));
}
}
break;
diff --git a/src/mainboard/iwill/dk8s2/mptable.c b/src/mainboard/iwill/dk8s2/mptable.c
index c7bb33d..b460ff7 100644
--- a/src/mainboard/iwill/dk8s2/mptable.c
+++ b/src/mainboard/iwill/dk8s2/mptable.c
@@ -54,7 +54,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */
- smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 2, 0x11, VIO_APIC_VADDR);
{
device_t dev;
struct resource *res;
@@ -63,7 +63,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, 0x03, 0x11, res->base);
+ smp_write_ioapic(mc, 0x03, 0x11,
+ res2mmio(res, 0, 0));
}
}
/* 8131 apic 4 */
@@ -71,7 +72,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, 0x04, 0x11, res->base);
+ smp_write_ioapic(mc, 0x04, 0x11,
+ res2mmio(res, 0, 0));
}
}
}
diff --git a/src/mainboard/iwill/dk8x/mptable.c b/src/mainboard/iwill/dk8x/mptable.c
index c7bb33d..b460ff7 100644
--- a/src/mainboard/iwill/dk8x/mptable.c
+++ b/src/mainboard/iwill/dk8x/mptable.c
@@ -54,7 +54,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */
- smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 2, 0x11, VIO_APIC_VADDR);
{
device_t dev;
struct resource *res;
@@ -63,7 +63,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, 0x03, 0x11, res->base);
+ smp_write_ioapic(mc, 0x03, 0x11,
+ res2mmio(res, 0, 0));
}
}
/* 8131 apic 4 */
@@ -71,7 +72,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, 0x04, 0x11, res->base);
+ smp_write_ioapic(mc, 0x04, 0x11,
+ res2mmio(res, 0, 0));
}
}
}
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
index 4390605..cc73c83 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
@@ -44,8 +44,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
/* Intialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v)
* Type 2: I/O APICs:
* APIC ID, Version, APIC Flags:EN, Address
*/
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/*
* Type 3: I/O Interrupt Table Entries:
diff --git a/src/mainboard/jetway/pa78vm5/mptable.c b/src/mainboard/jetway/pa78vm5/mptable.c
index 7cabdf1..e28d057 100644
--- a/src/mainboard/jetway/pa78vm5/mptable.c
+++ b/src/mainboard/jetway/pa78vm5/mptable.c
@@ -60,7 +60,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb700,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c
index 03f7370..2df0a44 100644
--- a/src/mainboard/kontron/986lcd-m/mptable.c
+++ b/src/mainboard/kontron/986lcd-m/mptable.c
@@ -56,7 +56,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
ioapic_id = 2;
- smp_write_ioapic(mc, ioapic_id, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, 0x20, VIO_APIC_VADDR);
/* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
diff --git a/src/mainboard/kontron/kt690/mptable.c b/src/mainboard/kontron/kt690/mptable.c
index 8b86b02..45212be 100644
--- a/src/mainboard/kontron/kt690/mptable.c
+++ b/src/mainboard/kontron/kt690/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb600 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb600, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb600,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c
index 31f1b22..22dc33d 100644
--- a/src/mainboard/kontron/ktqm77/romstage.c
+++ b/src/mainboard/kontron/ktqm77/romstage.c
@@ -112,15 +112,15 @@ void main(unsigned long bist)
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
- .mchbar = DEFAULT_MCHBAR,
- .dmibar = DEFAULT_DMIBAR,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = DEFAULT_RCBABASE,
+ .rcba = (uintptr_t)DEFAULT_RCBABASE,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,
diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c
index 65b1279..75730b7 100644
--- a/src/mainboard/lenovo/g505s/mptable.c
+++ b/src/mainboard/lenovo/g505s/mptable.c
@@ -76,8 +76,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -93,7 +93,7 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
diff --git a/src/mainboard/lenovo/t60/mptable.c b/src/mainboard/lenovo/t60/mptable.c
index 744ef30..8a245cc 100644
--- a/src/mainboard/lenovo/t60/mptable.c
+++ b/src/mainboard/lenovo/t60/mptable.c
@@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);
/* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb
index edd3c64..cc27d25 100644
--- a/src/mainboard/lenovo/x200/devicetree.cb
+++ b/src/mainboard/lenovo/x200/devicetree.cb
@@ -77,7 +77,7 @@ chip northbridge/intel/gm45
register "have_isa_interrupts" = "1"
register "irq_on_fsb" = "1"
register "enable_virtual_wire" = "1"
- register "base" = "0xfec00000"
+ register "base" = "(void *)0xfec00000"
device ioapic 2 on end
end
diff --git a/src/mainboard/lenovo/x60/mptable.c b/src/mainboard/lenovo/x60/mptable.c
index 8ade71b..9ebb106 100644
--- a/src/mainboard/lenovo/x60/mptable.c
+++ b/src/mainboard/lenovo/x60/mptable.c
@@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);
/* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c
index 078601e..b7a1862 100644
--- a/src/mainboard/lippert/frontrunner-af/mptable.c
+++ b/src/mainboard/lippert/frontrunner-af/mptable.c
@@ -48,8 +48,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -61,7 +61,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
u8 byte;
diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c
index 078601e..b7a1862 100644
--- a/src/mainboard/lippert/toucan-af/mptable.c
+++ b/src/mainboard/lippert/toucan-af/mptable.c
@@ -48,8 +48,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -61,7 +61,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
u8 byte;
diff --git a/src/mainboard/msi/ms7135/mptable.c b/src/mainboard/msi/ms7135/mptable.c
index b43a516..fb4ae8b 100644
--- a/src/mainboard/msi/ms7135/mptable.c
+++ b/src/mainboard/msi/ms7135/mptable.c
@@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v)
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
smp_write_ioapic(mc, apicid_ck804, 0x11,
- res->base);
+ res2mmio(res, 0, 0));
}
/* Initialize interrupt mapping */
diff --git a/src/mainboard/msi/ms7260/mptable.c b/src/mainboard/msi/ms7260/mptable.c
index ea003a8..cbe26aa 100644
--- a/src/mainboard/msi/ms7260/mptable.c
+++ b/src/mainboard/msi/ms7260/mptable.c
@@ -56,7 +56,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res)
- smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_mcp55, 0x11,
+ res2mmio(res, 0, 0));
dword = 0x43c6c643;
pci_write_config32(dev, 0x7c, dword);
diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c
index b30ab73..6f6e638 100644
--- a/src/mainboard/msi/ms9185/mptable.c
+++ b/src/mainboard/msi/ms9185/mptable.c
@@ -63,7 +63,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11,
+ res2mmio(res, 0, 0));
}
}
}
diff --git a/src/mainboard/msi/ms9282/mptable.c b/src/mainboard/msi/ms9282/mptable.c
index 1764cf3..b6efdd0 100644
--- a/src/mainboard/msi/ms9282/mptable.c
+++ b/src/mainboard/msi/ms9282/mptable.c
@@ -60,7 +60,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_mcp55, 0x11,
+ res2mmio(res, 0, 0));
}
dword = 0x43c6c643;
diff --git a/src/mainboard/msi/ms9652_fam10/mptable.c b/src/mainboard/msi/ms9652_fam10/mptable.c
index 09a25f2..e718493 100644
--- a/src/mainboard/msi/ms9652_fam10/mptable.c
+++ b/src/mainboard/msi/ms9652_fam10/mptable.c
@@ -57,7 +57,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_mcp55, 0x11,
+ res2mmio(res, 0, 0));
}
dword = 0x43c6c643;
diff --git a/src/mainboard/newisys/khepri/mptable.c b/src/mainboard/newisys/khepri/mptable.c
index 1d7c79e..7e2e597 100644
--- a/src/mainboard/newisys/khepri/mptable.c
+++ b/src/mainboard/newisys/khepri/mptable.c
@@ -55,7 +55,7 @@ static void *smp_write_config_table(void *v)
/* IOAPIC handling */
- smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 2, 0x11, VIO_APIC_VADDR);
{
device_t dev;
struct resource *res;
@@ -64,7 +64,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, 0x03, 0x11, res->base);
+ smp_write_ioapic(mc, 0x03, 0x11,
+ res2mmio(res, 0, 0));
}
}
/* 8131 apic 4 */
@@ -72,7 +73,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, 0x04, 0x11, res->base);
+ smp_write_ioapic(mc, 0x04, 0x11,
+ res2mmio(res, 0, 0));
}
}
}
diff --git a/src/mainboard/nvidia/l1_2pvv/mptable.c b/src/mainboard/nvidia/l1_2pvv/mptable.c
index e991efd..fe6a095 100644
--- a/src/mainboard/nvidia/l1_2pvv/mptable.c
+++ b/src/mainboard/nvidia/l1_2pvv/mptable.c
@@ -57,7 +57,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res)
- smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_mcp55, 0x11,
+ res2mmio(res, 0, 0));
/* Initialize interrupt mapping*/
dword = pci_read_config32(dev, 0x74);
@@ -81,7 +82,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res)
- smp_write_ioapic(mc, m->apicid_mcp55b, 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_mcp55b, 0x11,
+ res2mmio(res, 0, 0));
dword = 0x43c60000;
pci_write_config32(dev, 0x7c, dword);
diff --git a/src/mainboard/roda/rk886ex/mptable.c b/src/mainboard/roda/rk886ex/mptable.c
index 9b59bb4..05586b9 100644
--- a/src/mainboard/roda/rk886ex/mptable.c
+++ b/src/mainboard/roda/rk886ex/mptable.c
@@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);
/* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb
index deece86..2bd2358 100644
--- a/src/mainboard/roda/rk9/devicetree.cb
+++ b/src/mainboard/roda/rk9/devicetree.cb
@@ -66,7 +66,7 @@ chip northbridge/intel/gm45
register "have_isa_interrupts" = "1"
register "irq_on_fsb" = "1"
register "enable_virtual_wire" = "1"
- register "base" = "0xfec00000"
+ register "base" = "(void *)0xfec00000"
device ioapic 2 on end
end
diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb
index 9b0fc40..0372614 100644
--- a/src/mainboard/samsung/lumpy/devicetree.cb
+++ b/src/mainboard/samsung/lumpy/devicetree.cb
@@ -112,7 +112,7 @@ chip northbridge/intel/sandybridge
register "have_isa_interrupts" = "1"
register "irq_on_fsb" = "1"
register "enable_virtual_wire" = "1"
- register "base" = "0xfec00000"
+ register "base" = "(void *)0xfec00000"
device ioapic 4 on end
end
end
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index a8c1249..98f5c7d 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -106,15 +106,15 @@ void main(unsigned long bist)
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
- .mchbar = DEFAULT_MCHBAR,
- .dmibar = DEFAULT_DMIBAR,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = DEFAULT_RCBABASE,
+ .rcba = (uintptr_t)DEFAULT_RCBABASE,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index c5c2095..5db8773 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -144,15 +144,15 @@ void main(unsigned long bist)
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
- .mchbar = DEFAULT_MCHBAR,
- .dmibar = DEFAULT_DMIBAR,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = DEFAULT_RCBABASE,
+ .rcba = (uintptr_t)DEFAULT_RCBABASE,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,
diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c
index de5151d..8cc6c97 100644
--- a/src/mainboard/siemens/sitemp_g1p1/mptable.c
+++ b/src/mainboard/siemens/sitemp_g1p1/mptable.c
@@ -55,7 +55,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
struct resource *res;
res = find_resource(dev, 0x74);
- smp_write_ioapic(mc, apicid_sb600, 0x20, res->base);
+ smp_write_ioapic(mc, apicid_sb600, 0x20,
+ res2mmio(res, 0, 0));
}
}
mptable_add_isa_interrupts(mc, isa_bus, apicid_sb600, 0);
diff --git a/src/mainboard/sunw/ultra40/mptable.c b/src/mainboard/sunw/ultra40/mptable.c
index 1ba1dcf..eeae519 100644
--- a/src/mainboard/sunw/ultra40/mptable.c
+++ b/src/mainboard/sunw/ultra40/mptable.c
@@ -57,7 +57,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_ck804, 0x11,
+ res2mmio(res, 0, 0));
}
/* Initialize interrupt mapping*/
@@ -77,14 +78,16 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_1, 0x11,
+ res2mmio(res, 0, 0));
}
}
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_2, 0x11,
+ res2mmio(res, 0, 0));
}
}
@@ -93,7 +96,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, apicid_ck804b, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_ck804b, 0x11,
+ res2mmio(res, 0, 0));
}
dword = 0x0000d218;
diff --git a/src/mainboard/supermicro/h8dme/mptable.c b/src/mainboard/supermicro/h8dme/mptable.c
index 17067ed..b301eb9 100644
--- a/src/mainboard/supermicro/h8dme/mptable.c
+++ b/src/mainboard/supermicro/h8dme/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_mcp55, 0x11,
+ res2mmio(res, 0, 0));
}
dword = 0x43c6c643;
diff --git a/src/mainboard/supermicro/h8dmr/mptable.c b/src/mainboard/supermicro/h8dmr/mptable.c
index 11db23f..9ebcb87 100644
--- a/src/mainboard/supermicro/h8dmr/mptable.c
+++ b/src/mainboard/supermicro/h8dmr/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_mcp55, 0x11,
+ res2mmio(res, 0, 0));
}
dword = 0x43c6c643;
diff --git a/src/mainboard/supermicro/h8dmr_fam10/mptable.c b/src/mainboard/supermicro/h8dmr_fam10/mptable.c
index 4e2d48c..9ed0160 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/mptable.c
@@ -56,7 +56,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_mcp55, 0x11,
+ res2mmio(res, 0, 0));
}
dword = 0x43c6c643;
diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c
index 5ec4a35..63ec044 100644
--- a/src/mainboard/supermicro/h8qgi/mptable.c
+++ b/src/mainboard/supermicro/h8qgi/mptable.c
@@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v)
u32 apicid_sp5100;
u32 apicid_sr5650;
device_t dev;
- u32 dword;
+ u32 *dword;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
if (dev) {
/* Set SP5100 IOAPIC ID */
- dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
+ dword = (u32 *)(pci_read_config32(dev, 0x74) & 0xfffffff0);
smp_write_ioapic(mc, apicid_sp5100, 0x20, dword);
#ifdef UNUSED_CODE
@@ -72,8 +72,8 @@ static void *smp_write_config_table(void *v)
pci_write_config8(dev, 0x63, byte);
/* SATA */
dword = pci_read_config32(dev, 0xAC);
- dword &= ~(7 << 26);
- dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
+ dword = dword & ~(7 << 26);
+ dword = dword | (6 << 26); /* 0: INTA, ...., 7: INTH */
/* dword |= 1<<22; PIC and APIC co exists */
pci_write_config32(dev, 0xAC, dword);
#endif
@@ -96,7 +96,7 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (dev) {
pci_write_config32(dev, 0xF8, 0x1);
- dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
+ dword = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
smp_write_ioapic(mc, apicid_sr5650, 0x20, dword);
}
diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c
index 4fbb4c8..a34a5be 100644
--- a/src/mainboard/supermicro/h8qme_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c
@@ -58,7 +58,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_mcp55, 0x11,
+ res2mmio(res, 0, 0));
}
dword = 0x00000ab5;
diff --git a/src/mainboard/supermicro/h8scm/mptable.c b/src/mainboard/supermicro/h8scm/mptable.c
index 5ec4a35..a47e190 100644
--- a/src/mainboard/supermicro/h8scm/mptable.c
+++ b/src/mainboard/supermicro/h8scm/mptable.c
@@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v)
u32 apicid_sp5100;
u32 apicid_sr5650;
device_t dev;
- u32 dword;
+ u32 *dword;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
if (dev) {
/* Set SP5100 IOAPIC ID */
- dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
+ dword = (u32 *)(pci_read_config32(dev, 0x74) & 0xfffffff0);
smp_write_ioapic(mc, apicid_sp5100, 0x20, dword);
#ifdef UNUSED_CODE
@@ -71,9 +71,9 @@ static void *smp_write_config_table(void *v)
byte |= 0; /* 0: INTA, ...., 7: INTH */
pci_write_config8(dev, 0x63, byte);
/* SATA */
- dword = pci_read_config32(dev, 0xAC);
- dword &= ~(7 << 26);
- dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
+ dword = (u32 *)pci_read_config32(dev, 0xAC);
+ dword = dword & ~(7 << 26);
+ dword = dword | (6 << 26); /* 0: INTA, ...., 7: INTH */
/* dword |= 1<<22; PIC and APIC co exists */
pci_write_config32(dev, 0xAC, dword);
#endif
@@ -96,7 +96,7 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (dev) {
pci_write_config32(dev, 0xF8, 0x1);
- dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
+ dword = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
smp_write_ioapic(mc, apicid_sr5650, 0x20, dword);
}
diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c
index 84593fc..860c417 100644
--- a/src/mainboard/supermicro/h8scm_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8scm_fam10/mptable.c
@@ -56,13 +56,13 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
{
device_t dev;
- u32 dword;
+ u32 *dword;
u8 byte;
dev = dev_find_slot(0, //bus_sp5100[0], TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0.
PCI_DEVFN(sbdn_sp5100 + 0x14, 0));
if (dev) {
- dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
+ dword = (u32 *)(pci_read_config32(dev, 0x74) & 0xfffffff0);
smp_write_ioapic(mc, apicid_sp5100, 0x11, dword);
/* Initialize interrupt mapping */
@@ -73,11 +73,11 @@ static void *smp_write_config_table(void *v)
pci_write_config8(dev, 0x63, byte);
/* SATA */
- dword = pci_read_config32(dev, 0xac);
- dword &= ~(7 << 26);
- dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
+ dword = (u32 *)((pci_read_config32(dev, 0xac) &
+ ~(7 << 26)) | (6 << 26));
+
/* dword |= 1<<22; PIC and APIC co exists */
- pci_write_config32(dev, 0xac, dword);
+ pci_write_config32(dev, 0xac, (u32)dword);
/*
* 00:12.0: PROG SATA : INT F
@@ -96,7 +96,7 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (dev) {
pci_write_config32(dev, 0xF8, 0x1);
- dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
+ dword = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
smp_write_ioapic(mc, apicid_sp5100+1, 0x11, dword);
}
}
diff --git a/src/mainboard/supermicro/x7db8/romstage.c b/src/mainboard/supermicro/x7db8/romstage.c
index b4364a3..53da4b5 100644
--- a/src/mainboard/supermicro/x7db8/romstage.c
+++ b/src/mainboard/supermicro/x7db8/romstage.c
@@ -51,7 +51,7 @@ static void early_config(void)
u32 gcs, rpc, fd;
/* Enable RCBA */
- pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1);
+ pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
/* Disable watchdog */
gcs = read32(DEFAULT_RCBA + RCBA_GCS);
@@ -144,7 +144,7 @@ void main(unsigned long bist)
outb(0x03, 0x11b8);
outb(0x01, 0x11b8);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, DEFAULT_RCBA | 1);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, (uintptr_t)DEFAULT_RCBA | 1);
i5000_fbdimm_init();
smbus_write_byte(0x69, 0x01, 0x01);
}
diff --git a/src/mainboard/technexion/tim5690/mptable.c b/src/mainboard/technexion/tim5690/mptable.c
index 8b86b02..45212be 100644
--- a/src/mainboard/technexion/tim5690/mptable.c
+++ b/src/mainboard/technexion/tim5690/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb600 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb600, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb600,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/technexion/tim8690/mptable.c b/src/mainboard/technexion/tim8690/mptable.c
index 8b86b02..45212be 100644
--- a/src/mainboard/technexion/tim8690/mptable.c
+++ b/src/mainboard/technexion/tim8690/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb600 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb600, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb600,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/thomson/ip1000/mainboard.c b/src/mainboard/thomson/ip1000/mainboard.c
index 7267696..4fb8056 100644
--- a/src/mainboard/thomson/ip1000/mainboard.c
+++ b/src/mainboard/thomson/ip1000/mainboard.c
@@ -65,14 +65,14 @@ static void parport_gpios(void)
static void flash_gpios(void)
{
- u8 manufacturer_id = read8(0xffbc0000);
- u8 device_id = read8(0xffbc0001);
+ u8 manufacturer_id = read8((u8 *)0xffbc0000);
+ u8 device_id = read8((u8 *)0xffbc0001);
if ((manufacturer_id == 0x20) &&
((device_id == 0x2c) || (device_id == 0x2d))) {
printk(BIOS_DEBUG, "Detected ST M50FW0%c0 flash:\n",
(device_id==0x2c)?'4':'8');
- u8 fgpi = read8(0xffbc0100);
+ u8 fgpi = read8((u8 *)0xffbc0100);
printk(BIOS_DEBUG, " FGPI0 [%c] FGPI1 [%c] FGPI2 [%c] FGPI3 [%c] FGPI4 [%c]\n",
(fgpi & (1 << 0)) ? 'X' : ' ',
(fgpi & (1 << 1)) ? 'X' : ' ',
diff --git a/src/mainboard/tyan/s2735/mptable.c b/src/mainboard/tyan/s2735/mptable.c
index 9073728..1d1c2e7 100644
--- a/src/mainboard/tyan/s2735/mptable.c
+++ b/src/mainboard/tyan/s2735/mptable.c
@@ -17,7 +17,7 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
mptable_write_buses(mc, NULL, &isa_bus);
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 8, 0x20, VIO_APIC_VADDR);
{
device_t dev;
struct resource *res;
@@ -25,14 +25,16 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, 0x09, 0x20, res->base);
+ smp_write_ioapic(mc, 0x09, 0x20,
+ res2mmio(res, 0, 0));
}
}
dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, 0x0a, 0x20, res->base);
+ smp_write_ioapic(mc, 0x0a, 0x20,
+ res2mmio(res, 0, 0));
}
}
}
diff --git a/src/mainboard/tyan/s2850/mptable.c b/src/mainboard/tyan/s2850/mptable.c
index 371d9a3..c3fdeef 100644
--- a/src/mainboard/tyan/s2850/mptable.c
+++ b/src/mainboard/tyan/s2850/mptable.c
@@ -87,7 +87,7 @@ static void *smp_write_config_table(void *v)
#endif
apicid_8111 = apicid_base+0;
- smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
+ smp_write_ioapic(mc, apicid_8111, 0x11, VIO_APIC_VADDR);
mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
diff --git a/src/mainboard/tyan/s2875/mptable.c b/src/mainboard/tyan/s2875/mptable.c
index 90299a7..c8b12bd 100644
--- a/src/mainboard/tyan/s2875/mptable.c
+++ b/src/mainboard/tyan/s2875/mptable.c
@@ -104,7 +104,7 @@ static void *smp_write_config_table(void *v)
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
#endif
apicid_8111 = apicid_base+0;
- smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
+ smp_write_ioapic(mc, apicid_8111, 0x11, VIO_APIC_VADDR);
mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
diff --git a/src/mainboard/tyan/s2880/mptable.c b/src/mainboard/tyan/s2880/mptable.c
index 32fc639..10db9bb 100644
--- a/src/mainboard/tyan/s2880/mptable.c
+++ b/src/mainboard/tyan/s2880/mptable.c
@@ -117,7 +117,7 @@ static void *smp_write_config_table(void *v)
apicid_8111 = apicid_base+0;
apicid_8131_1 = apicid_base+1;
apicid_8131_2 = apicid_base+2;
- smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
+ smp_write_ioapic(mc, apicid_8111, 0x11, VIO_APIC_VADDR);
{
device_t dev;
@@ -126,14 +126,16 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_1, 0x11,
+ res2mmio(res, 0, 0));
}
}
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_2, 0x11,
+ res2mmio(res, 0, 0));
}
}
diff --git a/src/mainboard/tyan/s2881/mptable.c b/src/mainboard/tyan/s2881/mptable.c
index 7df5e87..8948b7c 100644
--- a/src/mainboard/tyan/s2881/mptable.c
+++ b/src/mainboard/tyan/s2881/mptable.c
@@ -33,7 +33,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
+ smp_write_ioapic(mc, apicid_8111, 0x11, VIO_APIC_VADDR);
{
device_t dev;
struct resource *res;
@@ -41,14 +41,16 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_1, 0x11,
+ res2mmio(res, 0, 0));
}
}
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_2, 0x11,
+ res2mmio(res, 0, 0));
}
}
diff --git a/src/mainboard/tyan/s2882/mptable.c b/src/mainboard/tyan/s2882/mptable.c
index 6c07965..d29c775 100644
--- a/src/mainboard/tyan/s2882/mptable.c
+++ b/src/mainboard/tyan/s2882/mptable.c
@@ -116,7 +116,7 @@ static void *smp_write_config_table(void *v)
apicid_8131_1 = apicid_base+1;
apicid_8131_2 = apicid_base+2;
- smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
+ smp_write_ioapic(mc, apicid_8111, 0x11, VIO_APIC_VADDR);
{
device_t dev;
struct resource *res;
@@ -124,14 +124,16 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_1, 0x11,
+ res2mmio(res, 0, 0));
}
}
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_2, 0x11,
+ res2mmio(res, 0, 0));
}
}
diff --git a/src/mainboard/tyan/s2885/mptable.c b/src/mainboard/tyan/s2885/mptable.c
index 26081c7..fe0f8d8 100644
--- a/src/mainboard/tyan/s2885/mptable.c
+++ b/src/mainboard/tyan/s2885/mptable.c
@@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); //8111
+ smp_write_ioapic(mc, apicid_8111, 0x11, VIO_APIC_VADDR); //8111
{
device_t dev;
struct resource *res;
@@ -44,14 +44,16 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_1, 0x11,
+ res2mmio(res, 0, 0));
}
}
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_2, 0x11,
+ res2mmio(res, 0, 0));
}
}
}
diff --git a/src/mainboard/tyan/s2891/mptable.c b/src/mainboard/tyan/s2891/mptable.c
index cb49434..a8f5157 100644
--- a/src/mainboard/tyan/s2891/mptable.c
+++ b/src/mainboard/tyan/s2891/mptable.c
@@ -47,7 +47,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_ck804, 0x11,
+ res2mmio(res, 0, 0));
}
/* Initialize interrupt mapping*/
@@ -67,14 +68,16 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_1, 0x11,
+ res2mmio(res, 0, 0));
}
}
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_2, 0x11,
+ res2mmio(res, 0, 0));
}
}
diff --git a/src/mainboard/tyan/s2892/mptable.c b/src/mainboard/tyan/s2892/mptable.c
index 882ac69..014e3f2 100644
--- a/src/mainboard/tyan/s2892/mptable.c
+++ b/src/mainboard/tyan/s2892/mptable.c
@@ -47,7 +47,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_ck804, 0x11,
+ res2mmio(res, 0, 0));
}
/* Initialize interrupt mapping*/
@@ -67,14 +68,16 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_1, 0x11,
+ res2mmio(res, 0, 0));
}
}
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_2, 0x11,
+ res2mmio(res, 0, 0));
}
}
diff --git a/src/mainboard/tyan/s2895/mptable.c b/src/mainboard/tyan/s2895/mptable.c
index 20fa92c..1abab1b 100644
--- a/src/mainboard/tyan/s2895/mptable.c
+++ b/src/mainboard/tyan/s2895/mptable.c
@@ -55,7 +55,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_ck804, 0x11,
+ res2mmio(res, 0, 0));
}
/* Initialize interrupt mapping*/
@@ -75,14 +76,16 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_1, 0x11,
+ res2mmio(res, 0, 0));
}
}
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_2, 0x11,
+ res2mmio(res, 0, 0));
}
}
@@ -91,7 +94,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, apicid_ck804b, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_ck804b, 0x11,
+ res2mmio(res, 0, 0));
}
dword = 0x0000d218; // Why does the factory BIOS have 0?
diff --git a/src/mainboard/tyan/s2912/mptable.c b/src/mainboard/tyan/s2912/mptable.c
index 133ce43..2163307 100644
--- a/src/mainboard/tyan/s2912/mptable.c
+++ b/src/mainboard/tyan/s2912/mptable.c
@@ -56,7 +56,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_mcp55, 0x11,
+ res2mmio(res, 0, 0));
}
dword = 0x43c6c643;
diff --git a/src/mainboard/tyan/s2912_fam10/mptable.c b/src/mainboard/tyan/s2912_fam10/mptable.c
index e15387d..b317303 100644
--- a/src/mainboard/tyan/s2912_fam10/mptable.c
+++ b/src/mainboard/tyan/s2912_fam10/mptable.c
@@ -56,7 +56,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_mcp55, 0x11,
+ res2mmio(res, 0, 0));
}
dword = 0x43c6c643;
diff --git a/src/mainboard/tyan/s4880/mptable.c b/src/mainboard/tyan/s4880/mptable.c
index dcc0fd8..b315c40 100644
--- a/src/mainboard/tyan/s4880/mptable.c
+++ b/src/mainboard/tyan/s4880/mptable.c
@@ -118,7 +118,7 @@ static void *smp_write_config_table(void *v)
apicid_8131_1 = apicid_base+1;
apicid_8131_2 = apicid_base+2;
- smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
+ smp_write_ioapic(mc, apicid_8111, 0x11, VIO_APIC_VADDR);
{
device_t dev;
struct resource *res;
@@ -126,14 +126,16 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_1, 0x11,
+ res2mmio(res, 0, 0));
}
}
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_2, 0x11,
+ res2mmio(res, 0, 0));
}
}
diff --git a/src/mainboard/tyan/s4882/mptable.c b/src/mainboard/tyan/s4882/mptable.c
index 350b55c..7bde349 100644
--- a/src/mainboard/tyan/s4882/mptable.c
+++ b/src/mainboard/tyan/s4882/mptable.c
@@ -117,7 +117,7 @@ static void *smp_write_config_table(void *v)
apicid_8111 = apicid_base+0;
apicid_8131_1 = apicid_base+1;
apicid_8131_2 = apicid_base+2;
- smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
+ smp_write_ioapic(mc, apicid_8111, 0x11, VIO_APIC_VADDR);
{
device_t dev;
struct resource *res;
@@ -125,14 +125,16 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_1, 0x11,
+ res2mmio(res, 0, 0));
}
}
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_2, 0x11,
+ res2mmio(res, 0, 0));
}
}
diff --git a/src/mainboard/tyan/s8226/mptable.c b/src/mainboard/tyan/s8226/mptable.c
index 5ec4a35..63ec044 100644
--- a/src/mainboard/tyan/s8226/mptable.c
+++ b/src/mainboard/tyan/s8226/mptable.c
@@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v)
u32 apicid_sp5100;
u32 apicid_sr5650;
device_t dev;
- u32 dword;
+ u32 *dword;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
if (dev) {
/* Set SP5100 IOAPIC ID */
- dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
+ dword = (u32 *)(pci_read_config32(dev, 0x74) & 0xfffffff0);
smp_write_ioapic(mc, apicid_sp5100, 0x20, dword);
#ifdef UNUSED_CODE
@@ -72,8 +72,8 @@ static void *smp_write_config_table(void *v)
pci_write_config8(dev, 0x63, byte);
/* SATA */
dword = pci_read_config32(dev, 0xAC);
- dword &= ~(7 << 26);
- dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
+ dword = dword & ~(7 << 26);
+ dword = dword | (6 << 26); /* 0: INTA, ...., 7: INTH */
/* dword |= 1<<22; PIC and APIC co exists */
pci_write_config32(dev, 0xAC, dword);
#endif
@@ -96,7 +96,7 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (dev) {
pci_write_config32(dev, 0xF8, 0x1);
- dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
+ dword = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
smp_write_ioapic(mc, apicid_sr5650, 0x20, dword);
}
diff --git a/src/mainboard/via/epia-m850/devicetree.cb b/src/mainboard/via/epia-m850/devicetree.cb
index 0c21cc8..aa2db2a 100644
--- a/src/mainboard/via/epia-m850/devicetree.cb
+++ b/src/mainboard/via/epia-m850/devicetree.cb
@@ -38,7 +38,7 @@ chip northbridge/via/vx900 # Northbridge
register "have_isa_interrupts" = "0"
register "irq_on_fsb" = "1"
register "enable_virtual_wire" = "1"
- register "base" = "0xfecc0000"
+ register "base" = "(void *)0xfecc0000"
device ioapic 2 on end
end
end
@@ -71,7 +71,7 @@ chip northbridge/via/vx900 # Northbridge
register "have_isa_interrupts" = "1"
register "irq_on_fsb" = "1"
register "enable_virtual_wire" = "1"
- register "base" = "0xfec00000"
+ register "base" = "(void *)0xfec00000"
device ioapic 1 on end
end
#chip drivers/generic/generic # DIMM 0 channel 1
diff --git a/src/mainboard/via/pc2500e/mptable.c b/src/mainboard/via/pc2500e/mptable.c
index f3f8186..da84ceb 100644
--- a/src/mainboard/via/pc2500e/mptable.c
+++ b/src/mainboard/via/pc2500e/mptable.c
@@ -43,7 +43,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VIO_APIC_VADDR);
/* Now, assemble the table. */
mptable_add_isa_interrupts(mc, isa_bus, VT8237R_APIC_ID, 0);
diff --git a/src/mainboard/via/vt8454c/mptable.c b/src/mainboard/via/vt8454c/mptable.c
index fc9cb99..c97701f 100644
--- a/src/mainboard/via/vt8454c/mptable.c
+++ b/src/mainboard/via/vt8454c/mptable.c
@@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 17, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 2, 17, VIO_APIC_VADDR);
mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
diff --git a/src/mainboard/winent/mb6047/mptable.c b/src/mainboard/winent/mb6047/mptable.c
index 26e79ca..1a5685f 100644
--- a/src/mainboard/winent/mb6047/mptable.c
+++ b/src/mainboard/winent/mb6047/mptable.c
@@ -41,7 +41,8 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_ck804, 0x11,
+ res2mmio(res, 0, 0));
}
/* Initialize interrupt mapping*/
diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c
index fa23344..9a73e63 100644
--- a/src/northbridge/amd/cimx/rd890/late.c
+++ b/src/northbridge/amd/cimx/rd890/late.c
@@ -119,10 +119,10 @@ struct chip_operations northbridge_amd_cimx_rd890_ops = {
static void ioapic_init(struct device *dev)
{
- u32 ioapic_base;
+ void *ioapic_base;
pci_write_config32(dev, 0xF8, 0x1);
- ioapic_base = pci_read_config32(dev, 0xFC) & 0xfffffff0;
+ ioapic_base = (void *)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
clear_ioapic(ioapic_base);
setup_ioapic(ioapic_base, 1);
}
diff --git a/src/northbridge/intel/e7501/raminit.c b/src/northbridge/intel/e7501/raminit.c
index 22d1bbc..f4fc9a8 100644
--- a/src/northbridge/intel/e7501/raminit.c
+++ b/src/northbridge/intel/e7501/raminit.c
@@ -44,7 +44,7 @@ Definitions:
// NOTE: This used to be 0x100000.
// That doesn't work on systems where A20M# is asserted, because
// attempts to access 0x1000NN end up accessing 0x0000NN.
-#define RCOMP_MMIO 0x200000
+#define RCOMP_MMIO ((u8 *)0x200000)
struct dimm_size {
unsigned long side1;
@@ -893,8 +893,8 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
// NOTE: 2^26 == 64 MB
- uint32_t dimm_start_address =
- dimm_start_64M_multiple << 26;
+ u8 *dimm_start_address = (u8 *)
+ (dimm_start_64M_multiple << 26);
RAM_DEBUG_MESSAGE(" Sending RAM command to 0x");
RAM_DEBUG_HEX32(dimm_start_address + e7501_mode_bits);
@@ -1704,7 +1704,7 @@ static void ram_set_d0f0_regs(void)
* @param src_addr TODO
* @param dst_addr TODO
*/
-static void write_8dwords(const uint32_t *src_addr, uint32_t dst_addr)
+static void write_8dwords(const uint32_t *src_addr, u8 *dst_addr)
{
int i;
for (i = 0; i < 8; i++) {
@@ -1737,7 +1737,8 @@ static void ram_set_rcomp_regs(void)
pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword);
// Set the RCOMP MMIO base address
- pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_SMRBASE, RCOMP_MMIO);
+ pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_SMRBASE,
+ (uintptr_t)RCOMP_MMIO);
// Block RCOMP updates while we configure the registers
dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index b758c61..fc715bc 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -63,7 +63,7 @@ Definitions:
// NOTE: This used to be 0x100000.
// That doesn't work on systems where A20M# is asserted, because
// attempts to access 0x1000NN end up accessing 0x0000NN.
-#define RCOMP_MMIO 0x200000
+#define RCOMP_MMIO ((u8 *)0x200000)
struct dimm_size {
unsigned long side1;
@@ -665,7 +665,7 @@ SDRAM configuration functions:
static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
{
uint8_t dimm_start_64M_multiple;
- uint32_t dimm_start_address;
+ uintptr_t dimm_start_address;
uint32_t dram_controller_mode;
uint8_t i;
@@ -713,7 +713,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
if (dimm_end_64M_multiple > dimm_start_64M_multiple) {
dimm_start_address &= 0x3ffffff;
dimm_start_address |= dimm_start_64M_multiple << 26;
- read32(dimm_start_address);
+ read32((void *)dimm_start_address);
// Set the start of the next DIMM
dimm_start_64M_multiple = dimm_end_64M_multiple;
}
@@ -1521,7 +1521,7 @@ static void RAM_RESET_DDR_PTR(void)
* @param src_addr TODO
* @param dst_addr TODO
*/
-static void write_8dwords(const uint32_t *src_addr, uint32_t dst_addr)
+static void write_8dwords(const uint32_t *src_addr, u8 *dst_addr)
{
int i;
for (i = 0; i < 8; i++) {
@@ -1627,7 +1627,7 @@ static void ram_set_rcomp_regs(void)
{
/* Set the RCOMP MMIO base address */
mchtest_control(RCOMP_BAR_ENABLE);
- pci_write_config32(MCHDEV, SMRBASE, RCOMP_MMIO);
+ pci_write_config32(MCHDEV, SMRBASE, (uintptr_t)RCOMP_MMIO);
/* Block RCOMP updates while we configure the registers */
rcomp_smr_control(RCOMP_HOLD);
diff --git a/src/northbridge/intel/fsp_sandybridge/acpi.c b/src/northbridge/intel/fsp_sandybridge/acpi.c
index a372e7b..bf23e65 100644
--- a/src/northbridge/intel/fsp_sandybridge/acpi.c
+++ b/src/northbridge/intel/fsp_sandybridge/acpi.c
@@ -120,7 +120,7 @@ static int init_opregion_vbt(igd_opregion_t *opregion)
optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios +
oprom->vbt_offset);
- if (read32((unsigned long)vbt->hdr_signature) != VBT_SIGNATURE) {
+ if (read32(vbt->hdr_signature) != VBT_SIGNATURE) {
printk(BIOS_DEBUG, "VBT not found!\n");
return 1;
}
diff --git a/src/northbridge/intel/fsp_sandybridge/early_init.c b/src/northbridge/intel/fsp_sandybridge/early_init.c
index 4b615e9..f86690d 100644
--- a/src/northbridge/intel/fsp_sandybridge/early_init.c
+++ b/src/northbridge/intel/fsp_sandybridge/early_init.c
@@ -32,12 +32,12 @@ static void sandybridge_setup_bars(void)
/* Set up all hardcoded northbridge BARs */
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32);
- pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+DEFAULT_MCHBAR) >> 32);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+(uintptr_t)DEFAULT_MCHBAR) >> 32);
pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */
pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR + 4, (0LL+DEFAULT_PCIEXBAR) >> 32);
- pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+DEFAULT_DMIBAR) >> 32);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32);
/* Set C0000-FFFFF to access RAM on both reads and writes */
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30);
diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.h b/src/northbridge/intel/fsp_sandybridge/northbridge.h
index d67d696..0432963 100644
--- a/src/northbridge/intel/fsp_sandybridge/northbridge.h
+++ b/src/northbridge/intel/fsp_sandybridge/northbridge.h
@@ -49,10 +49,15 @@
/* Northbridge BARs */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
+#ifndef __ACPI__
+#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */
+#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */
+#else
#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
+#endif
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
-#define DEFAULT_RCBABASE 0xfed1c000
+#define DEFAULT_RCBABASE ((u8 *)0xfed1c000)
#if CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X
#include <southbridge/intel/fsp_bd82x6x/pch.h>
diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c
index 335ef68..224dfce 100644
--- a/src/northbridge/intel/gm45/early_init.c
+++ b/src/northbridge/intel/gm45/early_init.c
@@ -26,10 +26,10 @@ void gm45_early_init(void)
const device_t d0f0 = PCI_DEV(0, 0, 0);
/* Setup MCHBAR. */
- pci_write_config32(d0f0, D0F0_MCHBAR_LO, DEFAULT_MCHBAR | 1);
+ pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1);
/* Setup DMIBAR. */
- pci_write_config32(d0f0, D0F0_DMIBAR_LO, DEFAULT_DMIBAR | 1);
+ pci_write_config32(d0f0, D0F0_DMIBAR_LO, (uintptr_t)DEFAULT_DMIBAR | 1);
/* Setup EPBAR. */
pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1);
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index 5bdf9e4..a31ea7d 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -187,10 +187,15 @@ enum {
(could be reduced to 10 bytes) */
+#ifndef __ACPI__
+#define DEFAULT_MCHBAR ((u8 *)0xfed14000)
+#define DEFAULT_DMIBAR ((u8 *)0xfed18000)
+#else
#define DEFAULT_MCHBAR 0xfed14000
#define DEFAULT_DMIBAR 0xfed18000
+#endif
#define DEFAULT_EPBAR 0xfed19000
-#define DEFAULT_HECIBAR 0xfed1a000
+#define DEFAULT_HECIBAR ((u8 *)0xfed1a000)
/* 4 KB per PCIe device */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index 74e16ad..4cf2776 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -43,12 +43,12 @@ static struct resource *gtt_res = NULL;
void gtt_write(u32 reg, u32 data)
{
- write32(gtt_res->base + reg, data);
+ write32(res2mmio(gtt_res, reg, 0), data);
}
#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
-static void power_port(u32 mmio)
+static void power_port(u8 *mmio)
{
read32(mmio + 0x00061100); // = 0x00000000
write32(mmio + 0x00061100, 0x00000000);
@@ -103,7 +103,7 @@ static void power_port(u32 mmio)
}
static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
- u32 mmio, u32 physbase, u16 piobase, u32 lfb)
+ u8 *mmio, u32 physbase, u16 piobase, u32 lfb)
{
int i;
@@ -464,8 +464,8 @@ static void gma_func0_init(struct device *dev)
&& lfb_res && lfb_res->base) {
printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n",
gtt_res->base);
- intel_gma_init(conf, gtt_res->base, physbase, pio_res->base,
- lfb_res->base);
+ intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase,
+ pio_res->base, lfb_res->base);
}
/* Linux relies on VBT for panel info. */
diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c
index 39791a6..ae34a11 100644
--- a/src/northbridge/intel/gm45/pcie.c
+++ b/src/northbridge/intel/gm45/pcie.c
@@ -308,7 +308,7 @@ static void setup_rcrb(const int peg_enabled)
/* Link1: component ID 1, link valid. */
EPBAR32(EPLE1D) = (EPBAR32(EPLE1D) & 0xff000000) | (1 << 16) | (1 << 0);
- EPBAR32(EPLE1A) = DEFAULT_DMIBAR;
+ EPBAR32(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR;
if (peg_enabled)
/* Link2: link_valid. */
@@ -322,12 +322,12 @@ static void setup_rcrb(const int peg_enabled)
/* Link1: target port 0, component id 2 (ICH), link valid. */
DMIBAR32(DMILE1D) = (0 << 24) | (2 << 16) | (1 << 0);
- DMIBAR32(DMILE1A) = DEFAULT_RCBA;
+ DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA;
/* Link2: component ID 1 (MCH), link valid */
DMIBAR32(DMILE2D) =
(DMIBAR32(DMILE2D) & 0xff000000) | (1 << 16) | (1 << 0);
- DMIBAR32(DMILE2A) = DEFAULT_MCHBAR;
+ DMIBAR32(DMILE2A) = (uintptr_t)DEFAULT_MCHBAR;
}
void gm45_late_init(const stepping_t stepping)
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index 60b05bd..2c810de 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -1579,15 +1579,15 @@ static void jedec_init(const timings_t *const timings,
const u32 rankaddr = raminit_get_rank_addr(ch, r);
printk(BIOS_DEBUG, "Performing Jedec initialization at address 0x%08x.\n", rankaddr);
MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(2);
- read32(rankaddr | WL);
+ read32((u32 *)(rankaddr | WL));
MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(3);
- read32(rankaddr);
+ read32((u32 *)rankaddr);
MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(1);
- read32(rankaddr | ODT_120OHMS | ODS_34OHMS);
+ read32((u32 *)(rankaddr | ODT_120OHMS | ODS_34OHMS));
MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_SET_MREG;
- read32(rankaddr | WR | DLL1 | CAS | INTERLEAVED);
+ read32((u32 *)(rankaddr | WR | DLL1 | CAS | INTERLEAVED));
MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_SET_MREG;
- read32(rankaddr | WR | CAS | INTERLEAVED);
+ read32((u32 *)(rankaddr | WR | CAS | INTERLEAVED));
}
}
@@ -1701,7 +1701,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
/* Wait for some bit, maybe TXT clear. */
if (sysinfo->txt_enabled) {
- while (!(read8(0xfed40000) & (1 << 7))) {}
+ while (!(read8((u8 *)0xfed40000) & (1 << 7))) {}
}
/* Enable SMBUS. */
diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c
index 5149c2b..b03cb33 100644
--- a/src/northbridge/intel/gm45/raminit_read_write_training.c
+++ b/src/northbridge/intel/gm45/raminit_read_write_training.c
@@ -114,7 +114,7 @@ static int read_training_test(const int channel, const int lane,
for (i = 0; i < addresses->count; ++i) {
unsigned int offset;
for (offset = lane_offset; offset < 320; offset += 8) {
- const u32 read = read32(addresses->addr[i] + offset);
+ const u32 read = read32((u32 *)(addresses->addr[i] + offset));
const u32 good = read_training_schedule[offset >> 3];
if ((read & lane_mask) != (good & lane_mask))
return 0;
@@ -228,7 +228,7 @@ static void perform_read_training(const dimminfo_t *const dimms)
/* Write test pattern. */
unsigned int offset;
for (offset = 0; offset < 320; offset += 4)
- write32(addresses.addr[i] + offset,
+ write32((u32 *)(addresses.addr[i] + offset),
read_training_schedule[offset >> 3]);
}
@@ -436,18 +436,18 @@ static int write_training_test(const address_bunch_t *const addresses,
unsigned int off;
for (off = 0; off < 640; off += 8) {
const u32 pattern = write_training_schedule[off >> 3];
- write32(addr + off, pattern);
- write32(addr + off + 4, pattern);
+ write32((u32 *)(addr + off), pattern);
+ write32((u32 *)(addr + off + 4), pattern);
}
MCHBAR8(0x78) |= 1;
for (off = 0; off < 640; off += 8) {
const u32 good = write_training_schedule[off >> 3];
- const u32 read1 = read32(addr + off);
+ const u32 read1 = read32((u32 *)(addr + off));
if ((read1 & masks[0]) != (good & masks[0]))
goto _bad_timing_out;
- const u32 read2 = read32(addr + off + 4);
+ const u32 read2 = read32((u32 *)(addr + off + 4));
if ((read2 & masks[1]) != (good & masks[1]))
goto _bad_timing_out;
}
diff --git a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
index 5130b59..62be05e 100644
--- a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
+++ b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
@@ -147,7 +147,7 @@ static int read_dqs_level(const int channel, const int lane)
MCHBAR32(mchbar) |= (1 << 9);
/* Read from this channel. */
- read32(raminit_get_rank_addr(channel, 0));
+ read32((u32 *)raminit_get_rank_addr(channel, 0));
mchbar = 0x14b0 + (channel * 0x0100) + ((7 - lane) * 4);
return MCHBAR32(mchbar) & (1 << 30);
diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c
index 488170d..1b77b64 100644
--- a/src/northbridge/intel/haswell/acpi.c
+++ b/src/northbridge/intel/haswell/acpi.c
@@ -118,7 +118,7 @@ static int init_opregion_vbt(igd_opregion_t *opregion)
optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios +
oprom->vbt_offset);
- if (read32((unsigned long)vbt->hdr_signature) != VBT_SIGNATURE) {
+ if (read32(vbt->hdr_signature) != VBT_SIGNATURE) {
printk(BIOS_DEBUG, "VBT not found!\n");
return 1;
}
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index 7f9f187..ef19984 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -34,8 +34,8 @@ static void haswell_setup_bars(void)
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32);
pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+DEFAULT_MCHBAR) >> 32);
- pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+DEFAULT_DMIBAR) >> 32);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32);
/* Set C0000-FFFFF to access RAM on both reads and writes */
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30);
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 325edbd..5d0e8e7 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -171,14 +171,14 @@ static struct resource *gtt_res = NULL;
u32 gtt_read(u32 reg)
{
u32 val;
- val = read32(gtt_res->base + reg);
+ val = read32(res2mmio(gtt_res, reg, 0));
return val;
}
void gtt_write(u32 reg, u32 data)
{
- write32(gtt_res->base + reg, data);
+ write32(res2mmio(gtt_res, reg, 0), data);
}
static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask)
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index d8221a9..b673f81 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -32,7 +32,11 @@
/* Northbridge BARs */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */
+#ifndef __ACPI__
+#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */
+#else
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
+#endif
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
#include <southbridge/intel/lynxpoint/pch.h>
diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c
index 4a38b28..f1b137e 100644
--- a/src/northbridge/intel/haswell/minihd.c
+++ b/src/northbridge/intel/haswell/minihd.c
@@ -67,7 +67,8 @@ static const u32 minihd_verb_table[] = {
static void minihd_init(struct device *dev)
{
struct resource *res;
- u32 base, reg32;
+ u32 reg32;
+ u8 *base;
int codec_mask, i;
/* Find base address */
@@ -75,8 +76,8 @@ static void minihd_init(struct device *dev)
if (!res)
return;
- base = (u32)res->base;
- printk(BIOS_DEBUG, "Mini-HD: base = %08x\n", (u32)base);
+ base = res2mmio(res, 0, 0);
+ printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base);
/* Set Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/northbridge/intel/i3100/i3100.h b/src/northbridge/intel/i3100/i3100.h
index 2d036bd..ac6f8c6 100644
--- a/src/northbridge/intel/i3100/i3100.h
+++ b/src/northbridge/intel/i3100/i3100.h
@@ -65,7 +65,7 @@
#define DRC_72BIT_ECC (1 << 20)
#define RCBA 0xF0
-#define DEFAULT_RCBA 0xFEA00000
+#define DEFAULT_RCBA ((u8 *)0xFEA00000)
int bios_reset_detected(void);
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index ebe137b..34d1eef 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -28,7 +28,7 @@
#include "i3100.h"
/* DDR2 memory controller register space */
-#define MCBAR 0x90000000
+#define MCBAR ((u8 *)(0x90000000))
static void sdram_set_registers(const struct mem_controller *ctrl)
{
@@ -61,7 +61,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1<<22)|(6<<2) | DEVPRES1_CONFIG,
/* 0x14 */
- PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, MCBAR |0,
+ PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, (uintptr_t)(MCBAR + 0),
};
int i;
int max;
@@ -936,6 +936,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
int i;
int cs;
int cnt;
+ u8 *cntptr;
int cas_latency;
long mask;
u32 drc;
@@ -1139,8 +1140,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* DQS */
pci_write_config32(ctrl->f0, 0x94, 0x3904aa00);
- for(i = 0, cnt = (MCBAR+0x200); i < 24; i++, cnt+=4) {
- write32(cnt, dqs_data[i]);
+ for(i = 0, cntptr = (MCBAR+0x200); i < 24; i++, cnt+=4) {
+ write32(cntptr, dqs_data[i]);
}
pci_write_config32(ctrl->f0, 0x94, 0x3900aa00);
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c
index b2858e4..77d4463 100644
--- a/src/northbridge/intel/i3100/raminit_ep80579.c
+++ b/src/northbridge/intel/i3100/raminit_ep80579.c
@@ -25,7 +25,7 @@
#include "raminit_ep80579.h"
#include "ep80579.h"
-#define BAR 0x90000000
+#define BAR ((u8 *)0x90000000)
static void sdram_set_registers(const struct mem_controller *ctrl)
{
@@ -35,7 +35,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000,
PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333,
PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffffffff, 0x0040003a,
- PCI_ADDR(0, 0x00, 0, SMRBASE), 0x00000fff, BAR | 0,
+ PCI_ADDR(0, 0x00, 0, SMRBASE), 0x00000fff, (uintptr_t)BAR | 0,
};
int i;
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index f191abe..bed2a51 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -387,7 +387,8 @@ static void do_ram_command(u32 command)
int i, caslatency;
u8 dimm_start, dimm_end;
u16 reg16;
- u32 addr, addr_offset;
+ void *addr;
+ u32 addr_offset;
/* Configure the RAM command. */
reg16 = pci_read_config16(NB, SDRAMC);
@@ -424,7 +425,7 @@ static void do_ram_command(u32 command)
dimm_end = pci_read_config8(NB, DRB + i);
- addr = (dimm_start * 8 * 1024 * 1024) + addr_offset;
+ addr = (void *)((dimm_start * 8 * 1024 * 1024) + addr_offset);
if (dimm_end > dimm_start) {
#if 0
PRINT_DEBUG(" Sending RAM command 0x%04x to 0x%08x\n",
diff --git a/src/northbridge/intel/i5000/raminit.h b/src/northbridge/intel/i5000/raminit.h
index aa14092..021e6fa 100644
--- a/src/northbridge/intel/i5000/raminit.h
+++ b/src/northbridge/intel/i5000/raminit.h
@@ -151,7 +151,7 @@
#define I5000_DMIR3 0x9c
#define I5000_DMIR4 0xa0
-#define DEFAULT_AMBASE 0xfe000000
+#define DEFAULT_AMBASE ((u8 *)0xfe000000)
/* AMB function 1 registers */
#define AMB_FBDSBCFGNXT 0x54
diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c
index b451803..dddfaa4 100644
--- a/src/northbridge/intel/i82810/raminit.c
+++ b/src/northbridge/intel/i82810/raminit.c
@@ -138,7 +138,7 @@ SDRAM configuration functions.
*/
static void do_ram_command(u8 command)
{
- u32 addr, addr_offset;
+ u32 *addr, addr_offset;
u16 dimm_size, dimm_start, dimm_bank;
u8 reg8, drp;
int i, caslatency;
@@ -191,15 +191,15 @@ static void do_ram_command(u8 command)
dimm_size = translate_i82810_to_mb[drp];
if (dimm_size) {
- addr = (dimm_start * 1024 * 1024) + addr_offset;
- PRINT_DEBUG(" Sending RAM command 0x%02x to 0x%08x\n", reg8, addr);
+ addr = (u32 *)((dimm_start * 1024 * 1024) + addr_offset);
+ PRINT_DEBUG(" Sending RAM command 0x%02x to 0x%p\n", reg8, addr);
read32(addr);
}
dimm_bank = translate_i82810_to_bank[drp];
if (dimm_bank) {
- addr = ((dimm_start + dimm_bank) * 1024 * 1024) + addr_offset;
- PRINT_DEBUG(" Sending RAM command 0x%02x to 0x%08x\n", reg8, addr);
+ addr = (u32 *)(((dimm_start + dimm_bank) * 1024 * 1024) + addr_offset);
+ PRINT_DEBUG(" Sending RAM command 0x%02x to 0x%p\n", reg8, addr);
read32(addr);
}
diff --git a/src/northbridge/intel/i82830/raminit.c b/src/northbridge/intel/i82830/raminit.c
index a42374c..bff59bf 100644
--- a/src/northbridge/intel/i82830/raminit.c
+++ b/src/northbridge/intel/i82830/raminit.c
@@ -77,15 +77,15 @@ static void ram_read32(u8 dimm_start, u32 offset)
{
u32 reg32, base_addr = 32 * 1024 * 1024 * dimm_start;
if (offset == 0x55aa55aa) {
- reg32 = read32(base_addr);
+ reg32 = read32((u32 *)base_addr);
PRINTK_DEBUG(" Reading RAM at 0x%08x => 0x%08x\n", base_addr, reg32);
PRINTK_DEBUG(" Writing RAM at 0x%08x <= 0x%08x\n", base_addr, offset);
- write32(base_addr, offset);
- reg32 = read32(base_addr);
+ write32((u32 *)base_addr, offset);
+ reg32 = read32((u32 *)base_addr);
PRINTK_DEBUG(" Reading RAM at 0x%08x => 0x%08x\n", base_addr, reg32);
} else {
PRINTK_DEBUG(" to 0x%08x\n", base_addr + offset);
- read32(base_addr + offset);
+ read32((u32 *)(base_addr + offset));
}
}
diff --git a/src/northbridge/intel/i82830/smihandler.c b/src/northbridge/intel/i82830/smihandler.c
index e4d93cf..b50c884 100644
--- a/src/northbridge/intel/i82830/smihandler.c
+++ b/src/northbridge/intel/i82830/smihandler.c
@@ -297,7 +297,7 @@ static void mbi_call(u8 subf, banner_id_t *banner_id)
static void smi_interface_call(void)
{
- u32 mmio = pci_read_config32(PCI_DEV(0, 0x02, 0), 0x14);
+ u8 *mmio = (u8 *)pci_read_config32(PCI_DEV(0, 0x02, 0), 0x14);
// mmio &= 0xfff80000;
// printk(BIOS_DEBUG, "mmio=%x\n", mmio);
u16 swsmi = pci_read_config16(PCI_DEV(0, 0x02, 0), 0xe0);
diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c
index 39e12d2..f0cc5a9 100644
--- a/src/northbridge/intel/i855/raminit.c
+++ b/src/northbridge/intel/i855/raminit.c
@@ -393,7 +393,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
uint32_t dimm_start_address = dimm_start_32M_multiple << 25;
PRINTK_DEBUG(" Sending RAM command to 0x%08x\n", dimm_start_address + i855_mode_bits);
- read32(dimm_start_address + i855_mode_bits);
+ read32((void *)(dimm_start_address + i855_mode_bits));
// Set the start of the next DIMM
dimm_start_32M_multiple = dimm_end_32M_multiple;
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 0b2acd7..776c051 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -156,7 +156,7 @@ static void i945_setup_bars(void)
/* Setting up Southbridge. In the northbridge code. */
printk(BIOS_DEBUG, "Setting up static southbridge registers...");
- pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
@@ -177,8 +177,8 @@ static void i945_setup_bars(void)
printk(BIOS_DEBUG, "Setting up static northbridge registers...");
/* Set up all hardcoded northbridge BARs */
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1);
/* Hardware default is 8MB UMA. If someone wants to make this a
@@ -342,7 +342,7 @@ static void ich7_setup_dmi_rcrb(void)
RCBA32(ULD) |= (1 << 24) | (1 << 16);
- RCBA32(ULBA) = DEFAULT_DMIBAR;
+ RCBA32(ULBA) = (uintptr_t)DEFAULT_DMIBAR;
RCBA32(RP1D) |= (2 << 16);
RCBA32(RP2D) |= (2 << 16);
@@ -818,7 +818,7 @@ static void i945_setup_root_complex_topology(void)
EPBAR32(EPLE1D) |= (1 << 16) | (1 << 0);
- EPBAR32(EPLE1A) = DEFAULT_DMIBAR;
+ EPBAR32(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR;
EPBAR32(EPLE2D) |= (1 << 16) | (1 << 0);
@@ -833,7 +833,7 @@ static void i945_setup_root_complex_topology(void)
reg32 |= (1 << 0);
DMIBAR32(DMILE1D) = reg32;
- DMIBAR32(DMILE1A) = DEFAULT_RCBA;
+ DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA;
DMIBAR32(DMILE2D) |= (1 << 16) | (1 << 0);
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index fe59ebe..7d02b37 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -23,8 +23,13 @@
/* Northbridge BARs */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
#define DEFAULT_X60BAR 0xfed13000
+#ifndef __ACPI__
+#define DEFAULT_MCHBAR ((u8 *)0xfed14000) /* 16 KB */
+#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */
+#else
#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
+#endif
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
#include "../../../southbridge/intel/i82801gx/i82801gx.h"
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 0a60112..c3f9bae 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -90,7 +90,7 @@ static void ram_read32(u32 offset)
{
PRINTK_DEBUG(" ram read: %08x\n", offset);
- read32(offset);
+ read32((void *)offset);
}
#if CONFIG_DEBUG_RAM_SETUP
diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c
index 88d6a00..6d429e4 100644
--- a/src/northbridge/intel/i945/rcven.c
+++ b/src/northbridge/intel/i945/rcven.c
@@ -42,8 +42,8 @@ static u32 sample_strobes(int channel_offset, struct sys_info *sysinfo)
}
for (i = 0; i < 28; i++) {
- read32(addr);
- read32(addr + 0x80);
+ read32((void *)addr);
+ read32((void *)(addr + 0x80));
}
reg32 = MCHBAR32(RCVENMT);
diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c
index 460942f..4a208ce 100644
--- a/src/northbridge/intel/nehalem/acpi.c
+++ b/src/northbridge/intel/nehalem/acpi.c
@@ -120,7 +120,7 @@ static int init_opregion_vbt(igd_opregion_t * opregion)
optionrom_header_t *oprom = (optionrom_header_t *) vbios;
optionrom_vbt_t *vbt = (optionrom_vbt_t *) (vbios + oprom->vbt_offset);
- if (read32((unsigned long)vbt->hdr_signature) != VBT_SIGNATURE) {
+ if (read32(vbt->hdr_signature) != VBT_SIGNATURE) {
printk(BIOS_DEBUG, "VBT not found!\n");
return 1;
}
diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c
index ee8c17a..56c0d68 100644
--- a/src/northbridge/intel/nehalem/early_init.c
+++ b/src/northbridge/intel/nehalem/early_init.c
@@ -36,7 +36,7 @@ static void nehalem_setup_bars(void)
{
/* Setting up Southbridge. In the northbridge code. */
printk(BIOS_DEBUG, "Setting up static southbridge registers...");
- pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
/* Enable ACPI BAR */
@@ -59,13 +59,13 @@ static void nehalem_setup_bars(void)
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4,
(0LL + DEFAULT_EPBAR) >> 32);
- pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4,
- (0LL + DEFAULT_MCHBAR) >> 32);
+ (0LL + (uintptr_t)DEFAULT_MCHBAR) >> 32);
- pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4,
- (0LL + DEFAULT_DMIBAR) >> 32);
+ (0LL + (uintptr_t)DEFAULT_DMIBAR) >> 32);
/* Set C0000-FFFFF to access RAM on both reads and writes */
pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(0), 0x30);
@@ -163,7 +163,7 @@ void nehalem_early_initialization(int chipset_type)
early_cpu_init();
- pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, DEFAULT_HECIBAR);
+ pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, (uintptr_t)DEFAULT_HECIBAR);
pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c
index c3e2a49..9fc4bd4 100644
--- a/src/northbridge/intel/nehalem/gma.c
+++ b/src/northbridge/intel/nehalem/gma.c
@@ -274,12 +274,12 @@ static struct resource *gtt_res = NULL;
u32 gtt_read(u32 reg)
{
- return read32(gtt_res->base + reg);
+ return read32(res2mmio(gtt_res, reg, 0));
}
void gtt_write(u32 reg, u32 data)
{
- write32(gtt_res->base + reg, data);
+ write32(res2mmio(gtt_res, reg, 0), data);
}
static inline void gtt_write_powermeter(const struct gt_powermeter *pm)
@@ -561,7 +561,7 @@ static void gma_pm_init_post_vbios(struct device *dev)
#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
-static void train_link(u32 mmio)
+static void train_link(u8 *mmio)
{
/* Clear interrupts. */
write32(mmio + DEIIR, 0xffffffff);
@@ -584,7 +584,7 @@ static void train_link(u32 mmio)
read32(mmio + 0x000f0014); // = 0x00000600
}
-static void power_port(u32 mmio)
+static void power_port(u8 *mmio)
{
read32(mmio + 0x000e1100); // = 0x00000000
write32(mmio + 0x000e1100, 0x00000000);
@@ -639,7 +639,7 @@ static void power_port(u32 mmio)
}
static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
- u32 mmio, u32 physbase, u16 piobase, u32 lfb)
+ u8 *mmio, u32 physbase, u16 piobase, u32 lfb)
{
int i;
u8 edid_data[128];
@@ -1020,8 +1020,8 @@ static void gma_func0_init(struct device *dev)
&& lfb_res && lfb_res->base) {
printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n",
gtt_res->base);
- intel_gma_init(conf, gtt_res->base, physbase, pio_res->base,
- lfb_res->base);
+ intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase,
+ pio_res->base, lfb_res->base);
}
/* Linux relies on VBT for panel info. */
diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h
index 73137b2..b90e5a9 100644
--- a/src/northbridge/intel/nehalem/nehalem.h
+++ b/src/northbridge/intel/nehalem/nehalem.h
@@ -186,7 +186,7 @@ enum {
(could be reduced to 10 bytes) */
-#define DEFAULT_HECIBAR 0xfed17000
+#define DEFAULT_HECIBAR ((u8 *)0xfed17000)
/* 4 KB per PCIe device */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS
@@ -454,10 +454,15 @@ void init_iommu(void);
/* Northbridge BARs */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
+#ifndef __ACPI__
+#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */
+#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */
+#else
#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
+#endif
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
-#define DEFAULT_RCBABASE 0xfed1c000
+#define DEFAULT_RCBABASE ((u8 *)0xfed1c000)
#define QUICKPATH_BUS 0xff
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 85c82c9..3917288 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -200,6 +200,16 @@ static u16 read_1d0(u16 addr, int split)
return val;
}
+static void write32p(uintptr_t addr, uint32_t val)
+{
+ write32((void *)addr, val);
+}
+
+static uint32_t read32p(uintptr_t addr)
+{
+ return read32((void *)addr);
+}
+
static void sfence(void)
{
#if REAL
@@ -314,36 +324,36 @@ static int rw_test(int rank)
int ok = 0xff;
int i;
for (i = 0; i < 64; i++)
- write32((rank << 28) | (i << 2), 0);
+ write32p((rank << 28) | (i << 2), 0);
sfence();
for (i = 0; i < 64; i++)
- gav(read32((rank << 28) | (i << 2)));
+ gav(read32p((rank << 28) | (i << 2)));
sfence();
for (i = 0; i < 32; i++) {
u32 pat = (((mask >> i) & 1) ? 0xffffffff : 0);
- write32((rank << 28) | (i << 3), pat);
- write32((rank << 28) | (i << 3) | 4, pat);
+ write32p((rank << 28) | (i << 3), pat);
+ write32p((rank << 28) | (i << 3) | 4, pat);
}
sfence();
for (i = 0; i < 32; i++) {
u8 pat = (((mask >> i) & 1) ? 0xff : 0);
int j;
u32 val;
- gav(val = read32((rank << 28) | (i << 3)));
+ gav(val = read32p((rank << 28) | (i << 3)));
for (j = 0; j < 4; j++)
if (((val >> (j * 8)) & 0xff) != pat)
ok &= ~(1 << j);
- gav(val = read32((rank << 28) | (i << 3) | 4));
+ gav(val = read32p((rank << 28) | (i << 3) | 4));
for (j = 0; j < 4; j++)
if (((val >> (j * 8)) & 0xff) != pat)
ok &= ~(16 << j);
}
sfence();
for (i = 0; i < 64; i++)
- write32((rank << 28) | (i << 2), 0);
+ write32p((rank << 28) | (i << 2), 0);
sfence();
for (i = 0; i < 64; i++)
- gav(read32((rank << 28) | (i << 2)));
+ gav(read32p((rank << 28) | (i << 2)));
return ok;
}
@@ -1072,12 +1082,12 @@ static void jedec_read(struct raminfo *info,
(value & ~0x1f8) | ((value >> 1) & 0xa8) | ((value & 0xa8)
<< 1);
- read32((value << 3) | (total_rank << 28));
+ read32p((value << 3) | (total_rank << 28));
write_mchbar8(0x271, (read_mchbar8(0x271) & 0xC3) | 2);
write_mchbar8(0x671, (read_mchbar8(0x671) & 0xC3) | 2);
- read32(total_rank << 28);
+ read32p(total_rank << 28);
}
enum {
@@ -1562,7 +1572,7 @@ static void collect_system_info(struct raminfo *info)
unsigned channel;
/* Wait for some bit, maybe TXT clear. */
- while (!(read8(0xfed40000) & (1 << 7))) ;
+ while (!(read8((u8 *)0xfed40000) & (1 << 7))) ;
if (!info->heci_bar)
gav(info->heci_bar =
@@ -1746,9 +1756,9 @@ static const struct ram_training *get_cached_training(void)
/* FIXME: add timeout. */
static void wait_heci_ready(void)
{
- while (!(read32(DEFAULT_HECIBAR | 0xc) & 8)) ; // = 0x8000000c
- write32((DEFAULT_HECIBAR | 0x4),
- (read32(DEFAULT_HECIBAR | 0x4) & ~0x10) | 0xc);
+ while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) ; // = 0x8000000c
+ write32((DEFAULT_HECIBAR + 0x4),
+ (read32(DEFAULT_HECIBAR + 0x4) & ~0x10) | 0xc);
}
/* FIXME: add timeout. */
@@ -1759,10 +1769,10 @@ static void wait_heci_cb_avail(int len)
u32 raw;
} csr;
- while (!(read32(DEFAULT_HECIBAR | 0xc) & 8)) ;
+ while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) ;
do
- csr.raw = read32(DEFAULT_HECIBAR | 0x4);
+ csr.raw = read32(DEFAULT_HECIBAR + 0x4);
while (len >
csr.csr.buffer_depth - (csr.csr.buffer_write_ptr -
csr.csr.buffer_read_ptr));
@@ -1776,12 +1786,12 @@ static void send_heci_packet(struct mei_header *head, u32 * payload)
wait_heci_cb_avail(len + 1);
/* FIXME: handle leftovers correctly. */
- write32(DEFAULT_HECIBAR | 0, *(u32 *) head);
+ write32(DEFAULT_HECIBAR + 0, *(u32 *) head);
for (i = 0; i < len - 1; i++)
- write32(DEFAULT_HECIBAR | 0, payload[i]);
+ write32(DEFAULT_HECIBAR + 0, payload[i]);
- write32(DEFAULT_HECIBAR | 0, payload[i] & ((1 << (8 * len)) - 1));
- write32(DEFAULT_HECIBAR | 0x4, read32(DEFAULT_HECIBAR | 0x4) | 0x4);
+ write32(DEFAULT_HECIBAR + 0, payload[i] & ((1 << (8 * len)) - 1));
+ write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 0x4);
}
static void
@@ -1791,7 +1801,7 @@ send_heci_message(u8 * msg, int len, u8 hostaddress, u8 clientaddress)
int maxlen;
wait_heci_ready();
- maxlen = (read32(DEFAULT_HECIBAR | 0x4) >> 24) * 4 - 4;
+ maxlen = (read32(DEFAULT_HECIBAR + 0x4) >> 24) * 4 - 4;
while (len) {
int cur = len;
@@ -1821,19 +1831,19 @@ recv_heci_packet(struct raminfo *info, struct mei_header *head, u32 * packet,
} csr;
int i = 0;
- write32(DEFAULT_HECIBAR | 0x4, read32(DEFAULT_HECIBAR | 0x4) | 2);
+ write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 2);
do {
- csr.raw = read32(DEFAULT_HECIBAR | 0xc);
+ csr.raw = read32(DEFAULT_HECIBAR + 0xc);
#if !REAL
if (i++ > 346)
return -1;
#endif
}
while (csr.csr.buffer_write_ptr == csr.csr.buffer_read_ptr);
- *(u32 *) head = read32(DEFAULT_HECIBAR | 0x8);
+ *(u32 *) head = read32(DEFAULT_HECIBAR + 0x8);
if (!head->length) {
- write32(DEFAULT_HECIBAR | 0x4,
- read32(DEFAULT_HECIBAR | 0x4) | 2);
+ write32(DEFAULT_HECIBAR + 0x4,
+ read32(DEFAULT_HECIBAR + 0x4) | 2);
*packet_size = 0;
return 0;
}
@@ -1844,16 +1854,16 @@ recv_heci_packet(struct raminfo *info, struct mei_header *head, u32 * packet,
}
do
- csr.raw = read32(DEFAULT_HECIBAR | 0xc);
+ csr.raw = read32(DEFAULT_HECIBAR + 0xc);
while ((head->length + 3) >> 2 >
csr.csr.buffer_write_ptr - csr.csr.buffer_read_ptr);
for (i = 0; i < (head->length + 3) >> 2; i++)
- packet[i++] = read32(DEFAULT_HECIBAR | 0x8);
+ packet[i++] = read32(DEFAULT_HECIBAR + 0x8);
*packet_size = head->length;
if (!csr.csr.ready)
*packet_size = 0;
- write32(DEFAULT_HECIBAR | 0x4, read32(DEFAULT_HECIBAR | 0x4) | 4);
+ write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 4);
return 0;
}
@@ -1941,27 +1951,27 @@ static void setup_heci_uma(struct raminfo *info)
pcie_read_config32(NORTHBRIDGE, DMIBAR);
if (info->memory_reserved_for_heci_mb) {
- write32(DEFAULT_DMIBAR | 0x14,
- read32(DEFAULT_DMIBAR | 0x14) & ~0x80);
- write32(DEFAULT_RCBA | 0x14,
- read32(DEFAULT_RCBA | 0x14) & ~0x80);
- write32(DEFAULT_DMIBAR | 0x20,
- read32(DEFAULT_DMIBAR | 0x20) & ~0x80);
- write32(DEFAULT_RCBA | 0x20,
- read32(DEFAULT_RCBA | 0x20) & ~0x80);
- write32(DEFAULT_DMIBAR | 0x2c,
- read32(DEFAULT_DMIBAR | 0x2c) & ~0x80);
- write32(DEFAULT_RCBA | 0x30,
- read32(DEFAULT_RCBA | 0x30) & ~0x80);
- write32(DEFAULT_DMIBAR | 0x38,
- read32(DEFAULT_DMIBAR | 0x38) & ~0x80);
- write32(DEFAULT_RCBA | 0x40,
- read32(DEFAULT_RCBA | 0x40) & ~0x80);
-
- write32(DEFAULT_RCBA | 0x40, 0x87000080); // OK
- write32(DEFAULT_DMIBAR | 0x38, 0x87000080); // OK
- while (read16(DEFAULT_RCBA | 0x46) & 2
- && read16(DEFAULT_DMIBAR | 0x3e) & 2) ;
+ write32(DEFAULT_DMIBAR + 0x14,
+ read32(DEFAULT_DMIBAR + 0x14) & ~0x80);
+ write32(DEFAULT_RCBA + 0x14,
+ read32(DEFAULT_RCBA + 0x14) & ~0x80);
+ write32(DEFAULT_DMIBAR + 0x20,
+ read32(DEFAULT_DMIBAR + 0x20) & ~0x80);
+ write32(DEFAULT_RCBA + 0x20,
+ read32(DEFAULT_RCBA + 0x20) & ~0x80);
+ write32(DEFAULT_DMIBAR + 0x2c,
+ read32(DEFAULT_DMIBAR + 0x2c) & ~0x80);
+ write32(DEFAULT_RCBA + 0x30,
+ read32(DEFAULT_RCBA + 0x30) & ~0x80);
+ write32(DEFAULT_DMIBAR + 0x38,
+ read32(DEFAULT_DMIBAR + 0x38) & ~0x80);
+ write32(DEFAULT_RCBA + 0x40,
+ read32(DEFAULT_RCBA + 0x40) & ~0x80);
+
+ write32(DEFAULT_RCBA + 0x40, 0x87000080); // OK
+ write32(DEFAULT_DMIBAR + 0x38, 0x87000080); // OK
+ while (read16(DEFAULT_RCBA + 0x46) & 2
+ && read16(DEFAULT_DMIBAR + 0x3e) & 2) ;
}
write_mchbar32(0x24, 0x10000 + info->memory_reserved_for_heci_mb);
@@ -2092,9 +2102,9 @@ static void write_testing(struct raminfo *info, int totalrank, int flip)
int nwrites = 0;
/* in 8-byte units. */
u32 offset;
- u32 base;
+ u8 *base;
- base = totalrank << 28;
+ base = (u8 *)(totalrank << 28);
for (offset = 0; offset < 9 * 480; offset += 2) {
write32(base + offset * 8, get_etalon2(flip, offset));
write32(base + offset * 8 + 4, get_etalon2(flip, offset));
@@ -2212,8 +2222,8 @@ write_testing_type2(struct raminfo *info, u8 totalrank, u8 region, u8 block,
{
int i;
for (i = 0; i < 2048; i++)
- write32((totalrank << 28) | (region << 25) | (block << 16) |
- (i << 2), get_etalon(flip, (block << 16) | (i << 2)));
+ write32p((totalrank << 28) | (region << 25) | (block << 16) |
+ (i << 2), get_etalon(flip, (block << 16) | (i << 2)));
}
static u8
@@ -2238,7 +2248,7 @@ check_testing_type2(struct raminfo *info, u8 totalrank, u8 region, u8 block,
| (comp3 << 12) | (comp2 << 6) | (comp1 <<
2);
failxor[comp1 & 1] |=
- read32(addr) ^ get_etalon(flip, addr);
+ read32p(addr) ^ get_etalon(flip, addr);
}
for (i = 0; i < 8; i++)
if ((0xff << (8 * (i % 4))) & failxor[i / 4])
@@ -3774,13 +3784,13 @@ static void restore_274265(struct raminfo *info)
#if REAL
static void dmi_setup(void)
{
- gav(read8(DEFAULT_DMIBAR | 0x254));
- write8(DEFAULT_DMIBAR | 0x254, 0x1);
- write16(DEFAULT_DMIBAR | 0x1b8, 0x18f2);
+ gav(read8(DEFAULT_DMIBAR + 0x254));
+ write8(DEFAULT_DMIBAR + 0x254, 0x1);
+ write16(DEFAULT_DMIBAR + 0x1b8, 0x18f2);
read_mchbar16(0x48);
write_mchbar16(0x48, 0x2);
- write32(DEFAULT_DMIBAR | 0xd68, read32(DEFAULT_DMIBAR | 0xd68) | 0x08000000);
+ write32(DEFAULT_DMIBAR + 0xd68, read32(DEFAULT_DMIBAR + 0xd68) | 0x08000000);
outl((gav(inl(DEFAULT_GPIOBASE | 0x38)) & ~0x140000) | 0x400000,
DEFAULT_GPIOBASE | 0x38);
@@ -3842,18 +3852,18 @@ void chipset_init(const int s3resume)
write_mchbar32(0x2c44, 0x1053687);
pcie_read_config8(GMA, 0x62); // = 0x2
pcie_write_config8(GMA, 0x62, 0x2);
- read8(DEFAULT_RCBA | 0x2318);
- write8(DEFAULT_RCBA | 0x2318, 0x47);
- read8(DEFAULT_RCBA | 0x2320);
- write8(DEFAULT_RCBA | 0x2320, 0xfc);
+ read8(DEFAULT_RCBA + 0x2318);
+ write8(DEFAULT_RCBA + 0x2318, 0x47);
+ read8(DEFAULT_RCBA + 0x2320);
+ write8(DEFAULT_RCBA + 0x2320, 0xfc);
}
read_mchbar32(0x30);
write_mchbar32(0x30, 0x40);
pcie_write_config16(NORTHBRIDGE, D0F0_GGC, ggc);
- gav(read32(DEFAULT_RCBA | 0x3428));
- write32(DEFAULT_RCBA | 0x3428, 0x1d);
+ gav(read32(DEFAULT_RCBA + 0x3428));
+ write32(DEFAULT_RCBA + 0x3428, 0x1d);
}
void raminit(const int s3resume, const u8 *spd_addrmap)
@@ -4813,17 +4823,17 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
write_mchbar32(0xd40, IOMMU_BASE1 | 1);
write_mchbar32(0xdc0, IOMMU_BASE4 | 1);
- write32(IOMMU_BASE1 | 0xffc, 0x80000000);
- write32(IOMMU_BASE2 | 0xffc, 0xc0000000);
- write32(IOMMU_BASE4 | 0xffc, 0x80000000);
+ write32p(IOMMU_BASE1 | 0xffc, 0x80000000);
+ write32p(IOMMU_BASE2 | 0xffc, 0xc0000000);
+ write32p(IOMMU_BASE4 | 0xffc, 0x80000000);
#else
{
u32 eax;
- eax = read32(0xffc + (read_mchbar32(0xd00) & ~1)) | 0x08000000; // = 0xe911714b// OK
- write32(0xffc + (read_mchbar32(0xd00) & ~1), eax); // OK
- eax = read32(0xffc + (read_mchbar32(0xdc0) & ~1)) | 0x40000000; // = 0xe911714b// OK
- write32(0xffc + (read_mchbar32(0xdc0) & ~1), eax); // OK
+ eax = read32p(0xffc + (read_mchbar32(0xd00) & ~1)) | 0x08000000; // = 0xe911714b// OK
+ write32p(0xffc + (read_mchbar32(0xd00) & ~1), eax); // OK
+ eax = read32p(0xffc + (read_mchbar32(0xdc0) & ~1)) | 0x40000000; // = 0xe911714b// OK
+ write32p(0xffc + (read_mchbar32(0xdc0) & ~1), eax); // OK
}
#endif
@@ -4870,9 +4880,9 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
}
u32 reg1c;
pcie_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK
- reg1c = read32(DEFAULT_EPBAR | 0x01c); // = 0x8001 // OK
+ reg1c = read32p(DEFAULT_EPBAR | 0x01c); // = 0x8001 // OK
pcie_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK
- write32(DEFAULT_EPBAR | 0x01c, reg1c); // OK
+ write32p(DEFAULT_EPBAR | 0x01c, reg1c); // OK
read_mchbar8(0xe08); // = 0x0
pcie_read_config32(NORTHBRIDGE, 0xe4); // = 0x316126
write_mchbar8(0x1210, read_mchbar8(0x1210) | 2); // OK
diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c
index 7a48696..71eb9df 100644
--- a/src/northbridge/intel/sandybridge/acpi.c
+++ b/src/northbridge/intel/sandybridge/acpi.c
@@ -121,7 +121,7 @@ static int init_opregion_vbt(igd_opregion_t *opregion)
optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios +
oprom->vbt_offset);
- if (read32((unsigned long)vbt->hdr_signature) != VBT_SIGNATURE) {
+ if (read32(vbt->hdr_signature) != VBT_SIGNATURE) {
printk(BIOS_DEBUG, "VBT not found!\n");
return 1;
}
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index 3156f86..d9ebe36 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -32,7 +32,7 @@ static void sandybridge_setup_bars(void)
{
/* Setting up Southbridge. In the northbridge code. */
printk(BIOS_DEBUG, "Setting up static southbridge registers...");
- pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
@@ -48,10 +48,10 @@ static void sandybridge_setup_bars(void)
/* Set up all hardcoded northbridge BARs */
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32);
- pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+DEFAULT_MCHBAR) >> 32);
- pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+DEFAULT_DMIBAR) >> 32);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+(uintptr_t)DEFAULT_MCHBAR) >> 32);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32);
/* Set C0000-FFFFF to access RAM on both reads and writes */
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30);
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index 247c723..554c0a5 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -280,12 +280,12 @@ static struct resource *gtt_res = NULL;
u32 gtt_read(u32 reg)
{
- return read32(gtt_res->base + reg);
+ return read32(res2mmio(gtt_res, reg, 0));
}
void gtt_write(u32 reg, u32 data)
{
- write32(gtt_res->base + reg, data);
+ write32(res2mmio(gtt_res, reg, 0), data);
}
static inline void gtt_write_powermeter(const struct gt_powermeter *pm)
@@ -588,10 +588,11 @@ static void gma_func0_init(struct device *dev)
#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
/* This should probably run before post VBIOS init. */
printk(BIOS_SPEW, "Initializing VGA without OPROM.\n");
- u32 iobase, mmiobase, physbase, graphics_base;
+ u8 *mmiobase;
+ u32 iobase, physbase, graphics_base;
struct northbridge_intel_sandybridge_config *conf = dev->chip_info;
iobase = dev->resource_list[2].base;
- mmiobase = dev->resource_list[0].base;
+ mmiobase = res2mmio(&dev->resource_list[0], 0, 0);
physbase = pci_read_config32(dev, 0x5c) & ~0xf;
graphics_base = dev->resource_list[1].base;
diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h
index 3a73e08..9854f21 100644
--- a/src/northbridge/intel/sandybridge/gma.h
+++ b/src/northbridge/intel/sandybridge/gma.h
@@ -117,4 +117,4 @@ typedef struct {
struct i915_gpu_controller_info;
int i915lightup_sandy(const struct i915_gpu_controller_info *info,
- u32 physbase, u16 pio, u32 mmio, u32 lfb);
+ u32 physbase, u16 pio, u8 *mmio, u32 lfb);
diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
index e3e1f4b..6c1295a 100644
--- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
@@ -36,7 +36,7 @@
#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
-static void link_train(u32 mmio)
+static void link_train(u8 *mmio)
{
write32(mmio+0xf000c,0x40);
write32(mmio+0x60100,0x40000);
@@ -54,7 +54,7 @@ static void link_train(u32 mmio)
write32(mmio+0x70008,0x80000050);
}
-static void link_normal_operation(u32 mmio)
+static void link_normal_operation(u8 *mmio)
{
write32(mmio + FDI_TX_CTL(0), 0x80044f02);
write32(mmio + FDI_RX_CTL(0),
@@ -62,7 +62,7 @@ static void link_normal_operation(u32 mmio)
| 0x2f50);
}
-static void enable_port(u32 mmio)
+static void enable_port(u8 *mmio)
{
write32(mmio + 0xec008, 0x2c010000);
write32(mmio + 0xec020, 0x2c010000);
@@ -160,7 +160,7 @@ static void enable_port(u32 mmio)
}
int i915lightup_sandy(const struct i915_gpu_controller_info *info,
- u32 physbase, u16 piobase, u32 mmio, u32 lfb)
+ u32 physbase, u16 piobase, u8 *mmio, u32 lfb)
{
int i;
u8 edid_data[128];
diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
index 08cceea..eb86c62 100644
--- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
@@ -35,7 +35,7 @@
#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
-static void train_link(u32 mmio)
+static void train_link(u8 *mmio)
{
/* Clear interrupts. */
write32(mmio + DEIIR, 0xffffffff);
@@ -68,7 +68,7 @@ static void train_link(u32 mmio)
read32(mmio + 0x000f0014); // = 0x00000600
}
-static void power_port(u32 mmio)
+static void power_port(u8 *mmio)
{
read32(mmio + 0x000e1100); // = 0x00000000
write32(mmio + 0x000e1100, 0x00000000);
@@ -123,7 +123,7 @@ static void power_port(u32 mmio)
}
int i915lightup_sandy(const struct i915_gpu_controller_info *info,
- u32 physbase, u16 piobase, u32 mmio, u32 lfb)
+ u32 physbase, u16 piobase, u8 *mmio, u32 lfb)
{
int i;
u8 edid_data[128];
diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c
index de6dac7..e892caa 100644
--- a/src/northbridge/intel/sandybridge/raminit_native.c
+++ b/src/northbridge/intel/sandybridge/raminit_native.c
@@ -181,10 +181,10 @@ static void wait_txt_clear(void)
if (!(cp.ecx & 0x40))
return;
/* Some TXT public bit. */
- if (!(read32(0xfed30010) & 1))
+ if (!(read32((void *)0xfed30010) & 1))
return;
/* Wait for TXT clear. */
- while (!(read8(0xfed40000) & (1 << 7))) ;
+ while (!(read8((void *)0xfed40000) & (1 << 7))) ;
}
static void sfence(void)
@@ -1105,7 +1105,7 @@ static void dram_ioregs(ramctr_timing * ctrl)
static void wait_428c(int channel)
{
while (1) {
- if (read32(DEFAULT_MCHBAR | 0x428c | (channel << 10)) & 0x50)
+ if (read32(DEFAULT_MCHBAR + 0x428c + (channel << 10)) & 0x50)
return;
}
}
@@ -2081,7 +2081,7 @@ static void fill_pattern0(ramctr_timing * ctrl, int channel, u32 a, u32 b)
get_precedening_channels(ctrl, channel) * 0x40;
printram("channel_offset=%x\n", channel_offset);
for (j = 0; j < 16; j++)
- write32(0x04000000 + channel_offset + 4 * j, j & 2 ? b : a);
+ write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a);
sfence();
}
@@ -2100,9 +2100,9 @@ static void fill_pattern1(ramctr_timing * ctrl, int channel)
get_precedening_channels(ctrl, channel) * 0x40;
unsigned channel_step = 0x40 * num_of_channels(ctrl);
for (j = 0; j < 16; j++)
- write32(0x04000000 + channel_offset + j * 4, 0xffffffff);
+ write32((void *)(0x04000000 + channel_offset + j * 4), 0xffffffff);
for (j = 0; j < 16; j++)
- write32(0x04000000 + channel_offset + channel_step + j * 4, 0);
+ write32((void *)(0x04000000 + channel_offset + channel_step + j * 4), 0);
sfence();
}
@@ -2298,7 +2298,7 @@ static void adjust_high_timB(ramctr_timing * ctrl)
write32(DEFAULT_MCHBAR + 0x3400, 0x200);
FOR_ALL_POPULATED_CHANNELS {
fill_pattern1(ctrl, channel);
- write32(DEFAULT_MCHBAR | 0x4288 | (channel << 10), 1);
+ write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 1);
}
FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS {
@@ -2489,7 +2489,7 @@ static void write_training(ramctr_timing * ctrl)
FOR_ALL_POPULATED_CHANNELS {
fill_pattern0(ctrl, channel, 0xaaaaaaaa, 0x55555555);
- write32(DEFAULT_MCHBAR | 0x4288 | (channel << 10), 0);
+ write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 0);
}
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS
@@ -2602,16 +2602,16 @@ static void fill_pattern5(ramctr_timing * ctrl, int channel, int patno)
u32 val = use_base[patno - 1][i] & (1 << (j / 2)) ? base : 0;
if (invert[patno - 1][i] & (1 << (j / 2)))
val = ~val;
- write32(0x04000000 + channel_offset + i * channel_step +
- j * 4, val);
+ write32((void *)(0x04000000 + channel_offset + i * channel_step +
+ j * 4), val);
}
}
} else {
for (i = 0; i < sizeof(pattern) / sizeof(pattern[0]); i++) {
for (j = 0; j < 16; j++)
- write32(0x04000000 + channel_offset + i * channel_step +
- j * 4, pattern[i][j]);
+ write32((void *)(0x04000000 + channel_offset + i * channel_step +
+ j * 4), pattern[i][j]);
}
sfence();
}
@@ -2866,7 +2866,7 @@ static void discover_edges(ramctr_timing * ctrl)
FOR_ALL_POPULATED_CHANNELS {
fill_pattern0(ctrl, channel, 0, 0);
- write32(DEFAULT_MCHBAR | 0x4288 | (channel << 10), 0);
+ write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 0);
FOR_ALL_LANES {
read32(DEFAULT_MCHBAR + 0x400 * channel +
lane * 4 + 0x4140);
@@ -2978,7 +2978,7 @@ static void discover_edges(ramctr_timing * ctrl)
}
fill_pattern0(ctrl, channel, 0, 0xffffffff);
- write32(DEFAULT_MCHBAR | 0x4288 | (channel << 10), 0);
+ write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 0);
}
/* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */
@@ -3335,9 +3335,9 @@ static void write_controller_mr(ramctr_timing * ctrl)
int channel, slotrank;
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
- write32(DEFAULT_MCHBAR | 0x0004 | (channel << 8) |
+ write32(DEFAULT_MCHBAR + 0x0004 + (channel << 8) +
lane_registers[slotrank], make_mr0(ctrl, slotrank));
- write32(DEFAULT_MCHBAR | 0x0008 | (channel << 8) |
+ write32(DEFAULT_MCHBAR + 0x0008 + (channel << 8) +
lane_registers[slotrank], make_mr1(ctrl, slotrank));
}
}
@@ -3347,46 +3347,46 @@ static void channel_test(ramctr_timing * ctrl)
int channel, slotrank, lane;
FOR_ALL_POPULATED_CHANNELS
- if (read32(DEFAULT_MCHBAR | 0x42a0 | (channel << 10)) & 0xa000)
+ if (read32(DEFAULT_MCHBAR + 0x42a0 + (channel << 10)) & 0xa000)
die("Mini channel test failed (1)\n");
FOR_ALL_POPULATED_CHANNELS {
fill_pattern0(ctrl, channel, 0x12345678, 0x98765432);
- write32(DEFAULT_MCHBAR | 0x4288 | (channel << 10), 0);
+ write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 0);
}
for (slotrank = 0; slotrank < 4; slotrank++)
FOR_ALL_CHANNELS
if (ctrl->rankmap[channel] & (1 << slotrank)) {
FOR_ALL_LANES {
- write32(DEFAULT_MCHBAR | (0x4f40 + 4 * lane), 0);
- write32(DEFAULT_MCHBAR | (0x4d40 + 4 * lane), 0);
+ write32(DEFAULT_MCHBAR + (0x4f40 + 4 * lane), 0);
+ write32(DEFAULT_MCHBAR + (0x4d40 + 4 * lane), 0);
}
wait_428c(channel);
- write32(DEFAULT_MCHBAR | 0x4220 | (channel << 10), 0x0001f006);
- write32(DEFAULT_MCHBAR | 0x4230 | (channel << 10), 0x0028a004);
- write32(DEFAULT_MCHBAR | 0x4200 | (channel << 10),
+ write32(DEFAULT_MCHBAR + 0x4220 + (channel << 10), 0x0001f006);
+ write32(DEFAULT_MCHBAR + 0x4230 + (channel << 10), 0x0028a004);
+ write32(DEFAULT_MCHBAR + 0x4200 + (channel << 10),
0x00060000 | (slotrank << 24));
- write32(DEFAULT_MCHBAR | 0x4210 | (channel << 10), 0x00000244);
- write32(DEFAULT_MCHBAR | 0x4224 | (channel << 10), 0x0001f201);
- write32(DEFAULT_MCHBAR | 0x4234 | (channel << 10), 0x08281064);
- write32(DEFAULT_MCHBAR | 0x4204 | (channel << 10),
+ write32(DEFAULT_MCHBAR + 0x4210 + (channel << 10), 0x00000244);
+ write32(DEFAULT_MCHBAR + 0x4224 + (channel << 10), 0x0001f201);
+ write32(DEFAULT_MCHBAR + 0x4234 + (channel << 10), 0x08281064);
+ write32(DEFAULT_MCHBAR + 0x4204 + (channel << 10),
0x00000000 | (slotrank << 24));
- write32(DEFAULT_MCHBAR | 0x4214 | (channel << 10), 0x00000242);
- write32(DEFAULT_MCHBAR | 0x4228 | (channel << 10), 0x0001f105);
- write32(DEFAULT_MCHBAR | 0x4238 | (channel << 10), 0x04281064);
- write32(DEFAULT_MCHBAR | 0x4208 | (channel << 10),
+ write32(DEFAULT_MCHBAR + 0x4214 + (channel << 10), 0x00000242);
+ write32(DEFAULT_MCHBAR + 0x4228 + (channel << 10), 0x0001f105);
+ write32(DEFAULT_MCHBAR + 0x4238 + (channel << 10), 0x04281064);
+ write32(DEFAULT_MCHBAR + 0x4208 + (channel << 10),
0x00000000 | (slotrank << 24));
- write32(DEFAULT_MCHBAR | 0x4218 | (channel << 10), 0x00000242);
- write32(DEFAULT_MCHBAR | 0x422c | (channel << 10), 0x0001f002);
- write32(DEFAULT_MCHBAR | 0x423c | (channel << 10), 0x00280c01);
- write32(DEFAULT_MCHBAR | 0x420c | (channel << 10),
+ write32(DEFAULT_MCHBAR + 0x4218 + (channel << 10), 0x00000242);
+ write32(DEFAULT_MCHBAR + 0x422c + (channel << 10), 0x0001f002);
+ write32(DEFAULT_MCHBAR + 0x423c + (channel << 10), 0x00280c01);
+ write32(DEFAULT_MCHBAR + 0x420c + (channel << 10),
0x00060400 | (slotrank << 24));
- write32(DEFAULT_MCHBAR | 0x421c | (channel << 10), 0x00000240);
- write32(DEFAULT_MCHBAR | 0x4284 | (channel << 10), 0x000c0001);
+ write32(DEFAULT_MCHBAR + 0x421c + (channel << 10), 0x00000240);
+ write32(DEFAULT_MCHBAR + 0x4284 + (channel << 10), 0x000c0001);
wait_428c(channel);
FOR_ALL_LANES
- if (read32(DEFAULT_MCHBAR | 0x4340 | (channel << 10)))
+ if (read32(DEFAULT_MCHBAR + 0x4340 + (channel << 10)))
die("Mini channel test failed (2)\n");
}
}
@@ -3403,9 +3403,9 @@ static void set_scrambling_seed(ramctr_timing * ctrl)
};
FOR_ALL_POPULATED_CHANNELS {
MCHBAR32(0x4020 + 0x400 * channel) &= ~0x10000000;
- write32(DEFAULT_MCHBAR | 0x4034, seeds[channel][0]);
- write32(DEFAULT_MCHBAR | 0x403c, seeds[channel][1]);
- write32(DEFAULT_MCHBAR | 0x4038, seeds[channel][2]);
+ write32(DEFAULT_MCHBAR + 0x4034, seeds[channel][0]);
+ write32(DEFAULT_MCHBAR + 0x403c, seeds[channel][1]);
+ write32(DEFAULT_MCHBAR + 0x4038, seeds[channel][2]);
}
}
@@ -3463,12 +3463,12 @@ static void set_4008c(ramctr_timing * ctrl)
else
b4_8_12 = 0x2220;
- reg = read32(DEFAULT_MCHBAR | 0x400c | (channel << 10));
- write32(DEFAULT_MCHBAR | 0x400c | (channel << 10),
+ reg = read32(DEFAULT_MCHBAR + 0x400c + (channel << 10));
+ write32(DEFAULT_MCHBAR + 0x400c + (channel << 10),
(reg & 0xFFF0FFFF)
| (ctrl->ref_card_offset[channel] << 16)
| (ctrl->ref_card_offset[channel] << 18));
- write32(DEFAULT_MCHBAR | 0x4008 | (channel << 10),
+ write32(DEFAULT_MCHBAR + 0x4008 + (channel << 10),
0x0a000000
| (b20 << 20)
| ((ctrl->ref_card_offset[channel] + 2) << 16)
@@ -3480,7 +3480,7 @@ static void set_42a0(ramctr_timing * ctrl)
{
int channel;
FOR_ALL_POPULATED_CHANNELS {
- write32(DEFAULT_MCHBAR | (0x42a0 + 0x400 * channel),
+ write32(DEFAULT_MCHBAR + (0x42a0 + 0x400 * channel),
0x00001000 | ctrl->rankmap[channel]);
MCHBAR32(0x4004 + 0x400 * channel) &= ~0x20000000; // OK
}
@@ -3499,15 +3499,15 @@ static void final_registers(ramctr_timing * ctrl)
int t3_ns;
u32 r32;
- write32(DEFAULT_MCHBAR | 0x4cd4, 0x00000046);
+ write32(DEFAULT_MCHBAR + 0x4cd4, 0x00000046);
- write32(DEFAULT_MCHBAR | 0x400c, (read32(DEFAULT_MCHBAR | 0x400c) & 0xFFFFCFFF) | 0x1000); // OK
- write32(DEFAULT_MCHBAR | 0x440c, (read32(DEFAULT_MCHBAR | 0x440c) & 0xFFFFCFFF) | 0x1000); // OK
- write32(DEFAULT_MCHBAR | 0x4cb0, 0x00000740);
- write32(DEFAULT_MCHBAR | 0x4380, 0x00000aaa); // OK
- write32(DEFAULT_MCHBAR | 0x4780, 0x00000aaa); // OK
- write32(DEFAULT_MCHBAR | 0x4f88, 0x5f7003ff); // OK
- write32(DEFAULT_MCHBAR | 0x5064, 0x00073000 | ctrl->reg_5064b0); // OK
+ write32(DEFAULT_MCHBAR + 0x400c, (read32(DEFAULT_MCHBAR + 0x400c) & 0xFFFFCFFF) | 0x1000); // OK
+ write32(DEFAULT_MCHBAR + 0x440c, (read32(DEFAULT_MCHBAR + 0x440c) & 0xFFFFCFFF) | 0x1000); // OK
+ write32(DEFAULT_MCHBAR + 0x4cb0, 0x00000740);
+ write32(DEFAULT_MCHBAR + 0x4380, 0x00000aaa); // OK
+ write32(DEFAULT_MCHBAR + 0x4780, 0x00000aaa); // OK
+ write32(DEFAULT_MCHBAR + 0x4f88, 0x5f7003ff); // OK
+ write32(DEFAULT_MCHBAR + 0x5064, 0x00073000 | ctrl->reg_5064b0); // OK
FOR_ALL_CHANNELS {
switch (ctrl->rankmap[channel]) {
@@ -3528,15 +3528,15 @@ static void final_registers(ramctr_timing * ctrl)
}
}
- write32 (DEFAULT_MCHBAR | 0x5880, 0xca9171e5);
- write32 (DEFAULT_MCHBAR | 0x5888,
- (read32 (DEFAULT_MCHBAR | 0x5888) & ~0xffffff) | 0xe4d5d0);
- write32 (DEFAULT_MCHBAR | 0x58a8, read32 (DEFAULT_MCHBAR | 0x58a8) & ~0x1f);
- write32 (DEFAULT_MCHBAR | 0x4294,
- (read32 (DEFAULT_MCHBAR | 0x4294) & ~0x30000)
+ write32 (DEFAULT_MCHBAR + 0x5880, 0xca9171e5);
+ write32 (DEFAULT_MCHBAR + 0x5888,
+ (read32 (DEFAULT_MCHBAR + 0x5888) & ~0xffffff) | 0xe4d5d0);
+ write32 (DEFAULT_MCHBAR + 0x58a8, read32 (DEFAULT_MCHBAR + 0x58a8) & ~0x1f);
+ write32 (DEFAULT_MCHBAR + 0x4294,
+ (read32 (DEFAULT_MCHBAR + 0x4294) & ~0x30000)
| (1 << 16));
- write32 (DEFAULT_MCHBAR | 0x4694,
- (read32 (DEFAULT_MCHBAR | 0x4694) & ~0x30000)
+ write32 (DEFAULT_MCHBAR + 0x4694,
+ (read32 (DEFAULT_MCHBAR + 0x4694) & ~0x30000)
| (1 << 16));
MCHBAR32(0x5030) |= 1; // OK
@@ -3721,10 +3721,10 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck,
wrmsr(0x000002e6, (msr_t) { .lo = 0, .hi = 0 });
- reg_5d10 = read32(DEFAULT_MCHBAR | 0x5d10); // !!! = 0x00000000
+ reg_5d10 = read32(DEFAULT_MCHBAR + 0x5d10); // !!! = 0x00000000
if ((pcie_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 /* 0x0004 */
&& reg_5d10 && !s3resume) {
- write32(DEFAULT_MCHBAR | 0x5d10, 0);
+ write32(DEFAULT_MCHBAR + 0x5d10, 0);
/* Need reset. */
outb(0x6, 0xcf9);
@@ -3858,7 +3858,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck,
}
/* FIXME: should be hardware revision-dependent. */
- write32(DEFAULT_MCHBAR | 0x5024, 0x00a030ce);
+ write32(DEFAULT_MCHBAR + 0x5024, 0x00a030ce);
set_scrambling_seed(&ctrl);
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 0790ae8..ab95572 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -48,10 +48,15 @@
/* Northbridge BARs */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
+#ifndef __ACPI__
+#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */
+#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */
+#else
#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
+#endif
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
-#define DEFAULT_RCBABASE 0xfed1c000
+#define DEFAULT_RCBABASE ((u8 *)0xfed1c000)
#include <southbridge/intel/bd82x6x/pch.h>
diff --git a/src/northbridge/intel/sch/early_init.c b/src/northbridge/intel/sch/early_init.c
index d80cc21..0c206bd 100644
--- a/src/northbridge/intel/sch/early_init.c
+++ b/src/northbridge/intel/sch/early_init.c
@@ -205,7 +205,8 @@ static void sch_setup_non_standard_bars(void)
sch_port_access_write(2, 9, 4, DEFAULT_PCIEXBAR | 1); /* b1+ */
/* RCBA */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xF0, (DEFAULT_RCBABASE | 1));
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xF0,
+ ((uintptr_t)DEFAULT_RCBABASE | 1));
printk(BIOS_DEBUG, " done.\n");
}
diff --git a/src/northbridge/intel/sch/sch.h b/src/northbridge/intel/sch/sch.h
index 3eb0825..9ac79ea 100644
--- a/src/northbridge/intel/sch/sch.h
+++ b/src/northbridge/intel/sch/sch.h
@@ -36,7 +36,7 @@ void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data);
#define DEFAULT_GPE0BASE 0x5C0
#define DEFAULT_SMMCNTRLBASE 0x3F703F76
-#define DEFAULT_RCBABASE 0xfed1c000
+#define DEFAULT_RCBABASE ((u8 *)0xfed1c000)
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c
index 747cbfd..289b315 100644
--- a/src/northbridge/via/cn700/raminit.c
+++ b/src/northbridge/via/cn700/raminit.c
@@ -393,7 +393,7 @@ static void sdram_set_post(const struct mem_controller *ctrl)
pci_write_config16(dev, 0xa4, 0x0010);
}
-static void sdram_enable(device_t dev, unsigned long rank_address)
+static void sdram_enable(device_t dev, u8 *rank_address)
{
u8 i;
@@ -413,7 +413,7 @@ static void sdram_enable(device_t dev, unsigned long rank_address)
PRINT_DEBUG_MEM("RAM Enable 3: Mode register set\n");
do_ram_command(dev, RAM_COMMAND_MRS);
read32(rank_address + 0x120000); /* EMRS DLL Enable */
- read32(rank_address + 0x800); /* MRS DLL Reset */
+ read32(rank_address + 0x800); /* MRS DLL Reset */
/* 4. Precharge all again. */
PRINT_DEBUG_MEM("RAM Enable 4: Precharge all\n");
@@ -457,10 +457,10 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
c7_cpu_setup(ctrl->d0f2);
sdram_set_registers(ctrl);
sdram_set_size(ctrl);
- sdram_enable(ctrl->d0f3, 0);
+ sdram_enable(ctrl->d0f3, (u8 *)0);
reg = pci_read_config8(ctrl->d0f3, 0x41);
if (reg != 0)
sdram_enable(ctrl->d0f3,
- pci_read_config8(ctrl->d0f3, 0x40) << 26);
+ (u8 *)(pci_read_config8(ctrl->d0f3, 0x40) << 26));
sdram_set_post(ctrl);
}
diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c
index 1e6d2ce..56842b0 100644
--- a/src/northbridge/via/cx700/lpc.c
+++ b/src/northbridge/via/cx700/lpc.c
@@ -274,7 +274,7 @@ static void cx700_lpc_init(struct device *dev)
#if CONFIG_IOAPIC
#define IO_APIC_ID 2
- setup_ioapic(IO_APIC_ADDR, IO_APIC_ID);
+ setup_ioapic(VIO_APIC_VADDR, IO_APIC_ID);
#endif
/* Initialize interrupts */
diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c
index 32be1ea..fabd7ff 100644
--- a/src/northbridge/via/cx700/raminit.c
+++ b/src/northbridge/via/cx700/raminit.c
@@ -967,9 +967,9 @@ static void step_20_21(const struct mem_controller *ctrl)
val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_NB_ODT);
if (val & DDR2_ODT_150ohm)
- read32(0x102200);
+ read32((void *)0x102200);
else
- read32(0x102020);
+ read32((void *)0x102020);
/* Step 21. Normal operation */
printk(BIOS_SPEW, "RAM Enable 5: Normal operation\n");
@@ -995,7 +995,7 @@ static void step_2_19(const struct mem_controller *ctrl)
// Step 4
printk(BIOS_SPEW, "SEND: ");
- read32(0);
+ read32((void *)0);
printk(BIOS_SPEW, "OK\n");
// Step 5
@@ -1007,7 +1007,7 @@ static void step_2_19(const struct mem_controller *ctrl)
// Step 7
printk(BIOS_SPEW, "SEND: ");
- read32(0);
+ read32((void *)0);
printk(BIOS_SPEW, "OK\n");
/* Step 8. Mode register set. */
@@ -1019,14 +1019,14 @@ static void step_2_19(const struct mem_controller *ctrl)
val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_NB_ODT);
if (val & DDR2_ODT_150ohm)
- read32(0x102200); //DDR2_ODT_150ohm
+ read32((void *)0x102200); //DDR2_ODT_150ohm
else
- read32(0x102020);
+ read32((void *)0x102020);
printk(BIOS_SPEW, "OK\n");
// Step 10
printk(BIOS_SPEW, "SEND: ");
- read32(0x800);
+ read32((void *)0x800);
printk(BIOS_SPEW, "OK\n");
/* Step 11. Precharge all. Wait tRP. */
@@ -1035,7 +1035,7 @@ static void step_2_19(const struct mem_controller *ctrl)
// Step 12
printk(BIOS_SPEW, "SEND: ");
- read32(0x0);
+ read32((u32 *)0x0);
printk(BIOS_SPEW, "OK\n");
/* Step 13. Perform 8 refresh cycles. Wait tRC each time. */
@@ -1046,7 +1046,7 @@ static void step_2_19(const struct mem_controller *ctrl)
// Step 16: Repeat Step 14 and 15 another 7 times
for (i = 0; i < 8; i++) {
// Step 14
- read32(0);
+ read32((u32 *)0);
printk(BIOS_SPEW, ".");
// Step 15
@@ -1076,7 +1076,7 @@ static void step_2_19(const struct mem_controller *ctrl)
val = pci_read_config8(MEMCTRL, 0x61);
val = val >> 6;
i |= DDR2_Twr_table[val];
- read32(i);
+ read32((void *)i);
printk(BIOS_DEBUG, "MRS = %08x\n", i);
@@ -1085,9 +1085,9 @@ static void step_2_19(const struct mem_controller *ctrl)
// Step 19
val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_NB_ODT);
if (val & DDR2_ODT_150ohm)
- read32(0x103e00); //EMRS OCD Default
+ read32((void *)0x103e00); //EMRS OCD Default
else
- read32(0x103c20);
+ read32((void *)0x103c20);
}
static void sdram_set_vr(const struct mem_controller *ctrl, u8 num)
@@ -1133,45 +1133,45 @@ static void sdram_calc_size(const struct mem_controller *ctrl, u8 num)
u8 ca, ra, ba, reg;
ba = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_FLAGS);
if (ba == 8) {
- write8(0, 0x0d);
- ra = read8(0);
- write8((1 << SDRAM1X_RA_12_8bk), 0x0c);
- ra = read8(0);
-
- write8(0, 0x0a);
- ca = read8(0);
- write8((1 << SDRAM1X_CA_09_8bk), 0x0c);
- ca = read8(0);
-
- write8(0, 0x03);
- ba = read8(0);
- write8((1 << SDRAM1X_BA2_8bk), 0x02);
- ba = read8(0);
- write8((1 << SDRAM1X_BA1_8bk), 0x01);
- ba = read8(0);
+ write8((void *)0, 0x0d);
+ ra = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_RA_12_8bk), 0x0c);
+ ra = read8((void *)0);
+
+ write8((void *)0, 0x0a);
+ ca = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_CA_09_8bk), 0x0c);
+ ca = read8((void *)0);
+
+ write8((void *)0, 0x03);
+ ba = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_BA2_8bk), 0x02);
+ ba = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_BA1_8bk), 0x01);
+ ba = read8((void *)0);
} else {
- write8(0, 0x0f);
- ra = read8(0);
- write8((1 << SDRAM1X_RA_14), 0x0e);
- ra = read8(0);
- write8((1 << SDRAM1X_RA_13), 0x0d);
- ra = read8(0);
- write8((1 << SDRAM1X_RA_12), 0x0c);
- ra = read8(0);
-
- write8(0, 0x0c);
- ca = read8(0);
- write8((1 << SDRAM1X_CA_12), 0x0b);
- ca = read8(0);
- write8((1 << SDRAM1X_CA_11), 0x0a);
- ca = read8(0);
- write8((1 << SDRAM1X_CA_09), 0x09);
- ca = read8(0);
-
- write8(0, 0x02);
- ba = read8(0);
- write8((1 << SDRAM1X_BA1), 0x01);
- ba = read8(0);
+ write8((void *)0, 0x0f);
+ ra = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_RA_14), 0x0e);
+ ra = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_RA_13), 0x0d);
+ ra = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_RA_12), 0x0c);
+ ra = read8((void *)0);
+
+ write8((void *)0, 0x0c);
+ ca = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_CA_12), 0x0b);
+ ca = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_CA_11), 0x0a);
+ ca = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_CA_09), 0x09);
+ ca = read8((void *)0);
+
+ write8((void *)0, 0x02);
+ ba = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_BA1), 0x01);
+ ba = read8((void *)0);
}
if (ra < 10 || ra > 15)
@@ -1277,19 +1277,19 @@ static void sdram_enable(const struct mem_controller *ctrl)
if (reg8) {
sdram_set_vr(ctrl, i);
sdram_ending_addr(ctrl, i);
- write32(0, 0x55555555);
- write32(4, 0x55555555);
+ write32((void *)0, 0x55555555);
+ write32((void *)4, 0x55555555);
udelay(15);
- if (read32(0) != 0x55555555)
+ if (read32((void *)0) != 0x55555555)
break;
- if (read32(4) != 0x55555555)
+ if (read32((void *)4) != 0x55555555)
break;
- write32(0, 0xaaaaaaaa);
- write32(4, 0xaaaaaaaa);
+ write32((void *)0, 0xaaaaaaaa);
+ write32((void *)4, 0xaaaaaaaa);
udelay(15);
- if (read32(0) != 0xaaaaaaaa)
+ if (read32((void *)0) != 0xaaaaaaaa)
break;
- if (read32(4) != 0xaaaaaaaa)
+ if (read32((void *)4) != 0xaaaaaaaa)
break;
sdram_clear_vr_addr(ctrl, i);
}
@@ -1310,19 +1310,19 @@ static void sdram_enable(const struct mem_controller *ctrl)
sdram_set_vr(ctrl, i);
sdram_ending_addr(ctrl, i);
- write32(0, 0x55555555);
- write32(4, 0x55555555);
+ write32((void *)0, 0x55555555);
+ write32((void *)4, 0x55555555);
udelay(15);
- if (read32(0) != 0x55555555)
+ if (read32((void *)0) != 0x55555555)
break;
- if (read32(4) != 0x55555555)
+ if (read32((void *)4) != 0x55555555)
break;
- write32(0, 0xaaaaaaaa);
- write32(4, 0xaaaaaaaa);
+ write32((void *)0, 0xaaaaaaaa);
+ write32((void *)4, 0xaaaaaaaa);
udelay(15);
- if (read32(0) != 0xaaaaaaaa)
+ if (read32((void *)0) != 0xaaaaaaaa)
break;
- if (read32(4) != 0xaaaaaaaa)
+ if (read32((void *)4) != 0xaaaaaaaa)
break;
sdram_clear_vr_addr(ctrl, i);
}
@@ -1364,17 +1364,17 @@ static void sdram_enable(const struct mem_controller *ctrl)
sdram_set_vr(ctrl, i);
sdram_ending_addr(ctrl, i);
if (reg8 == 4) {
- write8(0, 0x02);
- val = read8(0);
- write8((1 << SDRAM1X_BA1), 0x01);
- val = read8(0);
+ write8((void *)0, 0x02);
+ val = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_BA1), 0x01);
+ val = read8((void *)0);
} else {
- write8(0, 0x03);
- val = read8(0);
- write8((1 << SDRAM1X_BA2_8bk), 0x02);
- val = read8(0);
- write8((1 << SDRAM1X_BA1_8bk), 0x01);
- val = read8(0);
+ write8((void *)0, 0x03);
+ val = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_BA2_8bk), 0x02);
+ val = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_BA1_8bk), 0x01);
+ val = read8((void *)0);
}
if (val < dl)
dl = val;
diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c
index 3cff6b0..61a8a7b 100644
--- a/src/northbridge/via/vx900/lpc.c
+++ b/src/northbridge/via/vx900/lpc.c
@@ -139,10 +139,10 @@ static void vx900_lpc_ioapic_setup(device_t dev)
/* The base address of this IOAPIC _must_ be at 0xfec00000.
* Don't move this value to a #define, as people might think it's
* configurable. It is not. */
- const u32 base = config->base;
- if (base != 0xfec00000) {
+ const void *base = config->base;
+ if (base != (void *)0xfec00000) {
printk(BIOS_ERR, "ERROR: South module IOAPIC base should be at "
- "0xfec00000\n but we found it at 0x%.8x\n", base);
+ "0xfec00000\n but we found it at %p\n", base);
return;
}
diff --git a/src/northbridge/via/vx900/traf_ctrl.c b/src/northbridge/via/vx900/traf_ctrl.c
index 5183391..fb15193 100644
--- a/src/northbridge/via/vx900/traf_ctrl.c
+++ b/src/northbridge/via/vx900/traf_ctrl.c
@@ -80,24 +80,24 @@ static void vx900_north_ioapic_setup(device_t dev)
* be between 0xfec00000 and 0xfecfff00
* be 256-byte aligned
*/
- if ((config->base < 0xfec0000 || config->base > 0xfecfff00)
- || ((config->base & 0xff) != 0)) {
+ if ((config->base < (void *)0xfec0000 || config->base > (void *)0xfecfff00)
+ || (((uintptr_t)config->base & 0xff) != 0)) {
printk(BIOS_ERR, "ERROR: North module IOAPIC base should be "
"between 0xfec00000 and 0xfecfff00\n"
"and must be aligned to a 256-byte boundary, "
- "but we found it at 0x%.8x\n", config->base);
+ "but we found it at 0x%p\n", config->base);
return;
}
printk(BIOS_DEBUG, "VX900 TRAF_CTR: Setting up the north module IOAPIC "
- "at 0%.8x\n", config->base);
+ "at %p\n", config->base);
/* First register of the IOAPIC base */
- base_val = (config->base >> 8) & 0xff;
+ base_val = (((uintptr_t)config->base) >> 8) & 0xff;
pci_write_config8(dev, 0x41, base_val);
/* Second register of the base.
* Bit[7] also enables the IOAPIC and bit[5] enables MSI cycles */
- base_val = (config->base >> 16) & 0xf;
+ base_val = (((uintptr_t)config->base) >> 16) & 0xf;
pci_mod_config8(dev, 0x40, 0, base_val | (1 << 7) | (1 << 5));
}
diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c
index aae0c99..cefc215 100644
--- a/src/soc/intel/baytrail/acpi.c
+++ b/src/soc/intel/baytrail/acpi.c
@@ -106,7 +106,7 @@ void acpi_init_gnvs(global_nvs_t *gnvs)
static int acpi_sci_irq(void)
{
- const unsigned long actl = ILB_BASE_ADDRESS + ACTL;
+ u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL);
int scis;
static int sci_irq;
diff --git a/src/soc/intel/baytrail/baytrail/gpio.h b/src/soc/intel/baytrail/baytrail/gpio.h
index 5071b09..d51d6e2 100644
--- a/src/soc/intel/baytrail/baytrail/gpio.h
+++ b/src/soc/intel/baytrail/baytrail/gpio.h
@@ -387,15 +387,15 @@ struct soc_gpio_config* mainboard_get_gpios(void);
#define PCU_SMB_DATA_PAD 90
#define SOC_DDI1_VDDEN_PAD 16
-static inline unsigned int ncore_pconf0(int pad_num)
+static inline u32 *ncore_pconf0(int pad_num)
{
- return GPNCORE_PAD_BASE + pad_num * 16;
+ return (u32 *)(GPNCORE_PAD_BASE + pad_num * 16);
}
static inline void ncore_select_func(int pad, int func)
{
uint32_t reg;
- uint32_t pconf0_addr = ncore_pconf0(pad);
+ u32 *pconf0_addr = ncore_pconf0(pad);
reg = read32(pconf0_addr);
reg &= ~0x7;
@@ -403,20 +403,20 @@ static inline void ncore_select_func(int pad, int func)
write32(pconf0_addr, reg);
}
-static inline unsigned int score_pconf0(int pad_num)
+static inline u32 *score_pconf0(int pad_num)
{
- return GPSCORE_PAD_BASE + pad_num * 16;
+ return (u32 *)(GPSCORE_PAD_BASE + pad_num * 16);
}
-static inline unsigned int ssus_pconf0(int pad_num)
+static inline u32 *ssus_pconf0(int pad_num)
{
- return GPSSUS_PAD_BASE + pad_num * 16;
+ return (u32 *)(GPSSUS_PAD_BASE + pad_num * 16);
}
static inline void score_select_func(int pad, int func)
{
uint32_t reg;
- uint32_t pconf0_addr = score_pconf0(pad);
+ uint32_t *pconf0_addr = score_pconf0(pad);
reg = read32(pconf0_addr);
reg &= ~0x7;
@@ -427,7 +427,7 @@ static inline void score_select_func(int pad, int func)
static inline void ssus_select_func(int pad, int func)
{
uint32_t reg;
- uint32_t pconf0_addr = ssus_pconf0(pad);
+ uint32_t *pconf0_addr = ssus_pconf0(pad);
reg = read32(pconf0_addr);
reg &= ~0x7;
@@ -438,14 +438,14 @@ static inline void ssus_select_func(int pad, int func)
/* These functions require that the input pad be configured as an input GPIO */
static inline int score_get_gpio(int pad)
{
- uint32_t val_addr = score_pconf0(pad) + PAD_VAL_REG;
+ uint32_t *val_addr = score_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t));
return read32(val_addr) & PAD_VAL_HIGH;
}
static inline int ssus_get_gpio(int pad)
{
- uint32_t val_addr = ssus_pconf0(pad) + PAD_VAL_REG;
+ uint32_t *val_addr = ssus_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t));
return read32(val_addr) & PAD_VAL_HIGH;
}
diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c
index 4cce877..5b57cc3 100644
--- a/src/soc/intel/baytrail/gfx.c
+++ b/src/soc/intel/baytrail/gfx.c
@@ -59,7 +59,7 @@ static void gfx_lock_pcbase(device_t dev)
pcbase += (gmsize-1) * wopcmsz - pcsize;
pcbase |= 1; /* Lock */
- write32(res->base + 0x182120, pcbase);
+ write32((u32 *)(uintptr_t)(res->base + 0x182120), pcbase);
}
static const struct reg_script gfx_init_script[] = {
@@ -308,7 +308,7 @@ static void set_backlight_pwm(device_t dev, uint32_t bklt_reg, int req_hz)
divider = 25 * 1000 * 1000 / (16 * req_hz);
/* Do not set duty cycle (lower 16 bits). Just set the divider. */
- write32(res->base + bklt_reg, divider << 16);
+ write32((u32 *)(uintptr_t)(res->base + bklt_reg), divider << 16);
}
static void gfx_panel_setup(device_t dev)
diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c
index 43e52ef..6a971ea 100644
--- a/src/soc/intel/baytrail/gpio.c
+++ b/src/soc/intel/baytrail/gpio.c
@@ -142,9 +142,9 @@ static void setup_gpios(const struct soc_gpio_map *gpios,
reg, pad_conf0, config->pad_conf1, config->pad_val);
#endif
- write32(reg + PAD_CONF0_REG, pad_conf0);
- write32(reg + PAD_CONF1_REG, config->pad_conf1);
- write32(reg + PAD_VAL_REG, config->pad_val);
+ write32((u32 *)(reg + PAD_CONF0_REG), pad_conf0);
+ write32((u32 *)(reg + PAD_CONF1_REG), config->pad_conf1);
+ write32((u32 *)(reg + PAD_VAL_REG), config->pad_val);
}
if (bank->legacy_base != GP_LEGACY_BASE_NONE)
@@ -198,7 +198,7 @@ static void setup_gpio_route(const struct soc_gpio_map *sus,
static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],
const struct gpio_bank *bank)
{
- u32 reg = bank->pad_base + PAD_BASE_DIRQ_OFFSET;
+ u32 *reg = (u32 *)(bank->pad_base + PAD_BASE_DIRQ_OFFSET);
u32 val;
int i;
@@ -206,10 +206,10 @@ static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],
for (i=0; i<4; ++i) {
val = dirq[i * 4 + 3] << 24 | dirq[i * 4 + 2] << 16 |
dirq[i * 4 + 1] << 8 | dirq[i * 4];
- write32(reg + i * 4, val);
+ write32(reg + i, val);
#ifdef GPIO_DEBUG
printk(BIOS_DEBUG, "Write DIRQ reg(%x) - %x\n",
- reg + i * 4, val);
+ reg + i, val);
#endif
}
}
@@ -233,8 +233,8 @@ void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap)
*/
if (!enable_xdp_tap) {
printk(BIOS_DEBUG, "Tri-state TDO and TMS\n");
- write32(GPSSUS_PAD_BASE + 0x2fc, 0xc);
- write32(GPSSUS_PAD_BASE + 0x2cc, 0xc);
+ write32((u32 *)(GPSSUS_PAD_BASE + 0x2fc), 0xc);
+ write32((u32 *)(GPSSUS_PAD_BASE + 0x2cc), 0xc);
}
}
diff --git a/src/soc/intel/baytrail/hda.c b/src/soc/intel/baytrail/hda.c
index c5de654..010150f 100644
--- a/src/soc/intel/baytrail/hda.c
+++ b/src/soc/intel/baytrail/hda.c
@@ -83,6 +83,7 @@ static void hda_init(device_t dev)
struct resource *res;
int codec_mask;
int i;
+ u8 *base;
reg_script_run_on_dev(dev, init_ops);
@@ -90,7 +91,8 @@ static void hda_init(device_t dev)
if (res == NULL)
return;
- codec_mask = hda_codec_detect(res->base);
+ base = res2mmio(res, 0, 0);
+ codec_mask = hda_codec_detect(base);
printk(BIOS_DEBUG, "codec mask = %x\n", codec_mask);
if (!codec_mask)
@@ -99,7 +101,7 @@ static void hda_init(device_t dev)
for (i = 3; i >= 0; i--) {
if (!((1 << i) & codec_mask))
continue;
- hda_codec_init(res->base, i, sizeof(hdmi_codec_verb_table),
+ hda_codec_init(base, i, sizeof(hdmi_codec_verb_table),
hdmi_codec_verb_table);
}
}
diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c
index 2b07e2b..0834f4b 100644
--- a/src/soc/intel/baytrail/iosf.c
+++ b/src/soc/intel/baytrail/iosf.c
@@ -25,11 +25,11 @@
static inline void write_iosf_reg(int reg, uint32_t value)
{
- write32(IOSF_PCI_BASE + reg, value);
+ write32((u32 *)(IOSF_PCI_BASE + reg), value);
}
static inline uint32_t read_iosf_reg(int reg)
{
- return read32(IOSF_PCI_BASE + reg);
+ return read32((u32 *)(IOSF_PCI_BASE + reg));
}
#else
static inline void write_iosf_reg(int reg, uint32_t value)
diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c
index 581f42b..bc467ea 100644
--- a/src/soc/intel/baytrail/lpe.c
+++ b/src/soc/intel/baytrail/lpe.c
@@ -90,7 +90,7 @@ static void lpe_enable_acpi_mode(device_t dev)
static void setup_codec_clock(device_t dev)
{
uint32_t reg;
- int clk_reg;
+ u32 *clk_reg;
struct soc_intel_baytrail_config *config;
const char *freq_str;
@@ -119,8 +119,8 @@ static void setup_codec_clock(device_t dev)
printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str);
- clk_reg = PMC_BASE_ADDRESS + PLT_CLK_CTL_0;
- clk_reg += 4 * config->lpe_codec_clk_num;
+ clk_reg = (u32 *)(PMC_BASE_ADDRESS + PLT_CLK_CTL_0);
+ clk_reg += config->lpe_codec_clk_num;
write32(clk_reg, (read32(clk_reg) & ~0x7) | reg);
}
@@ -144,8 +144,10 @@ static void lpe_stash_firmware_info(device_t dev)
/* C0 and later steppings use an offset in the MMIO space. */
if (pattrs->stepping >= STEP_C0) {
mmio = find_resource(dev, PCI_BASE_ADDRESS_0);
- write32(mmio->base + FIRMWARE_REG_BASE_C0, res->base);
- write32(mmio->base + FIRMWARE_REG_LENGTH_C0, res->size);
+ write32((u32 *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0),
+ res->base);
+ write32((u32 *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0),
+ res->size);
}
}
diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c
index aee3726..8295b69 100644
--- a/src/soc/intel/baytrail/pmutil.c
+++ b/src/soc/intel/baytrail/pmutil.c
@@ -355,10 +355,10 @@ void clear_pmc_status(void)
uint32_t prsts;
uint32_t gen_pmcon1;
- prsts = read32(PMC_BASE_ADDRESS + PRSTS);
- gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
+ prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS));
+ gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1));
/* Clear the status bits. The RPS field is cleared on a 0 write. */
- write32(PMC_BASE_ADDRESS + GEN_PMCON1, gen_pmcon1 & ~RPS);
- write32(PMC_BASE_ADDRESS + PRSTS, prsts);
+ write32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS);
+ write32((u32 *)(PMC_BASE_ADDRESS + PRSTS), prsts);
}
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index ac5afab..2065733 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -84,8 +84,8 @@ static void program_base_addresses(void)
static void spi_init(void)
{
- const unsigned long scs = SPI_BASE_ADDRESS + SCS;
- const unsigned long bcr = SPI_BASE_ADDRESS + BCR;
+ u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS);
+ u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR);
uint32_t reg;
/* Disable generating SMI when setting WPD bit. */
@@ -176,9 +176,9 @@ static struct chipset_power_state *fill_power_state(void)
ps->gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS);
ps->gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN);
ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS);
- ps->prsts = read32(PMC_BASE_ADDRESS + PRSTS);
- ps->gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
- ps->gen_pmcon2 = read32(PMC_BASE_ADDRESS + GEN_PMCON2);
+ ps->prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS));
+ ps->gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1));
+ ps->gen_pmcon2 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2));
printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
ps->pm1_sts, ps->pm1_en, ps->pm1_cnt);
diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c
index 28a2f8c..bed57c7 100644
--- a/src/soc/intel/baytrail/sata.c
+++ b/src/soc/intel/baytrail/sata.c
@@ -92,7 +92,7 @@ static void sata_init(struct device *dev)
pci_write_config16(dev, 0x92, reg16);
if (config->sata_ahci) {
- u32 abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+ u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
/* Enable CR memory space decoding */
reg16 = pci_read_config16(dev, 0x04);
diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c
index daf759d..9349dfa 100644
--- a/src/soc/intel/baytrail/smm.c
+++ b/src/soc/intel/baytrail/smm.c
@@ -66,7 +66,7 @@ void southcluster_smm_clear_state(void)
static void southcluster_smm_route_gpios(void)
{
- const unsigned long gpio_rout = PMC_BASE_ADDRESS + GPIO_ROUT;
+ u32 *gpio_rout = (u32 *)(PMC_BASE_ADDRESS + GPIO_ROUT);
const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI;
uint32_t alt_gpio_reg = 0;
uint32_t route_reg = smm_save_params[SMM_SAVE_PARAM_GPIO_ROUTE];
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index 5274b03..d0569b4 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -134,7 +134,7 @@ static void sc_rtc_init(void)
if (ps != NULL) {
gen_pmcon1 = ps->gen_pmcon1;
} else {
- gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
+ gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1));
}
rtc_fail = !!(gen_pmcon1 & RPS);
@@ -185,20 +185,20 @@ static void com1_configure_resume(device_t dev)
static void sc_init(device_t dev)
{
int i;
- const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08;
- const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20;
- const unsigned long gen_pmcon1 = PMC_BASE_ADDRESS + GEN_PMCON1;
- const unsigned long actl = ILB_BASE_ADDRESS + ACTL;
+ u8 *pr_base = (u8 *)(ILB_BASE_ADDRESS + 0x08);
+ u16 *ir_base = (u16 *)ILB_BASE_ADDRESS + 0x20;
+ u32 *gen_pmcon1 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1);
+ u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL);
const struct baytrail_irq_route *ir = &global_baytrail_irq_route;
struct soc_intel_baytrail_config *config = dev->chip_info;
/* Set up the PIRQ PIC routing based on static config. */
for (i = 0; i < NUM_PIRQS; i++) {
- write8(pr_base + i*sizeof(ir->pic[i]), ir->pic[i]);
+ write8(pr_base + i, ir->pic[i]);
}
/* Set up the per device PIRQ routing base on static config. */
for (i = 0; i < NUM_IR_DEVS; i++) {
- write16(ir_base + i*sizeof(ir->pcidev[i]), ir->pcidev[i]);
+ write16(ir_base + i, ir->pcidev[i]);
}
/* Route SCI to IRQ9 */
@@ -226,8 +226,8 @@ static void sc_init(device_t dev)
/* Set bit in function disable register to hide this device. */
static void sc_disable_devfn(device_t dev)
{
- const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS;
- const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2;
+ u32 *func_dis = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS);
+ u32 *func_dis2 = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS2);
uint32_t mask = 0;
uint32_t mask2 = 0;
@@ -347,7 +347,7 @@ static inline void set_d3hot_bits(device_t dev, int offset)
* the audio paths work for LPE audio. */
static void hda_work_around(device_t dev)
{
- unsigned long gctl = TEMP_BASE_ADDRESS + 0x8;
+ u32 *gctl = (u32 *)(TEMP_BASE_ADDRESS + 0x8);
/* Need to set magic register 0x43 to 0xd7 in config space. */
pci_write_config8(dev, 0x43, 0xd7);
@@ -534,11 +534,11 @@ int __attribute__((weak)) mainboard_get_spi_config(struct spi_config *cfg)
static void finalize_chipset(void *unused)
{
- const unsigned long bcr = SPI_BASE_ADDRESS + BCR;
- const unsigned long gcs = RCBA_BASE_ADDRESS + GCS;
- const unsigned long gen_pmcon2 = PMC_BASE_ADDRESS + GEN_PMCON2;
- const unsigned long etr = PMC_BASE_ADDRESS + ETR;
- const unsigned long spi = SPI_BASE_ADDRESS;
+ u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR);
+ u32 *gcs = (u32 *)(RCBA_BASE_ADDRESS + GCS);
+ u32 *gen_pmcon2 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2);
+ u32 *etr = (u32 *)(PMC_BASE_ADDRESS + ETR);
+ u8 *spi = (u8 *)SPI_BASE_ADDRESS;
struct spi_config cfg;
/* Set the lock enable on the BIOS control register. */
diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c
index 8605dfc..a83fb8e 100644
--- a/src/soc/intel/baytrail/spi.c
+++ b/src/soc/intel/baytrail/spi.c
@@ -196,33 +196,33 @@ static u32 readl_(const void *addr)
static void writeb_(u8 b, const void *addr)
{
- write8((unsigned long)addr, b);
+ write8(addr, b);
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writew_(u16 b, const void *addr)
{
- write16((unsigned long)addr, b);
+ write16(addr, b);
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writel_(u32 b, const void *addr)
{
- write32((unsigned long)addr, b);
+ write32(addr, b);
printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
-#define readb_(a) read8((uint32_t)a)
-#define readw_(a) read16((uint32_t)a)
-#define readl_(a) read32((uint32_t)a)
-#define writeb_(val, addr) write8((uint32_t)addr, val)
-#define writew_(val, addr) write16((uint32_t)addr, val)
-#define writel_(val, addr) write32((uint32_t)addr, val)
+#define readb_(a) read8(a)
+#define readw_(a) read16(a)
+#define readl_(a) read32(a)
+#define writeb_(val, addr) write8(addr, val)
+#define writew_(val, addr) write16(addr, val)
+#define writel_(val, addr) write32(addr, val)
#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c
index 2a6dc17..4137215 100644
--- a/src/soc/intel/broadwell/adsp.c
+++ b/src/soc/intel/broadwell/adsp.c
@@ -58,7 +58,8 @@ static void adsp_init(struct device *dev)
* SNOOP_REQ[13]=1b SNOOP_SCALE[12:10]=100b (1ms) SNOOP_VAL[9:0]=3h
*/
tmp32 = pch_is_wpt() ? ADSP_SHIM_BASE_WPT : ADSP_SHIM_BASE_LPT;
- write32(bar0->base + tmp32 + ADSP_SHIM_LTRC, ADSP_SHIM_LTRC_VALUE);
+ write32(res2mmio(bar0, tmp32 + ADSP_SHIM_LTRC, 0),
+ ADSP_SHIM_LTRC_VALUE);
/* Program VDRTCTL2 D19:F0:A8[31:0] = 0x00000fff */
pci_write_config32(dev, ADSP_PCI_VDRTCTL2, ADSP_VDRTCTL2_VALUE);
@@ -115,9 +116,9 @@ static void adsp_init(struct device *dev)
ADSP_PCICFGCTL_ACPIIE);
/* Put ADSP in D3hot */
- tmp32 = read32(bar1->base + PCH_PCS);
+ tmp32 = read32(res2mmio(bar1, PCH_PCS, 0));
tmp32 |= PCH_PCS_PS_D3HOT;
- write32(bar1->base + PCH_PCS, tmp32);
+ write32(res2mmio(bar1, PCH_PCS, 0), tmp32);
} else {
printk(BIOS_INFO, "ADSP: Enable PCI Mode IRQ23\n");
diff --git a/src/soc/intel/broadwell/hda.c b/src/soc/intel/broadwell/hda.c
index 80caa2c..7686805 100644
--- a/src/soc/intel/broadwell/hda.c
+++ b/src/soc/intel/broadwell/hda.c
@@ -36,7 +36,7 @@ u32 cim_verb_data_size = 0;
const u32 * pc_beep_verbs = NULL;
u32 pc_beep_verbs_size = 0;
-static void codecs_init(u32 base, u32 codec_mask)
+static void codecs_init(u8 *base, u32 codec_mask)
{
int i;
@@ -52,7 +52,7 @@ static void codecs_init(u32 base, u32 codec_mask)
hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs);
}
-static void hda_pch_init(struct device *dev, u32 base)
+static void hda_pch_init(struct device *dev, u8 *base)
{
u8 reg8;
u16 reg16;
@@ -108,7 +108,7 @@ static void hda_pch_init(struct device *dev, u32 base)
static void hda_init(struct device *dev)
{
- u32 base;
+ u8 *base;
struct resource *res;
u32 codec_mask;
u32 reg32;
@@ -118,8 +118,8 @@ static void hda_init(struct device *dev)
if (!res)
return;
- base = (u32)res->base;
- printk(BIOS_DEBUG, "HDA: base = %08x\n", (u32)base);
+ base = res2mmio(res, 0, 0);
+ printk(BIOS_DEBUG, "HDA: base = %p\n", base);
/* Set Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index 0f27fec..31293e5 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -246,14 +246,14 @@ static struct resource *gtt_res = NULL;
static unsigned long gtt_read(unsigned long reg)
{
u32 val;
- val = read32(gtt_res->base + reg);
+ val = read32(res2mmio(gtt_res, reg, 0));
return val;
}
static void gtt_write(unsigned long reg, unsigned long data)
{
- write32(gtt_res->base + reg, data);
+ write32(res2mmio(gtt_res, reg, 0), data);
}
static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask)
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 394a9d7..53cc4b8 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -53,22 +53,22 @@ static void pch_enable_ioapic(struct device *dev)
{
u32 reg32;
- set_ioapic_id(IO_APIC_ADDR, 0x02);
+ set_ioapic_id(VIO_APIC_VADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */
- reg32 = io_apic_read(IO_APIC_ADDR, 0x01);
+ reg32 = io_apic_read(VIO_APIC_VADDR, 0x01);
/* PCH-LP has 39 redirection entries */
reg32 &= ~0x00ff0000;
reg32 |= 0x00270000;
- io_apic_write(IO_APIC_ADDR, 0x01, reg32);
+ io_apic_write(VIO_APIC_VADDR, 0x01, reg32);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
- io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
+ io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
}
/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c
index de043f4..fd28cfe 100644
--- a/src/soc/intel/broadwell/me.c
+++ b/src/soc/intel/broadwell/me.c
@@ -60,7 +60,7 @@ static const char *me_bios_path_values[] = {
static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev);
/* MMIO base address for MEI interface */
-static u32 mei_base_address;
+static u8 *mei_base_address;
void intel_me_mbp_clear(device_t dev);
#if CONFIG_DEBUG_INTEL_ME
@@ -572,7 +572,7 @@ void intel_me_finalize(void)
u32 reg32;
/* S3 path will have hidden this device already */
- if (!mei_base_address || mei_base_address == 0xfffffff0)
+ if (!mei_base_address || mei_base_address == (u8 *)0xfffffff0)
return;
#if CONFIG_ME_MBP_CLEAR_LATE
@@ -710,7 +710,7 @@ static int intel_mei_setup(device_t dev)
printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
return -1;
}
- mei_base_address = res->base;
+ mei_base_address = res2mmio(res, 0, 0);
/* Ensure Memory and Bus Master bits are set */
reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c
index 43aeec2..6fd8e63 100644
--- a/src/soc/intel/broadwell/minihd.c
+++ b/src/soc/intel/broadwell/minihd.c
@@ -68,7 +68,7 @@ static const u32 minihd_verb_table[] = {
static void minihd_init(struct device *dev)
{
struct resource *res;
- u32 base, reg32;
+ u8 *base, reg32;
int codec_mask, i;
/* Find base address */
@@ -76,8 +76,8 @@ static void minihd_init(struct device *dev)
if (!res)
return;
- base = (u32)res->base;
- printk(BIOS_DEBUG, "Mini-HD: base = %08x\n", (u32)base);
+ base = res2mmio(res, 0, 0);
+ printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base);
/* Set Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c
index e8d1fbe..13b4fe0 100644
--- a/src/soc/intel/broadwell/sata.c
+++ b/src/soc/intel/broadwell/sata.c
@@ -45,7 +45,8 @@ static inline void sir_write(struct device *dev, int idx, u32 value)
static void sata_init(struct device *dev)
{
config_t *config = dev->chip_info;
- u32 reg32, abar;
+ u32 reg32;
+ u8 *abar;
u16 reg16;
printk(BIOS_DEBUG, "SATA: Initializing controller in AHCI mode.\n");
@@ -107,8 +108,8 @@ static void sata_init(struct device *dev)
pci_write_config32(dev, 0x94, reg32);
/* Initialize AHCI memory-mapped space */
- abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
- printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
+ abar = (u8 *)(pci_read_config32(dev, PCI_BASE_ADDRESS_5));
+ printk(BIOS_DEBUG, "ABAR: %p\n", abar);
/* CAP (HBA Capabilities) : enable power management */
reg32 = read32(abar + 0x00);
diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c
index e2b17af..82f37cd 100644
--- a/src/soc/intel/broadwell/serialio.c
+++ b/src/soc/intel/broadwell/serialio.c
@@ -37,9 +37,9 @@
/* Set D3Hot Power State in ACPI mode */
static void serialio_enable_d3hot(struct resource *res)
{
- u32 reg32 = read32(res->base + PCH_PCS);
+ u32 reg32 = read32(res2mmio(res, PCH_PCS, 0));
reg32 |= PCH_PCS_PS_D3HOT;
- write32(res->base + PCH_PCS, reg32);
+ write32(res2mmio(res, PCH_PCS, 0), reg32);
}
static int serialio_uart_is_debug(struct device *dev)
@@ -58,9 +58,9 @@ static int serialio_uart_is_debug(struct device *dev)
/* Enable clock in PCI mode */
static void serialio_enable_clock(struct resource *bar0)
{
- u32 reg32 = read32(bar0->base + SIO_REG_PPR_CLOCK);
+ u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0));
reg32 |= SIO_REG_PPR_CLOCK_EN;
- write32(bar0->base + SIO_REG_PPR_CLOCK, reg32);
+ write32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0), reg32);
}
/* Put Serial IO D21:F0-F6 device into desired mode. */
@@ -111,22 +111,22 @@ static void serialio_d21_ltr(struct resource *bar0)
u32 reg;
/* 1. Program BAR0 + 808h[2] = 0b */
- reg = read32(bar0->base + SIO_REG_PPR_GEN);
+ reg = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0));
reg &= ~SIO_REG_PPR_GEN_LTR_MODE_MASK;
- write32(bar0->base + SIO_REG_PPR_GEN, reg);
+ write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg);
/* 2. Program BAR0 + 804h[1:0] = 00b */
- reg = read32(bar0->base + SIO_REG_PPR_RST);
+ reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0));
reg &= ~SIO_REG_PPR_RST_ASSERT;
- write32(bar0->base + SIO_REG_PPR_RST, reg);
+ write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg);
/* 3. Program BAR0 + 804h[1:0] = 11b */
- reg = read32(bar0->base + SIO_REG_PPR_RST);
+ reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0));
reg |= SIO_REG_PPR_RST_ASSERT;
- write32(bar0->base + SIO_REG_PPR_RST, reg);
+ write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg);
/* 4. Program BAR0 + 814h[31:0] = 00000000h */
- write32(bar0->base + SIO_REG_AUTO_LTR, 0);
+ write32(res2mmio(bar0, SIO_REG_AUTO_LTR, 0), 0);
}
/* Enable LTR Auto Mode for D23:F0. */
@@ -135,26 +135,26 @@ static void serialio_d23_ltr(struct resource *bar0)
u32 reg;
/* Program BAR0 + 1008h[2] = 1b */
- reg = read32(bar0->base + SIO_REG_SDIO_PPR_GEN);
+ reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0));
reg |= SIO_REG_PPR_GEN_LTR_MODE_MASK;
- write32(bar0->base + SIO_REG_SDIO_PPR_GEN, reg);
+ write32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0), reg);
/* Program BAR0 + 1010h = 0x00000000 */
- write32(bar0->base + SIO_REG_SDIO_PPR_SW_LTR, 0);
+ write32(res2mmio(bar0, SIO_REG_SDIO_PPR_SW_LTR, 0), 0);
/* Program BAR0 + 3Ch[30] = 1b */
- reg = read32(bar0->base + SIO_REG_SDIO_PPR_CMD12);
+ reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0));
reg |= SIO_REG_SDIO_PPR_CMD12_B30;
- write32(bar0->base + SIO_REG_SDIO_PPR_CMD12, reg);
+ write32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0), reg);
}
/* Select I2C voltage of 1.8V or 3.3V. */
static void serialio_i2c_voltage_sel(struct resource *bar0, u8 voltage)
{
- u32 reg32 = read32(bar0->base + SIO_REG_PPR_GEN);
+ u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0));
reg32 &= ~SIO_REG_PPR_GEN_VOLTAGE_MASK;
reg32 |= SIO_REG_PPR_GEN_VOLTAGE(voltage);
- write32(bar0->base + SIO_REG_PPR_GEN, reg32);
+ write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg32);
}
/* Init sequence to be run once, done as part of D21:F0 (SDMA) init. */
diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c
index eeffda0..4710271 100644
--- a/src/soc/intel/broadwell/spi.c
+++ b/src/soc/intel/broadwell/spi.c
@@ -168,7 +168,7 @@ enum {
static u8 readb_(const void *addr)
{
- u8 v = read8((unsigned long)addr);
+ u8 v = read8(addr);
printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -176,7 +176,7 @@ static u8 readb_(const void *addr)
static u16 readw_(const void *addr)
{
- u16 v = read16((unsigned long)addr);
+ u16 v = read16(addr);
printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -184,7 +184,7 @@ static u16 readw_(const void *addr)
static u32 readl_(const void *addr)
{
- u32 v = read32((unsigned long)addr);
+ u32 v = read32(addr);
printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -192,33 +192,33 @@ static u32 readl_(const void *addr)
static void writeb_(u8 b, const void *addr)
{
- write8((unsigned long)addr, b);
+ write8(addr, b);
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writew_(u16 b, const void *addr)
{
- write16((unsigned long)addr, b);
+ write16(addr, b);
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writel_(u32 b, const void *addr)
{
- write32((unsigned long)addr, b);
+ write32(addr, b);
printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
-#define readb_(a) read8((uint32_t)a)
-#define readw_(a) read16((uint32_t)a)
-#define readl_(a) read32((uint32_t)a)
-#define writeb_(val, addr) write8((uint32_t)addr, val)
-#define writew_(val, addr) write16((uint32_t)addr, val)
-#define writel_(val, addr) write32((uint32_t)addr, val)
+#define readb_(a) read8(a)
+#define readw_(a) read16(a)
+#define readl_(a) read32(a)
+#define writeb_(val, addr) write8(addr, val)
+#define writew_(val, addr) write16(addr, val)
+#define writel_(val, addr) write32(addr, val)
#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c
index 89e1139..60223c1 100644
--- a/src/soc/intel/broadwell/xhci.c
+++ b/src/soc/intel/broadwell/xhci.c
@@ -27,7 +27,7 @@
#include <broadwell/xhci.h>
#ifdef __SMM__
-static u32 usb_xhci_mem_base(device_t dev)
+static u8 *usb_xhci_mem_base(device_t dev)
{
u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
@@ -35,7 +35,7 @@ static u32 usb_xhci_mem_base(device_t dev)
if (mem_base == 0 || mem_base == 0xffffffff)
return 0;
- return mem_base & ~0xf;
+ return (u8 *)(mem_base & ~0xf);
}
static int usb_xhci_port_count_usb3(device_t dev)
@@ -44,9 +44,9 @@ static int usb_xhci_port_count_usb3(device_t dev)
return 4;
}
-static void usb_xhci_reset_status_usb3(u32 mem_base, int port)
+static void usb_xhci_reset_status_usb3(u8 *mem_base, int port)
{
- u32 portsc = mem_base + XHCI_USB3_PORTSC(port);
+ u8 *portsc = mem_base + XHCI_USB3_PORTSC(port);
u32 status = read32(portsc);
/* Do not set Port Enabled/Disabled field */
status &= ~XHCI_USB3_PORTSC_PED;
@@ -55,9 +55,9 @@ static void usb_xhci_reset_status_usb3(u32 mem_base, int port)
write32(portsc, status);
}
-static void usb_xhci_reset_port_usb3(u32 mem_base, int port)
+static void usb_xhci_reset_port_usb3(u8 *mem_base, int port)
{
- u32 portsc = mem_base + XHCI_USB3_PORTSC(port);
+ u8 *portsc = mem_base + XHCI_USB3_PORTSC(port);
write32(portsc, read32(portsc) | XHCI_USB3_PORTSC_WPR);
}
@@ -76,7 +76,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
u32 status, port_disabled;
int timeout, port;
int port_count = usb_xhci_port_count_usb3(dev);
- u32 mem_base = usb_xhci_mem_base(dev);
+ u8 *mem_base = usb_xhci_mem_base(dev);
if (!mem_base || !port_count)
return;
@@ -105,7 +105,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
/* Reset all requested ports */
for (port = 0; port < port_count; port++) {
- u32 portsc = mem_base + XHCI_USB3_PORTSC(port);
+ u8 *portsc = mem_base + XHCI_USB3_PORTSC(port);
/* Skip disabled ports */
if (port_disabled & (1 << port))
continue;
@@ -146,7 +146,7 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
{
u16 reg16;
u32 reg32;
- u32 mem_base = usb_xhci_mem_base(dev);
+ u8 *mem_base = usb_xhci_mem_base(dev);
if (!mem_base || slp_typ < 3)
return;
diff --git a/src/soc/intel/common/hda_verb.c b/src/soc/intel/common/hda_verb.c
index 946972e..bd61cee 100644
--- a/src/soc/intel/common/hda_verb.c
+++ b/src/soc/intel/common/hda_verb.c
@@ -27,7 +27,7 @@
/**
* Set bits in a register and wait for status
*/
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
@@ -59,7 +59,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
/**
* Probe for supported codecs
*/
-int hda_codec_detect(u32 base)
+int hda_codec_detect(u8 *base)
{
u8 reg8;
@@ -90,7 +90,7 @@ no_codec:
* Wait 50usec for the codec to indicate it is ready
* no response would imply that the codec is non-operative
*/
-static int hda_wait_for_ready(u32 base)
+static int hda_wait_for_ready(u8 *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -112,7 +112,7 @@ static int hda_wait_for_ready(u32 base)
* the previous command. No response would imply that the code
* is non-operative
*/
-static int hda_wait_for_valid(u32 base)
+static int hda_wait_for_valid(u8 *base)
{
u32 reg32;
@@ -184,7 +184,7 @@ static u32 hda_find_verb(u32 verb_table_bytes,
/**
* Write a supplied verb table
*/
-int hda_codec_write(u32 base, u32 size, const u32 *data)
+int hda_codec_write(u8 *base, u32 size, const u32 *data)
{
int i;
@@ -204,7 +204,7 @@ int hda_codec_write(u32 base, u32 size, const u32 *data)
/**
* Initialize codec, then find the verb table and write it
*/
-int hda_codec_init(u32 base, int addr, int verb_size, const u32 *verb_data)
+int hda_codec_init(u8 *base, int addr, int verb_size, const u32 *verb_data)
{
const u32 *verb;
u32 reg32, size;
diff --git a/src/soc/intel/common/hda_verb.h b/src/soc/intel/common/hda_verb.h
index a9c93c6..e062f28 100644
--- a/src/soc/intel/common/hda_verb.h
+++ b/src/soc/intel/common/hda_verb.h
@@ -32,8 +32,8 @@
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
-int hda_codec_detect(u32 base);
-int hda_codec_write(u32 base, u32 size, const u32 *data);
-int hda_codec_init(u32 base, int addr, int verb_size, const u32 *verb_data);
+int hda_codec_detect(u8 *base);
+int hda_codec_write(u8 *base, u32 size, const u32 *data);
+int hda_codec_init(u8 *base, int addr, int verb_size, const u32 *verb_data);
#endif /* _COMMON_HDA_VERB_H_ */
diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c
index fb0dc87..11c4493 100644
--- a/src/soc/intel/fsp_baytrail/acpi.c
+++ b/src/soc/intel/fsp_baytrail/acpi.c
@@ -105,7 +105,7 @@ void acpi_init_gnvs(global_nvs_t *gnvs)
static int acpi_sci_irq(void)
{
- const unsigned long actl = ILB_BASE_ADDRESS + ACTL;
+ u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL);
int scis;
static int sci_irq;
diff --git a/src/soc/intel/fsp_baytrail/baytrail/baytrail.h b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h
index d3a2377..1982c27 100644
--- a/src/soc/intel/fsp_baytrail/baytrail/baytrail.h
+++ b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h
@@ -34,8 +34,11 @@
/* Southbridge internal device MEM BARs (Set to match FSP settings) */
#define DEFAULT_IBASE 0xfed08000
#define DEFAULT_PBASE 0xfed03000
+#ifndef __ACPI__
+#define DEFAULT_RCBA ((u8 *)0xfed1c000)
+#else
#define DEFAULT_RCBA 0xfed1c000
-
+#endif
/* Everything below this line is ignored in the DSDT */
#ifndef __ACPI__
diff --git a/src/soc/intel/fsp_baytrail/baytrail/gpio.h b/src/soc/intel/fsp_baytrail/baytrail/gpio.h
index e13b663..1aa64d0 100644
--- a/src/soc/intel/fsp_baytrail/baytrail/gpio.h
+++ b/src/soc/intel/fsp_baytrail/baytrail/gpio.h
@@ -339,20 +339,20 @@ void configure_score_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val);
#define PCU_SMB_CLK_PAD 88
#define PCU_SMB_DATA_PAD 90
-static inline unsigned int score_pconf0(int pad_num)
+static inline uint32_t *score_pconf0(int pad_num)
{
- return GPSCORE_PAD_BASE + pad_num * 16;
+ return (uint32_t *)(GPSCORE_PAD_BASE + pad_num * 16);
}
-static inline unsigned int ssus_pconf0(int pad_num)
+static inline uint32_t *ssus_pconf0(int pad_num)
{
- return GPSSUS_PAD_BASE + pad_num * 16;
+ return (uint32_t *)(GPSSUS_PAD_BASE + pad_num * 16);
}
static inline void score_select_func(int pad, int func)
{
uint32_t reg;
- uint32_t pconf0_addr = score_pconf0(pad);
+ uint32_t *pconf0_addr = score_pconf0(pad);
reg = read32(pconf0_addr);
reg &= ~0x7;
@@ -363,7 +363,7 @@ static inline void score_select_func(int pad, int func)
static inline void ssus_select_func(int pad, int func)
{
uint32_t reg;
- uint32_t pconf0_addr = ssus_pconf0(pad);
+ uint32_t *pconf0_addr = ssus_pconf0(pad);
reg = read32(pconf0_addr);
reg &= ~0x7;
@@ -376,14 +376,14 @@ static inline void ssus_select_func(int pad, int func)
/* These functions require that the input pad be configured as an input GPIO */
static inline int score_get_gpio(int pad)
{
- uint32_t val_addr = score_pconf0(pad) + PAD_VAL_REG;
+ uint32_t *val_addr = score_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t));
return read32(val_addr) & PAD_VAL_HIGH;
}
static inline int ssus_get_gpio(int pad)
{
- uint32_t val_addr = ssus_pconf0(pad) + PAD_VAL_REG;
+ uint32_t *val_addr = ssus_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t));
return read32(val_addr) & PAD_VAL_HIGH;
}
diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
index e8f5572..843e741 100644
--- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
+++ b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
@@ -63,7 +63,7 @@ static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type)
*/
static void enable_spi_prefetch(void)
{
- uint32_t bcr = SPI_BASE_ADDRESS + BCR;
+ u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR);
/* Enable caching and prefetching in the SPI controller. */
write32(bcr, (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH);
}
diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c
index b202f00..f4159c9 100644
--- a/src/soc/intel/fsp_baytrail/gpio.c
+++ b/src/soc/intel/fsp_baytrail/gpio.c
@@ -103,7 +103,7 @@ static void setup_gpios(const struct soc_gpio_map *gpios,
{
const struct soc_gpio_map *config;
int gpio = 0;
- u32 reg, pad_conf0;
+ u32 reg, pad_conf0, *regmmio;
u8 set, bit;
u32 use_sel[4] = {0};
@@ -138,7 +138,8 @@ static void setup_gpios(const struct soc_gpio_map *gpios,
}
/* Pad configuration registers */
- reg = bank->pad_base + 16 * bank->gpio_to_pad[gpio];
+ regmmio = (u32 *)(bank->pad_base + 16 *
+ bank->gpio_to_pad[gpio]);
/* Add correct func to GPIO pad config */
pad_conf0 = config->pad_conf0;
@@ -152,13 +153,14 @@ static void setup_gpios(const struct soc_gpio_map *gpios,
}
#ifdef GPIO_DEBUG
- printk(BIOS_DEBUG, "Write Pad: Base(%x) - %x %x %x\n",
- reg, pad_conf0, config->pad_conf1, config->pad_val);
+ printk(BIOS_DEBUG, "Write Pad: Base(%p) - %x %x %x\n",
+ regmmio, pad_conf0, config->pad_conf1, config->pad_val);
#endif
- write32(reg + PAD_CONF0_REG, pad_conf0);
- write32(reg + PAD_CONF1_REG, config->pad_conf1);
- write32(reg + PAD_VAL_REG, config->pad_val);
+ write32(regmmio + (PAD_CONF0_REG/sizeof(u32)), pad_conf0);
+ write32(regmmio + (PAD_CONF1_REG/sizeof(u32)),
+ config->pad_conf1);
+ write32(regmmio + (PAD_VAL_REG/sizeof(u32)), config->pad_val);
}
if (bank->legacy_base != GP_LEGACY_BASE_NONE)
@@ -215,7 +217,7 @@ static void setup_gpio_route(const struct soc_gpio_map *sus,
static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],
const struct gpio_bank *bank)
{
- u32 reg = bank->pad_base + PAD_BASE_DIRQ_OFFSET;
+ u32 *reg = (u32 *)(bank->pad_base + PAD_BASE_DIRQ_OFFSET);
u32 val;
int i;
@@ -223,10 +225,10 @@ static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],
for (i=0; i<4; ++i) {
val = dirq[i * 4 + 3] << 24 | dirq[i * 4 + 2] << 16 |
dirq[i * 4 + 1] << 8 | dirq[i * 4];
- write32(reg + i * 4, val);
+ write32(reg + i, val);
#ifdef GPIO_DEBUG
printk(BIOS_DEBUG, "Write DIRQ reg(%x) - %x\n",
- reg + i * 4, val);
+ reg + i, val);
#endif
}
}
@@ -299,7 +301,7 @@ static void configure_ssus_score_gpio(uint8_t ssus_gpio, uint8_t gpio_num,
uint32_t pconf0, uint32_t pad_val)
{
uint32_t reg;
- uint32_t pad_addr;
+ uint32_t *pad_addr;
if (ssus_gpio)
pad_addr = ssus_pconf0(gpssus_gpio_to_pad[gpio_num]);
else
@@ -321,7 +323,7 @@ static void configure_ssus_score_gpio(uint8_t ssus_gpio, uint8_t gpio_num,
*/
reg = PAD_CONFIG0_DEFAULT;
reg |= pconf0 & 0x787;
- write32(pad_addr + PAD_CONF0_REG, reg);
+ write32(pad_addr + (PAD_CONF0_REG/sizeof(u32)), reg);
/*
* Pad Value Register
@@ -329,10 +331,10 @@ static void configure_ssus_score_gpio(uint8_t ssus_gpio, uint8_t gpio_num,
* 1: output enable (0 is enabled)
* 2: input enable (0 is enabled)
*/
- reg = read32(pad_addr + PAD_VAL_REG);
+ reg = read32(pad_addr + (PAD_VAL_REG/sizeof(u32)));
reg &= ~0x7;
reg |= pad_val & 0x7;
- write32(pad_addr + PAD_VAL_REG, reg);
+ write32(pad_addr + (PAD_VAL_REG/sizeof(u32)), reg);
}
/** \brief Sets up the function, pulls, and Input/Output of a Baytrail S5 GPIO
diff --git a/src/soc/intel/fsp_baytrail/iosf.c b/src/soc/intel/fsp_baytrail/iosf.c
index f892b20..eee7c64 100644
--- a/src/soc/intel/fsp_baytrail/iosf.c
+++ b/src/soc/intel/fsp_baytrail/iosf.c
@@ -29,11 +29,11 @@
static inline void write_iosf_reg(int reg, uint32_t value)
{
- write32(IOSF_PCI_BASE + reg, value);
+ write32((u32 *)(IOSF_PCI_BASE + reg), value);
}
static inline uint32_t read_iosf_reg(int reg)
{
- return read32(IOSF_PCI_BASE + reg);
+ return read32((u32 *)(IOSF_PCI_BASE + reg));
}
#else
static inline void write_iosf_reg(int reg, uint32_t value)
diff --git a/src/soc/intel/fsp_baytrail/pmutil.c b/src/soc/intel/fsp_baytrail/pmutil.c
index aee3726..8295b69 100644
--- a/src/soc/intel/fsp_baytrail/pmutil.c
+++ b/src/soc/intel/fsp_baytrail/pmutil.c
@@ -355,10 +355,10 @@ void clear_pmc_status(void)
uint32_t prsts;
uint32_t gen_pmcon1;
- prsts = read32(PMC_BASE_ADDRESS + PRSTS);
- gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
+ prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS));
+ gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1));
/* Clear the status bits. The RPS field is cleared on a 0 write. */
- write32(PMC_BASE_ADDRESS + GEN_PMCON1, gen_pmcon1 & ~RPS);
- write32(PMC_BASE_ADDRESS + PRSTS, prsts);
+ write32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS);
+ write32((u32 *)(PMC_BASE_ADDRESS + PRSTS), prsts);
}
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
index ad42e73..647198d 100644
--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -57,7 +57,7 @@ uint32_t chipset_prev_sleep_state(uint32_t clear)
/* Read Power State */
pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
- gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
+ gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1));
printk(BIOS_DEBUG, "PM1_STS = 0x%x PM1_CNT = 0x%x GEN_PMCON1 = 0x%x\n",
pm1_sts, pm1_cnt, gen_pmcon1);
@@ -119,8 +119,8 @@ static void program_base_addresses(void)
static void spi_init(void)
{
- const uint32_t scs = SPI_BASE_ADDRESS + SCS;
- const uint32_t bcr = SPI_BASE_ADDRESS + BCR;
+ uint32_t *scs = (uint32_t *)(SPI_BASE_ADDRESS + SCS);
+ uint32_t *bcr = (uint32_t *)(SPI_BASE_ADDRESS + BCR);
uint32_t reg;
/* Disable generating SMI when setting WPD bit. */
@@ -136,8 +136,8 @@ static void spi_init(void)
static void baytrail_rtc_init(void)
{
- uint32_t pbase = pci_read_config32(LPC_BDF, PBASE) & 0xfffffff0;
- uint32_t gen_pmcon1 = read32(pbase + GEN_PMCON1);
+ uint32_t *pbase = (uint32_t *)(pci_read_config32(LPC_BDF, PBASE) & 0xfffffff0);
+ uint32_t gen_pmcon1 = read32(pbase + (GEN_PMCON1/sizeof(u32)));
int rtc_failed = !!(gen_pmcon1 & RPS);
if (rtc_failed) {
@@ -145,7 +145,7 @@ static void baytrail_rtc_init(void)
"RTC Failure detected. Resetting Date to %s\n",
coreboot_dmi_date);
- write32(DEFAULT_PBASE + GEN_PMCON1, gen_pmcon1 & ~RPS);
+ write32((uint32_t *)(DEFAULT_PBASE + GEN_PMCON1), gen_pmcon1 & ~RPS);
}
cmos_init(rtc_failed);
@@ -154,8 +154,8 @@ static void baytrail_rtc_init(void)
/* Entry from cache-as-ram.inc. */
void main(FSP_INFO_HEADER *fsp_info_header)
{
- const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS;
- const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2;
+ uint32_t *func_dis = (uint32_t *)(PMC_BASE_ADDRESS + FUNC_DIS);
+ uint32_t *func_dis2 = (uint32_t *)(PMC_BASE_ADDRESS + FUNC_DIS2);
uint32_t fd_mask = 0;
uint32_t fd2_mask = 0;
diff --git a/src/soc/intel/fsp_baytrail/smm.c b/src/soc/intel/fsp_baytrail/smm.c
index d4b3d58..2a8892d 100644
--- a/src/soc/intel/fsp_baytrail/smm.c
+++ b/src/soc/intel/fsp_baytrail/smm.c
@@ -67,7 +67,7 @@ void southcluster_smm_clear_state(void)
static void southcluster_smm_route_gpios(void)
{
- const unsigned long gpio_rout = PMC_BASE_ADDRESS + GPIO_ROUT;
+ u32 *gpio_rout = (u32 *)(PMC_BASE_ADDRESS + GPIO_ROUT);
const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI;
uint32_t alt_gpio_reg = 0;
uint32_t route_reg = gpio_route;
diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c
index d87935b..878535f 100644
--- a/src/soc/intel/fsp_baytrail/southcluster.c
+++ b/src/soc/intel/fsp_baytrail/southcluster.c
@@ -82,17 +82,17 @@ static void sc_enable_ioapic(struct device *dev)
{
int i;
u32 reg32;
- volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
- volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
- u32 ilb_base = pci_read_config32(dev, IBASE) & ~0x0f;
+ volatile u32 *ioapic_index = (u32 *)(IO_APIC_ADDR);
+ volatile u32 *ioapic_data = (u32 *)(IO_APIC_ADDR + 0x10);
+ u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0x0f);
/*
* Enable ACPI I/O and power management.
* Set SCI IRQ to IRQ9
*/
write32(ilb_base + ILB_OIC, 0x100); /* AEN */
- reg32 = read32(ilb_base + ILB_OIC); /* Read back per BWG */
- write32(ilb_base + ILB_ACTL, 0); /* ACTL bit 2:0 SCIS IRQ9 */
+ reg32 = read32(ilb_base + (ILB_OIC/sizeof(u32))); /* Read back per BWG */
+ write32(ilb_base + (ILB_ACTL/sizeof(u32)), 0); /* ACTL bit 2:0 SCIS IRQ9 */
*ioapic_index = 0;
*ioapic_data = (1 << 25);
@@ -131,7 +131,7 @@ static void sc_enable_serial_irqs(struct device *dev)
* until we understand how it needs to be configured.
*/
u8 reg8;
- u32 ibase = pci_read_config32(dev, IBASE) & ~0xF;
+ u8 *ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF);
/*
* Disable the IOCHK# NMI. Let the NMI handler enable it if it needs.
@@ -259,9 +259,9 @@ static void sc_pirq_init(device_t dev)
{
int i, j;
int pirq;
- const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08;
- const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20;
- const unsigned long actl = ILB_BASE_ADDRESS + ACTL;
+ u8 *pr_base = (u8 *)(ILB_BASE_ADDRESS + 0x08);
+ u16 *ir_base = (u16 *)(ILB_BASE_ADDRESS + 0x20);
+ u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL);
const struct baytrail_irq_route *ir = &global_baytrail_irq_route;
/* Set up the PIRQ PIC routing based on static config. */
@@ -269,7 +269,7 @@ static void sc_pirq_init(device_t dev)
"PIRQ\tA \tB \tC \tD \tE \tF \tG \tH\n"
"IRQ ");
for (i = 0; i < NUM_PIRQS; i++) {
- write8(pr_base + i*sizeof(ir->pic[i]), ir->pic[i]);
+ write8(pr_base + i, ir->pic[i]);
printk(BIOS_SPEW, "\t%d", ir->pic[i]);
}
printk(BIOS_SPEW, "\n\n");
@@ -278,7 +278,7 @@ static void sc_pirq_init(device_t dev)
printk(BIOS_SPEW, "\t\t\tPIRQ[A-H] routed to each INT_PIN[A-D]\n"
"Dev\tINTA (IRQ)\tINTB (IRQ)\tINTC (IRQ)\tINTD (IRQ)\n");
for (i = 0; i < NUM_OF_PCI_DEVS; i++) {
- write16(ir_base + i*sizeof(ir->pcidev[i]), ir->pcidev[i]);
+ write16(ir_base + i, ir->pcidev[i]);
/* If the entry is more than just 0, print it out */
if(ir->pcidev[i]) {
@@ -372,11 +372,11 @@ static void enable_hpet(void)
static void sc_init(struct device *dev)
{
- u32 ibase;
+ u8 *ibase;
printk(BIOS_DEBUG, "soc: southcluster_init\n");
- ibase = pci_read_config32(dev, IBASE) & ~0xF;
+ ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF);
write8(ibase + ILB_MC, 0);
@@ -411,8 +411,8 @@ static void sc_init(struct device *dev)
/* Set bit in function disable register to hide this device. */
static void sc_disable_devfn(device_t dev)
{
- const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS;
- const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2;
+ u32 *func_dis = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS);
+ u32 *func_dis2 = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS2);
uint32_t fd_mask = 0;
uint32_t fd2_mask = 0;
@@ -471,7 +471,7 @@ static inline void set_d3hot_bits(device_t dev, int offset)
* the audio paths work for LPE audio. */
static void hda_work_around(device_t dev)
{
- unsigned long gctl = TEMP_BASE_ADDRESS + 0x8;
+ u32 *gctl = (u32 *)(TEMP_BASE_ADDRESS + 0x8);
/* Need to set magic register 0x43 to 0xd7 in config space. */
pci_write_config8(dev, 0x43, 0xd7);
diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c
index 0c3c63d..abcc62c 100644
--- a/src/soc/intel/fsp_baytrail/spi.c
+++ b/src/soc/intel/fsp_baytrail/spi.c
@@ -193,33 +193,33 @@ static u32 readl_(const void *addr)
static void writeb_(u8 b, const void *addr)
{
- write8((unsigned long)addr, b);
+ write8(addr, b);
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writew_(u16 b, const void *addr)
{
- write16((unsigned long)addr, b);
+ write16(addr, b);
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writel_(u32 b, const void *addr)
{
- write32((unsigned long)addr, b);
+ write32(addr, b);
printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
-#define readb_(a) read8((uint32_t)a)
-#define readw_(a) read16((uint32_t)a)
-#define readl_(a) read32((uint32_t)a)
-#define writeb_(val, addr) write8((uint32_t)addr, val)
-#define writew_(val, addr) write16((uint32_t)addr, val)
-#define writel_(val, addr) write32((uint32_t)addr, val)
+#define readb_(a) read8(a)
+#define readw_(a) read16(a)
+#define readl_(a) read32(a)
+#define writeb_(val, addr) write8(addr, val)
+#define writew_(val, addr) write16(addr, val)
+#define writel_(val, addr) write32(addr, val)
#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
index 258267e..5463d2b 100644
--- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
+++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
@@ -40,7 +40,7 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
{
- u32 base_regs = pci_ehci_base_regs(dev);
+ u8 *base_regs = pci_ehci_base_regs(dev);
u32 reg32;
/* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
@@ -48,7 +48,7 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
reg32 &= ~(0xf << 28);
reg32 |= (port << 28);
reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
- write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
+ write32(base_regs + (DEBUGPORT_MISC_CONTROL / sizeof(u32)), reg32);
}
diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c
index fd2c268..4ddfea2 100644
--- a/src/southbridge/amd/agesa/hudson/hudson.c
+++ b/src/southbridge/amd/agesa/hudson/hudson.c
@@ -40,22 +40,22 @@
void pm_write8(u8 reg, u8 value)
{
- write8(PM_MMIO_BASE + reg, value);
+ write8((void *)(PM_MMIO_BASE + reg), value);
}
u8 pm_read8(u8 reg)
{
- return read8(PM_MMIO_BASE + reg);
+ return read8((void *)(PM_MMIO_BASE + reg));
}
void pm_write16(u8 reg, u16 value)
{
- write16(PM_MMIO_BASE + reg, value);
+ write16((void *)(PM_MMIO_BASE + reg), value);
}
u16 pm_read16(u16 reg)
{
- return read16(PM_MMIO_BASE + reg);
+ return read16((void *)(PM_MMIO_BASE + reg));
}
#define PM_REG_USB_ENABLE 0xef
diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c
index d706292..65b31fd 100644
--- a/src/southbridge/amd/agesa/hudson/imc.c
+++ b/src/southbridge/amd/agesa/hudson/imc.c
@@ -27,22 +27,24 @@
#include <Proc/Fch/Common/FchCommonCfg.h>
#include <Proc/Fch/FchPlatform.h>
+#define VACPI_MMIO_VBASE ((u8 *)ACPI_MMIO_BASE)
+
void imc_reg_init(void)
{
/* Init Power Management Block 2 (PM2) Registers.
* Check BKDG for AMD Family 16h for details. */
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x00, 0x06);
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x01, 0x06);
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x02, 0xf7);
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x03, 0xff);
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x04, 0xff);
+ write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x00, 0x06);
+ write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x01, 0x06);
+ write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x02, 0xf7);
+ write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x03, 0xff);
+ write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x04, 0xff);
#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x10, 0x06);
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x11, 0x06);
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x12, 0xf7);
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x13, 0xff);
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x14, 0xff);
+ write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x10, 0x06);
+ write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x11, 0x06);
+ write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x12, 0xf7);
+ write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x13, 0xff);
+ write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x14, 0xff);
#endif
#if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c
index d6ca215..bc6564d 100644
--- a/src/southbridge/amd/agesa/hudson/sm.c
+++ b/src/southbridge/amd/agesa/hudson/sm.c
@@ -82,7 +82,7 @@
static void sm_init(device_t dev)
{
- setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS);
+ setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
}
static int lsmbus_recv_byte(device_t dev)
diff --git a/src/southbridge/amd/agesa/hudson/smi.h b/src/southbridge/amd/agesa/hudson/smi.h
index 53da00a..520c65f 100644
--- a/src/southbridge/amd/agesa/hudson/smi.h
+++ b/src/southbridge/amd/agesa/hudson/smi.h
@@ -36,22 +36,22 @@ enum smi_lvl {
static inline uint32_t smi_read32(uint8_t offset)
{
- return read32(SMI_BASE + offset);
+ return read32((void *)(SMI_BASE + offset));
}
static inline void smi_write32(uint8_t offset, uint32_t value)
{
- write32(SMI_BASE + offset, value);
+ write32((void *)(SMI_BASE + offset), value);
}
static inline uint16_t smi_read16(uint8_t offset)
{
- return read16(SMI_BASE + offset);
+ return read16((void *)(SMI_BASE + offset));
}
static inline void smi_write16(uint8_t offset, uint16_t value)
{
- write16(SMI_BASE + offset, value);
+ write16((void *)(SMI_BASE + offset), value);
}
void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);
diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c
index 735ab7e..fe6ea50 100644
--- a/src/southbridge/amd/agesa/hudson/spi.c
+++ b/src/southbridge/amd/agesa/hudson/spi.c
@@ -53,12 +53,12 @@ static u32 spibar;
static inline uint8_t spi_read(uint8_t reg)
{
- return read8(spibar + reg);
+ return read8((void *)(spibar + reg));
}
static inline void spi_write(uint8_t reg, uint8_t val)
{
- write8(spibar + reg, val);
+ write8((void *)(spibar + reg), val);
}
static void reset_internal_fifo_pointer(void)
diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c
index 718b40b..d75723c 100644
--- a/src/southbridge/amd/amd8111/lpc.c
+++ b/src/southbridge/amd/amd8111/lpc.c
@@ -42,7 +42,7 @@ static void lpc_init(struct device *dev)
byte |= 1;
pci_write_config8(dev, 0x4B, byte);
/* Don't rename IO APIC */
- setup_ioapic(IO_APIC_ADDR, 0);
+ setup_ioapic(VIO_APIC_VADDR, 0);
/* posted memory write enable */
byte = pci_read_config8(dev, 0x46);
diff --git a/src/southbridge/amd/amd8111/nic.c b/src/southbridge/amd/amd8111/nic.c
index 5352705..21df6c0 100644
--- a/src/southbridge/amd/amd8111/nic.c
+++ b/src/southbridge/amd/amd8111/nic.c
@@ -11,7 +11,7 @@
#include "amd8111.h"
-#define CMD3 0x54
+#define CMD3 (0x54/(sizeof(u32)))
typedef enum {
VAL3 = (1 << 31), /* VAL bit for byte 3 */
@@ -45,11 +45,11 @@ static void nic_init(struct device *dev)
{
struct southbridge_amd_amd8111_config *conf;
struct resource *resource;
- unsigned long mmio;
+ u8 *mmio;
conf = dev->chip_info;
resource = find_resource(dev, PCI_BASE_ADDRESS_0);
- mmio = resource->base;
+ mmio = res2mmio(resource, 0, 0);
/* Hard Reset PHY */
printk(BIOS_DEBUG, "Resetting PHY... ");
diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c
index b0ec2dc..1e1357e 100644
--- a/src/southbridge/amd/cimx/sb700/late.c
+++ b/src/southbridge/amd/cimx/sb700/late.c
@@ -237,12 +237,12 @@ static void sb700_enable(device_t dev)
u32 ioapic_base;
printk(BIOS_DEBUG, "sm_init().\n");
ioapic_base = IO_APIC_ADDR;
- clear_ioapic(ioapic_base);
+ clear_ioapic((void *)ioapic_base);
/* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
if (CONFIG_MAX_CPUS >= 16)
- setup_ioapic(ioapic_base, 0);
+ setup_ioapic((void *)ioapic_base, 0);
else
- setup_ioapic(ioapic_base, CONFIG_MAX_CPUS + 1);
+ setup_ioapic((void *)ioapic_base, CONFIG_MAX_CPUS + 1);
}
break;
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 1eb865e..d3ebcb9 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -408,18 +408,19 @@ static void sb800_enable(device_t dev)
case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
printk(BIOS_INFO, "sm_init().\n");
- clear_ioapic(IO_APIC_ADDR);
+ clear_ioapic(VIO_APIC_VADDR);
#if CONFIG_CPU_AMD_AGESA
/* Assign the ioapic ID the next available number after the processor core local APIC IDs */
- setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS);
+ setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
#else
/* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
#if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16)
/* Assign the ioapic ID the next available number after the processor core local APIC IDs */
- setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
+ setup_ioapic(VIO_APIC_VADDR,
+ CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
#elif (CONFIG_APIC_ID_OFFSET > 0)
/* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
- setup_ioapic(IO_APIC_ADDR, 0);
+ setup_ioapic(VIO_APIC_VADDR, 0);
#else
#error "The processor APIC IDs must be lifted to make room for the I/O APIC ID"
#endif
diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c
index c84eee2..48820bc 100644
--- a/src/southbridge/amd/cimx/sb800/spi.c
+++ b/src/southbridge/amd/cimx/sb800/spi.c
@@ -40,15 +40,17 @@ static u32 spibar;
static void reset_internal_fifo_pointer(void)
{
do {
- write8(spibar + 2, read8(spibar + 2) | 0x10);
- } while (read8(spibar + 0xD) & 0x7);
+ write8((void *)(spibar + 2),
+ read8((void *)(spibar + 2)) | 0x10);
+ } while (read8((void *)(spibar + 0xD)) & 0x7);
}
static void execute_command(void)
{
- write8(spibar + 2, read8(spibar + 2) | 1);
+ write8((void *)(spibar + 2), read8((void *)(spibar + 2)) | 1);
- while ((read8(spibar + 2) & 1) && (read8(spibar+3) & 0x80));
+ while ((read8((void *)(spibar + 2)) & 1) &&
+ (read8((void *)(spibar+3)) & 0x80));
}
void spi_init()
@@ -91,12 +93,12 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
readoffby1 = bytesout ? 0 : 1;
readwrite = (bytesin + readoffby1) << 4 | bytesout;
- write8(spibar + 1, readwrite);
- write8(spibar + 0, cmd);
+ write8((void *)(spibar + 1), readwrite);
+ write8((void *)(spibar + 0), cmd);
reset_internal_fifo_pointer();
for (count = 0; count < bytesout; count++, dout++) {
- write8(spibar + 0x0C, *(u8 *)dout);
+ write8((void *)(spibar + 0x0C), *(u8 *)dout);
}
reset_internal_fifo_pointer();
@@ -105,12 +107,12 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
reset_internal_fifo_pointer();
/* Skip the bytes we sent. */
for (count = 0; count < bytesout; count++) {
- cmd = read8(spibar + 0x0C);
+ cmd = read8((void *)(spibar + 0x0C));
}
reset_internal_fifo_pointer();
for (count = 0; count < bytesin; count++, din++) {
- *(u8 *)din = read8(spibar + 0x0C);
+ *(u8 *)din = read8((void *)(spibar + 0x0C));
}
return 0;
diff --git a/src/southbridge/amd/cimx/sb900/gpio_oem.h b/src/southbridge/amd/cimx/sb900/gpio_oem.h
index 7a61569..b6bde9f 100644
--- a/src/southbridge/amd/cimx/sb900/gpio_oem.h
+++ b/src/southbridge/amd/cimx/sb900/gpio_oem.h
@@ -3,7 +3,7 @@
/* Hudson-2 ACPI PmIO Space Define */
#define SB_ACPI_BASE_ADDRESS 0x0400
-#define ACPI_MMIO_BASE 0xFED80000
+#define ACPI_MMIO_BASE ((u8 *)0xFED80000)
#define SB_CFG_BASE 0x000 // DWORD
#define GPIO_BASE 0x100 // BYTE
#define SMI_BASE 0x200 // DWORD
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index 3d873d0..da79a67 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -429,7 +429,7 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb)
static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
{
- u32 bar;
+ void *bar;
msr_t msr;
device_t dev;
@@ -445,7 +445,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
/* write to clear diag register */
wrmsr(USB2_SB_GLD_MSR_DIAG, rdmsr(USB2_SB_GLD_MSR_DIAG));
- bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+ bar = (void *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
/* Make HCCPARAMS writable */
write32(bar + IPREG04, read32(bar + IPREG04) | USB_HCCPW_SET);
@@ -457,7 +457,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
if (dev) {
- bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+ bar = (void *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
write32(bar + UOCMUX, read32(bar + UOCMUX) & PUEN_SET);
@@ -485,7 +485,8 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
if (dev) {
- bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+ bar = (void *)pci_read_config32(dev,
+ PCI_BASE_ADDRESS_0);
write32(bar + UDCDEVCTL,
read32(bar + UDCDEVCTL) | UDC_SD_SET);
@@ -494,7 +495,8 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
if (dev) {
- bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+ bar = (void *)pci_read_config32(dev,
+ PCI_BASE_ADDRESS_0);
write32(bar + UOCCTL, read32(bar + UOCCTL) | PADEN_SET);
write32(bar + UOCCAP, read32(bar + UOCCAP) | APU_SET);
}
diff --git a/src/southbridge/amd/pi/avalon/enable_usbdebug.c b/src/southbridge/amd/pi/avalon/enable_usbdebug.c
index 258267e..9deeb45 100644
--- a/src/southbridge/amd/pi/avalon/enable_usbdebug.c
+++ b/src/southbridge/amd/pi/avalon/enable_usbdebug.c
@@ -40,7 +40,7 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
{
- u32 base_regs = pci_ehci_base_regs(dev);
+ u8 *base_regs = pci_ehci_base_regs(dev);
u32 reg32;
/* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
diff --git a/src/southbridge/amd/pi/avalon/hudson.c b/src/southbridge/amd/pi/avalon/hudson.c
index 3c07ed2..f38a92a 100644
--- a/src/southbridge/amd/pi/avalon/hudson.c
+++ b/src/southbridge/amd/pi/avalon/hudson.c
@@ -47,22 +47,22 @@ int acpi_get_sleep_type(void)
void pm_write8(u8 reg, u8 value)
{
- write8(PM_MMIO_BASE + reg, value);
+ write8((void *)(PM_MMIO_BASE + reg), value);
}
u8 pm_read8(u8 reg)
{
- return read8(PM_MMIO_BASE + reg);
+ return read8((void *)(PM_MMIO_BASE + reg));
}
void pm_write16(u8 reg, u16 value)
{
- write16(PM_MMIO_BASE + reg, value);
+ write16((void *)(PM_MMIO_BASE + reg), value);
}
u16 pm_read16(u16 reg)
{
- return read16(PM_MMIO_BASE + reg);
+ return read16((void *)(PM_MMIO_BASE + reg));
}
void hudson_enable(device_t dev)
diff --git a/src/southbridge/amd/pi/avalon/sm.c b/src/southbridge/amd/pi/avalon/sm.c
index d6ca215..bc6564d 100644
--- a/src/southbridge/amd/pi/avalon/sm.c
+++ b/src/southbridge/amd/pi/avalon/sm.c
@@ -82,7 +82,7 @@
static void sm_init(device_t dev)
{
- setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS);
+ setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
}
static int lsmbus_recv_byte(device_t dev)
diff --git a/src/southbridge/amd/pi/avalon/smi.h b/src/southbridge/amd/pi/avalon/smi.h
index de987a9..2296c6e 100644
--- a/src/southbridge/amd/pi/avalon/smi.h
+++ b/src/southbridge/amd/pi/avalon/smi.h
@@ -36,22 +36,22 @@ enum smi_lvl {
static inline uint32_t smi_read32(uint8_t offset)
{
- return read32(SMI_BASE + offset);
+ return read32((void *)(SMI_BASE + offset));
}
static inline void smi_write32(uint8_t offset, uint32_t value)
{
- write32(SMI_BASE + offset, value);
+ write32((void *)(SMI_BASE + offset), value);
}
static inline uint16_t smi_read16(uint8_t offset)
{
- return read16(SMI_BASE + offset);
+ return read16((void *)(SMI_BASE + offset));
}
static inline void smi_write16(uint8_t offset, uint16_t value)
{
- write16(SMI_BASE + offset, value);
+ write16((void *)(SMI_BASE + offset), value);
}
void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);
diff --git a/src/southbridge/amd/sb600/hda.c b/src/southbridge/amd/sb600/hda.c
index c65f324..de7a319 100644
--- a/src/southbridge/amd/sb600/hda.c
+++ b/src/southbridge/amd/sb600/hda.c
@@ -30,7 +30,7 @@
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 dword;
int count;
@@ -59,7 +59,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
return 0;
}
-static u32 codec_detect(u32 base)
+static u32 codec_detect(void *base)
{
u32 dword;
@@ -172,7 +172,7 @@ static u32 find_verb(u32 viddid, u32 ** verb)
* Wait 50usec for the codec to indicate it is ready
* no response would imply that the codec is non-operative
*/
-static int wait_for_ready(u32 base)
+static int wait_for_ready(void *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -194,7 +194,7 @@ static int wait_for_ready(u32 base)
* the previous command. No response would imply that the code
* is non-operative
*/
-static int wait_for_valid(u32 base)
+static int wait_for_valid(void *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -211,7 +211,7 @@ static int wait_for_valid(u32 base)
return -1;
}
-static void codec_init(u32 base, int addr)
+static void codec_init(void *base, int addr)
{
u32 dword;
u32 *verb;
@@ -253,7 +253,7 @@ static void codec_init(u32 base, int addr)
printk(BIOS_DEBUG, "verb loaded!\n");
}
-static void codecs_init(u32 base, u32 codec_mask)
+static void codecs_init(void *base, u32 codec_mask)
{
int i;
for (i = 2; i >= 0; i--) {
@@ -266,7 +266,7 @@ static void hda_init(struct device *dev)
{
u8 byte;
u32 dword;
- u32 base;
+ void *base;
struct resource *res;
u32 codec_mask;
device_t sm_dev;
@@ -300,8 +300,8 @@ static void hda_init(struct device *dev)
if (!res)
return;
- base = (u32)res->base;
- printk(BIOS_DEBUG, "base = 0x%x\n", base);
+ base = res2mmio(res, 0, 0);
+ printk(BIOS_DEBUG, "base = 0x%p\n", base);
codec_mask = codec_detect(base);
if (codec_mask) {
diff --git a/src/southbridge/amd/sb600/sata.c b/src/southbridge/amd/sb600/sata.c
index a17aab8..2ff7182 100644
--- a/src/southbridge/amd/sb600/sata.c
+++ b/src/southbridge/amd/sb600/sata.c
@@ -63,7 +63,7 @@ static void sata_init(struct device *dev)
u8 byte;
u16 word;
u32 dword;
- u32 sata_bar5;
+ void *sata_bar5;
u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
int i, j;
@@ -88,7 +88,7 @@ static void sata_init(struct device *dev)
pci_write_config8(sm_dev, 0xaf, byte);
/* get base address */
- sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF;
+ sata_bar5 = (void *)(pci_read_config32(dev, 0x24) & ~0x3FF);
sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3;
sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7;
@@ -100,7 +100,7 @@ static void sata_init(struct device *dev)
printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2); /* 3040 */
printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3); /* 3080 */
printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4); /* 3000 */
- printk(BIOS_SPEW, "sata_bar5=%x\n", sata_bar5); /* e0309000 */
+ printk(BIOS_SPEW, "sata_bar5=%p\n", sata_bar5); /* e0309000 */
/* SERR-Enable */
word = pci_read_config16(dev, 0x04);
diff --git a/src/southbridge/amd/sb600/sm.c b/src/southbridge/amd/sb600/sm.c
index a8e72c2..3ce5f02 100644
--- a/src/southbridge/amd/sb600/sm.c
+++ b/src/southbridge/amd/sb600/sm.c
@@ -57,7 +57,7 @@ static void sm_init(device_t dev)
ioapic_base = pci_read_config32(dev, 0x74) & (0xffffffe0); /* some like mem resource, but does not have enable bit */
/* Don't rename APIC ID */
- clear_ioapic(ioapic_base);
+ clear_ioapic((void *)ioapic_base);
dword = pci_read_config8(dev, 0x62);
dword |= 1 << 2;
diff --git a/src/southbridge/amd/sb600/usb.c b/src/southbridge/amd/sb600/usb.c
index 137a8da..1b2b9ff 100644
--- a/src/southbridge/amd/sb600/usb.c
+++ b/src/southbridge/amd/sb600/usb.c
@@ -88,13 +88,13 @@ static void usb_init2(struct device *dev)
u8 byte;
u16 word;
u32 dword;
- u32 usb2_bar0;
+ void *usb2_bar0;
/* dword = pci_read_config32(dev, 0xf8); */
/* dword |= 40; */
/* pci_write_config32(dev, 0xf8, dword); */
- usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF;
- printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0);
+ usb2_bar0 = (void *)(pci_read_config32(dev, 0x10) & ~0xFF);
+ printk(BIOS_INFO, "usb2_bar0=0x%p\n", usb2_bar0);
/* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistance */
dword = 0x00020F00;
diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c
index 3d23da0..856d5bf 100644
--- a/src/southbridge/amd/sb700/enable_usbdebug.c
+++ b/src/southbridge/amd/sb700/enable_usbdebug.c
@@ -39,7 +39,7 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
{
- u32 base_regs = pci_ehci_base_regs(dev);
+ u8 *base_regs = pci_ehci_base_regs(dev);
u32 reg32;
/* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
diff --git a/src/southbridge/amd/sb700/hda.c b/src/southbridge/amd/sb700/hda.c
index 308b08c..f29ee3d 100644
--- a/src/southbridge/amd/sb700/hda.c
+++ b/src/southbridge/amd/sb700/hda.c
@@ -30,7 +30,7 @@
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 dword;
int count;
@@ -59,7 +59,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
return 0;
}
-static u32 codec_detect(u32 base)
+static u32 codec_detect(void *base)
{
u32 dword;
@@ -94,7 +94,7 @@ no_codec:
* Wait 50usec for the codec to indicate it is ready
* no response would imply that the codec is non-operative
*/
-static int wait_for_ready(u32 base)
+static int wait_for_ready(void *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -116,7 +116,7 @@ static int wait_for_ready(u32 base)
* the previous command. No response would imply that the code
* is non-operative
*/
-static int wait_for_valid(u32 base)
+static int wait_for_valid(void *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -133,7 +133,7 @@ static int wait_for_valid(u32 base)
return -1;
}
-static void codec_init(u32 base, int addr)
+static void codec_init(void *base, int addr)
{
u32 dword;
@@ -153,7 +153,7 @@ static void codec_init(u32 base, int addr)
printk(BIOS_DEBUG, "%x(th) codec viddid: %08x\n", addr, dword);
}
-static void codecs_init(u32 base, u32 codec_mask)
+static void codecs_init(void *base, u32 codec_mask)
{
int i;
for (i = 2; i >= 0; i--) {
@@ -166,7 +166,7 @@ static void hda_init(struct device *dev)
{
u8 byte;
u32 dword;
- u32 base;
+ void *base;
struct resource *res;
u32 codec_mask;
device_t sm_dev;
@@ -202,8 +202,8 @@ static void hda_init(struct device *dev)
if (!res)
return;
- base = (u32)res->base;
- printk(BIOS_DEBUG, "base = 0x%x\n", base);
+ base = res2mmio(res, 0, 0);
+ printk(BIOS_DEBUG, "base = 0x%p\n", base);
codec_mask = codec_detect(base);
if (codec_mask) {
diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c
index 7fa924b..9df6d48 100644
--- a/src/southbridge/amd/sb700/sata.c
+++ b/src/southbridge/amd/sb700/sata.c
@@ -82,7 +82,7 @@ static void sata_init(struct device *dev)
u16 word;
u32 dword;
u8 rev_id;
- u32 sata_bar5;
+ void *sata_bar5;
u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
int i, j;
@@ -108,7 +108,7 @@ static void sata_init(struct device *dev)
rev_id = pci_read_config8(sm_dev, 0x08) - 0x28;
/* get base address */
- sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF;
+ sata_bar5 = (void *)(pci_read_config32(dev, 0x24) & ~0x3FF);
sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3;
sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7;
@@ -120,7 +120,7 @@ static void sata_init(struct device *dev)
printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2); /* 3040 */
printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3); /* 3080 */
printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4); /* 3000 */
- printk(BIOS_SPEW, "sata_bar5=%x\n", sata_bar5); /* e0309000 */
+ printk(BIOS_SPEW, "sata_bar5=%p\n", sata_bar5); /* e0309000 */
/* disable combined mode */
byte = pci_read_config8(sm_dev, 0xAD);
diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c
index 5aa4eb1..1db637b 100644
--- a/src/southbridge/amd/sb700/sm.c
+++ b/src/southbridge/amd/sb700/sm.c
@@ -50,14 +50,14 @@ static void sm_init(device_t dev)
u8 byte_old;
u8 rev;
u32 dword;
- u32 ioapic_base;
+ void *ioapic_base;
u32 on;
u32 nmi_option;
printk(BIOS_INFO, "sm_init().\n");
rev = get_sb700_revision(dev);
- ioapic_base = pci_read_config32(dev, 0x74) & (0xffffffe0); /* some like mem resource, but does not have enable bit */
+ ioapic_base = (void *)(pci_read_config32(dev, 0x74) & (0xffffffe0)); /* some like mem resource, but does not have enable bit */
/* Don't rename APIC ID */
/* TODO: We should call setup_ioapic() here. But kernel hangs if cpu is K8.
* We need to check out why and change back. */
diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c
index 77dcf2e..dd8b390 100644
--- a/src/southbridge/amd/sb700/usb.c
+++ b/src/southbridge/amd/sb700/usb.c
@@ -81,7 +81,7 @@ static void usb_init(struct device *dev)
static void usb_init2(struct device *dev)
{
u32 dword;
- u32 usb2_bar0;
+ void *usb2_bar0;
device_t sm_dev;
u8 rev;
@@ -92,8 +92,8 @@ static void usb_init2(struct device *dev)
/* dword |= 40; */
/* pci_write_config32(dev, 0xf8, dword); */
- usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF;
- printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0);
+ usb2_bar0 = (void *)(pci_read_config32(dev, 0x10) & ~0xFF);
+ printk(BIOS_INFO, "usb2_bar0=0x%p\n", usb2_bar0);
/* RPR6.4 Enables the USB PHY auto calibration resister to match 45ohm resistance */
dword = 0x00020F00;
diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c
index 74e3d33..ed1d88c 100644
--- a/src/southbridge/amd/sb800/enable_usbdebug.c
+++ b/src/southbridge/amd/sb800/enable_usbdebug.c
@@ -40,7 +40,7 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
{
- u32 base_regs = pci_ehci_base_regs(dev);
+ u8 *base_regs = pci_ehci_base_regs(dev);
u32 reg32;
/* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
diff --git a/src/southbridge/amd/sb800/hda.c b/src/southbridge/amd/sb800/hda.c
index 5265684..d40d088 100644
--- a/src/southbridge/amd/sb800/hda.c
+++ b/src/southbridge/amd/sb800/hda.c
@@ -30,7 +30,7 @@
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 dword;
int count;
@@ -59,7 +59,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
return 0;
}
-static u32 codec_detect(u32 base)
+static u32 codec_detect(void *base)
{
u32 dword;
@@ -96,7 +96,7 @@ no_codec:
* Wait 50usec for for the codec to indicate it is ready
* no response would imply that the codec is non-operative
*/
-static int wait_for_ready(u32 base)
+static int wait_for_ready(void *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -118,7 +118,7 @@ static int wait_for_ready(u32 base)
* the previous command. No response would imply that the code
* is non-operative
*/
-static int wait_for_valid(u32 base)
+static int wait_for_valid(void *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -135,7 +135,7 @@ static int wait_for_valid(u32 base)
return -1;
}
-static void codec_init(u32 base, int addr)
+static void codec_init(void *base, int addr)
{
u32 dword;
@@ -155,7 +155,7 @@ static void codec_init(u32 base, int addr)
printk(BIOS_DEBUG, "%x(th) codec viddid: %08x\n", addr, dword);
}
-static void codecs_init(u32 base, u32 codec_mask)
+static void codecs_init(void *base, u32 codec_mask)
{
int i;
for (i = 3; i >= 0; i--) {
@@ -167,7 +167,7 @@ static void codecs_init(u32 base, u32 codec_mask)
static void hda_init(struct device *dev)
{
u32 dword;
- u32 base;
+ void *base;
struct resource *res;
u32 codec_mask;
@@ -183,8 +183,8 @@ static void hda_init(struct device *dev)
if (!res)
return;
- base = (u32)res->base;
- printk(BIOS_DEBUG, "base = 0x%x\n", base);
+ base = res2mmio(res, 0, 0);
+ printk(BIOS_DEBUG, "base = 0x%p\n", base);
codec_mask = codec_detect(base);
if (codec_mask) {
diff --git a/src/southbridge/amd/sb800/sata.c b/src/southbridge/amd/sb800/sata.c
index a1aa6e0..cb685d1 100644
--- a/src/southbridge/amd/sb800/sata.c
+++ b/src/southbridge/amd/sb800/sata.c
@@ -82,7 +82,7 @@ static void sata_init(struct device *dev)
u16 word;
u32 dword;
u8 rev_id;
- u32 sata_bar5;
+ void *sata_bar5;
u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
int i, j;
@@ -98,7 +98,7 @@ static void sata_init(struct device *dev)
rev_id = pci_read_config8(sm_dev, 0x08) - 0x2F;
/* get base address */
- sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF;
+ sata_bar5 = (void *)(pci_read_config32(dev, 0x24) & ~0x3FF);
sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3;
sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7;
@@ -110,7 +110,7 @@ static void sata_init(struct device *dev)
printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2); /* 3040 */
printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3); /* 3080 */
printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4); /* 3000 */
- printk(BIOS_SPEW, "sata_bar5=%x\n", sata_bar5); /* e0309000 */
+ printk(BIOS_SPEW, "sata_bar5=%p\n", sata_bar5); /* e0309000 */
/* SERR-Enable */
word = pci_read_config16(dev, 0x04);
diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c
index 662a82e..2f5dfa1 100644
--- a/src/southbridge/amd/sb800/sm.c
+++ b/src/southbridge/amd/sb800/sm.c
@@ -89,7 +89,7 @@ static void sm_init(device_t dev)
/* Don't rename APIC ID */
/* TODO: We should call setup_ioapic() here. But kernel hangs if cpu is K8.
* We need to check out why and change back. */
- clear_ioapic(IO_APIC_ADDR);
+ clear_ioapic(VIO_APIC_VADDR);
//setup_ioapic(IO_APIC_ADDR, 0);
/* enable serial irq */
diff --git a/src/southbridge/amd/sb800/usb.c b/src/southbridge/amd/sb800/usb.c
index 55be7b8..9cd6397 100644
--- a/src/southbridge/amd/sb800/usb.c
+++ b/src/southbridge/amd/sb800/usb.c
@@ -58,7 +58,7 @@ static void usb_init(struct device *dev)
static void usb_init2(struct device *dev)
{
u32 dword;
- u32 usb2_bar0;
+ void *usb2_bar0;
device_t sm_dev;
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -68,8 +68,8 @@ static void usb_init2(struct device *dev)
/* dword |= 40; */
/* pci_write_config32(dev, 0xf8, dword); */
- usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF;
- printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0);
+ usb2_bar0 = (void *)(pci_read_config32(dev, 0x10) & ~0xFF);
+ printk(BIOS_INFO, "usb2_bar0=0x%p\n", usb2_bar0);
/* RPR7.3 Enables the USB PHY auto calibration resister to match 45ohm resistance */
dword = 0x00020F00;
diff --git a/src/southbridge/amd/sr5650/ht.c b/src/southbridge/amd/sr5650/ht.c
index 737eed2..816800f 100644
--- a/src/southbridge/amd/sr5650/ht.c
+++ b/src/southbridge/amd/sr5650/ht.c
@@ -128,7 +128,7 @@ static void sr5690_apic_init(struct device *dev)
dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
/* TODO: On SR56x0/SP5100 board, the IOAPIC on SR56x0 is the
* 2nd one. We need to check if it also is on your board. */
- setup_ioapic(dword, 1);
+ setup_ioapic((void *)dword, 1);
}
static void pcie_init(struct device *dev)
diff --git a/src/southbridge/broadcom/bcm5785/sata.c b/src/southbridge/broadcom/bcm5785/sata.c
index 62eab45..ca99b1c 100644
--- a/src/southbridge/broadcom/bcm5785/sata.c
+++ b/src/southbridge/broadcom/bcm5785/sata.c
@@ -31,9 +31,9 @@ static void sata_init(struct device *dev)
{
uint8_t byte;
- u32 mmio;
+ u8 *mmio;
struct resource *res;
- u32 mmio_base;
+ u8 *mmio_base;
int i;
if(!(dev->path.pci.devfn & 7)) { // only set it in Func0
@@ -42,8 +42,7 @@ static void sata_init(struct device *dev)
pci_write_config8(dev, 0x78, byte);
res = find_resource(dev, 0x24);
- mmio_base = res->base;
- mmio_base &= 0xfffffffc;
+ mmio_base = res2mmio(res, 0, 3);
write32(mmio_base + 0x10f0, 0x40000001);
write32(mmio_base + 0x8c, 0x00ff2007);
@@ -59,7 +58,7 @@ static void sata_init(struct device *dev)
printk(BIOS_DEBUG, "init PHY...\n");
for(i=0; i<4; i++) {
- mmio = res->base + 0x100 * i;
+ mmio = (u8 *)(uintptr_t)(res->base + 0x100 * i);
byte = read8(mmio + 0x40);
printk(BIOS_DEBUG, "port %d PHY status = %02x\n", i, byte);
if(byte & 0x4) {// bit 2 is set
diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index bef88ab..32223c2 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -35,7 +35,7 @@
typedef struct southbridge_intel_bd82x6x_config config_t;
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
@@ -64,7 +64,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
return 0;
}
-static int codec_detect(u32 base)
+static int codec_detect(u8 *base)
{
u8 reg8;
@@ -73,7 +73,8 @@ static int codec_detect(u32 base)
goto no_codec;
/* Write back the value once reset bit is set. */
- write16(base + 0x0, read16(base + 0x0));
+ write16(base + 0x0,
+ read16(base + 0x0));
/* Read in Codec location (BAR + 0xe)[2..0]*/
reg8 = read8(base + 0xe);
@@ -114,14 +115,14 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
* no response would imply that the codec is non-operative
*/
-static int wait_for_ready(u32 base)
+static int wait_for_ready(u8 *base)
{
/* Use a 1msec timeout */
int timeout = 1000;
while(timeout--) {
- u32 reg32 = read32(base + HDA_ICII_REG);
+ u32 reg32 = read32(base + HDA_ICII_REG);
if (!(reg32 & HDA_ICII_BUSY))
return 0;
udelay(1);
@@ -136,7 +137,7 @@ static int wait_for_ready(u32 base)
* is non-operative
*/
-static int wait_for_valid(u32 base)
+static int wait_for_valid(u8 *base)
{
u32 reg32;
@@ -159,7 +160,7 @@ static int wait_for_valid(u32 base)
return -1;
}
-static void codec_init(struct device *dev, u32 base, int addr)
+static void codec_init(struct device *dev, u8 *base, int addr)
{
u32 reg32;
const u32 *verb;
@@ -207,7 +208,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
}
-static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
+static void codecs_init(struct device *dev, u8 *base, u32 codec_mask)
{
int i;
for (i = 3; i >= 0; i--) {
@@ -228,7 +229,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
static void azalia_init(struct device *dev)
{
- u32 base;
+ u8 *base;
struct resource *res;
u32 codec_mask;
u8 reg8;
@@ -242,7 +243,7 @@ static void azalia_init(struct device *dev)
// NOTE this will break as soon as the Azalia get's a bar above
// 4G. Is there anything we can do about it?
- base = (u32)res->base;
+ base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
if (RCBA32(0x2030) & (1 << 31)) {
diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c
index b1b53af..52c2172 100644
--- a/src/southbridge/intel/bd82x6x/bootblock.c
+++ b/src/southbridge/intel/bd82x6x/bootblock.c
@@ -53,7 +53,7 @@ static void enable_port80_on_lpc(void)
pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
/* Enable port 80 POST on LPC */
- pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1);
+ pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
#if 0
RCBA32(GCS) &= (~0x04);
#else
diff --git a/src/southbridge/intel/bd82x6x/early_pch_native.c b/src/southbridge/intel/bd82x6x/early_pch_native.c
index 0863f34..5f42728 100644
--- a/src/southbridge/intel/bd82x6x/early_pch_native.c
+++ b/src/southbridge/intel/bd82x6x/early_pch_native.c
@@ -37,7 +37,7 @@
static void
wait_2338 (void)
{
- while (read8 (DEFAULT_RCBA | 0x2338) & 1);
+ while (read8 (DEFAULT_RCBA + 0x2338) & 1);
}
static u32
@@ -45,13 +45,13 @@ read_2338 (u32 edx)
{
u32 ret;
- write32 (DEFAULT_RCBA | 0x2330, edx);
- write16 (DEFAULT_RCBA | 0x2338, (read16 (DEFAULT_RCBA | 0x2338)
+ write32 (DEFAULT_RCBA + 0x2330, edx);
+ write16 (DEFAULT_RCBA + 0x2338, (read16 (DEFAULT_RCBA + 0x2338)
& 0x1ff) | 0x600);
wait_2338 ();
- ret = read32 (DEFAULT_RCBA | 0x2334);
+ ret = read32 (DEFAULT_RCBA + 0x2334);
wait_2338 ();
- read8 (DEFAULT_RCBA | 0x2338);
+ read8 (DEFAULT_RCBA + 0x2338);
return ret;
}
@@ -59,15 +59,15 @@ static void
write_2338 (u32 edx, u32 val)
{
read_2338 (edx);
- write16 (DEFAULT_RCBA | 0x2338, (read16 (DEFAULT_RCBA | 0x2338)
+ write16 (DEFAULT_RCBA + 0x2338, (read16 (DEFAULT_RCBA + 0x2338)
& 0x1ff) | 0x600);
wait_2338 ();
- write32 (DEFAULT_RCBA | 0x2334, val);
+ write32 (DEFAULT_RCBA + 0x2334, val);
wait_2338 ();
- write16 (DEFAULT_RCBA | 0x2338,
- (read16 (DEFAULT_RCBA | 0x2338) & 0x1ff) | 0x600);
- read8 (DEFAULT_RCBA | 0x2338);
+ write16 (DEFAULT_RCBA + 0x2338,
+ (read16 (DEFAULT_RCBA + 0x2338) & 0x1ff) | 0x600);
+ read8 (DEFAULT_RCBA + 0x2338);
}
@@ -76,214 +76,214 @@ init_dmi (void)
{
int i;
- write32 (DEFAULT_DMIBAR | 0x0914,
- read32 (DEFAULT_DMIBAR | 0x0914) | 0x80000000);
- write32 (DEFAULT_DMIBAR | 0x0934,
- read32 (DEFAULT_DMIBAR | 0x0934) | 0x80000000);
+ write32 (DEFAULT_DMIBAR + 0x0914,
+ read32 (DEFAULT_DMIBAR + 0x0914) | 0x80000000);
+ write32 (DEFAULT_DMIBAR + 0x0934,
+ read32 (DEFAULT_DMIBAR + 0x0934) | 0x80000000);
for (i = 0; i < 4; i++)
{
- write32 (DEFAULT_DMIBAR | 0x0a00 | (i << 4),
- read32 (DEFAULT_DMIBAR | 0x0a00 | (i << 4)) & 0xf3ffffff);
- write32 (DEFAULT_DMIBAR | 0x0a04 | (i << 4),
- read32 (DEFAULT_DMIBAR | 0x0a04 | (i << 4)) | 0x800);
+ write32 (DEFAULT_DMIBAR + 0x0a00 + (i << 4),
+ read32 (DEFAULT_DMIBAR + 0x0a00 + (i << 4)) & 0xf3ffffff);
+ write32 (DEFAULT_DMIBAR + 0x0a04 + (i << 4),
+ read32 (DEFAULT_DMIBAR + 0x0a04 + (i << 4)) | 0x800);
}
- write32 (DEFAULT_DMIBAR | 0x0c30, (read32 (DEFAULT_DMIBAR | 0x0c30)
+ write32 (DEFAULT_DMIBAR + 0x0c30, (read32 (DEFAULT_DMIBAR + 0x0c30)
& 0xfffffff) | 0x40000000);
for (i = 0; i < 2; i++)
{
- write32 (DEFAULT_DMIBAR | 0x0904 | (i << 5),
- read32 (DEFAULT_DMIBAR | 0x0904 | (i << 5)) & 0xfe3fffff);
- write32 (DEFAULT_DMIBAR | 0x090c | (i << 5),
- read32 (DEFAULT_DMIBAR | 0x090c | (i << 5)) & 0xfff1ffff);
+ write32 (DEFAULT_DMIBAR + 0x0904 + (i << 5),
+ read32 (DEFAULT_DMIBAR + 0x0904 + (i << 5)) & 0xfe3fffff);
+ write32 (DEFAULT_DMIBAR + 0x090c + (i << 5),
+ read32 (DEFAULT_DMIBAR + 0x090c + (i << 5)) & 0xfff1ffff);
}
- write32 (DEFAULT_DMIBAR | 0x090c,
- read32 (DEFAULT_DMIBAR | 0x090c) & 0xfe1fffff);
- write32 (DEFAULT_DMIBAR | 0x092c,
- read32 (DEFAULT_DMIBAR | 0x092c) & 0xfe1fffff);
- read32 (DEFAULT_DMIBAR | 0x0904); // !!! = 0x7a1842ec
- write32 (DEFAULT_DMIBAR | 0x0904, 0x7a1842ec);
- read32 (DEFAULT_DMIBAR | 0x090c); // !!! = 0x00000208
- write32 (DEFAULT_DMIBAR | 0x090c, 0x00000128);
- read32 (DEFAULT_DMIBAR | 0x0924); // !!! = 0x7a1842ec
- write32 (DEFAULT_DMIBAR | 0x0924, 0x7a1842ec);
- read32 (DEFAULT_DMIBAR | 0x092c); // !!! = 0x00000208
- write32 (DEFAULT_DMIBAR | 0x092c, 0x00000128);
- read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x46139008
- write32 (DEFAULT_DMIBAR | 0x0700, 0x46139008);
- read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x46139008
- write32 (DEFAULT_DMIBAR | 0x0720, 0x46139008);
- read32 (DEFAULT_DMIBAR | 0x0c04); // !!! = 0x2e680008
- write32 (DEFAULT_DMIBAR | 0x0c04, 0x2e680008);
- read32 (DEFAULT_DMIBAR | 0x0904); // !!! = 0x7a1842ec
- write32 (DEFAULT_DMIBAR | 0x0904, 0x3a1842ec);
- read32 (DEFAULT_DMIBAR | 0x0924); // !!! = 0x7a1842ec
- write32 (DEFAULT_DMIBAR | 0x0924, 0x3a1842ec);
- read32 (DEFAULT_DMIBAR | 0x0910); // !!! = 0x00006300
- write32 (DEFAULT_DMIBAR | 0x0910, 0x00004300);
- read32 (DEFAULT_DMIBAR | 0x0930); // !!! = 0x00006300
- write32 (DEFAULT_DMIBAR | 0x0930, 0x00004300);
- read32 (DEFAULT_DMIBAR | 0x0a00); // !!! = 0x03042010
- write32 (DEFAULT_DMIBAR | 0x0a00, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0a10); // !!! = 0x03042010
- write32 (DEFAULT_DMIBAR | 0x0a10, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0a20); // !!! = 0x03042010
- write32 (DEFAULT_DMIBAR | 0x0a20, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0a30); // !!! = 0x03042010
- write32 (DEFAULT_DMIBAR | 0x0a30, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0c00); // !!! = 0x29700c08
- write32 (DEFAULT_DMIBAR | 0x0c00, 0x29700c08);
- read32 (DEFAULT_DMIBAR | 0x0a04); // !!! = 0x0c0708f0
- write32 (DEFAULT_DMIBAR | 0x0a04, 0x0c0718f0);
- read32 (DEFAULT_DMIBAR | 0x0a14); // !!! = 0x0c0708f0
- write32 (DEFAULT_DMIBAR | 0x0a14, 0x0c0718f0);
- read32 (DEFAULT_DMIBAR | 0x0a24); // !!! = 0x0c0708f0
- write32 (DEFAULT_DMIBAR | 0x0a24, 0x0c0718f0);
- read32 (DEFAULT_DMIBAR | 0x0a34); // !!! = 0x0c0708f0
- write32 (DEFAULT_DMIBAR | 0x0a34, 0x0c0718f0);
- read32 (DEFAULT_DMIBAR | 0x0900); // !!! = 0x50000000
- write32 (DEFAULT_DMIBAR | 0x0900, 0x50000000);
- read32 (DEFAULT_DMIBAR | 0x0920); // !!! = 0x50000000
- write32 (DEFAULT_DMIBAR | 0x0920, 0x50000000);
- read32 (DEFAULT_DMIBAR | 0x0908); // !!! = 0x51ffffff
- write32 (DEFAULT_DMIBAR | 0x0908, 0x51ffffff);
- read32 (DEFAULT_DMIBAR | 0x0928); // !!! = 0x51ffffff
- write32 (DEFAULT_DMIBAR | 0x0928, 0x51ffffff);
- read32 (DEFAULT_DMIBAR | 0x0a00); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a00, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0a10); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a10, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0a20); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a20, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0a30); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a30, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x46139008
- write32 (DEFAULT_DMIBAR | 0x0700, 0x46139008);
- read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x46139008
- write32 (DEFAULT_DMIBAR | 0x0720, 0x46139008);
- read32 (DEFAULT_DMIBAR | 0x0904); // !!! = 0x3a1842ec
- write32 (DEFAULT_DMIBAR | 0x0904, 0x3a1846ec);
- read32 (DEFAULT_DMIBAR | 0x0924); // !!! = 0x3a1842ec
- write32 (DEFAULT_DMIBAR | 0x0924, 0x3a1846ec);
- read32 (DEFAULT_DMIBAR | 0x0a00); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a00, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0a10); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a10, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0a20); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a20, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0a30); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a30, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0908); // !!! = 0x51ffffff
- write32 (DEFAULT_DMIBAR | 0x0908, 0x51ffffff);
- read32 (DEFAULT_DMIBAR | 0x0928); // !!! = 0x51ffffff
- write32 (DEFAULT_DMIBAR | 0x0928, 0x51ffffff);
- read32 (DEFAULT_DMIBAR | 0x0c00); // !!! = 0x29700c08
- write32 (DEFAULT_DMIBAR | 0x0c00, 0x29700c08);
- read32 (DEFAULT_DMIBAR | 0x0c0c); // !!! = 0x16063400
- write32 (DEFAULT_DMIBAR | 0x0c0c, 0x00063400);
- read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x46139008
- write32 (DEFAULT_DMIBAR | 0x0700, 0x46339008);
- read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x46139008
- write32 (DEFAULT_DMIBAR | 0x0720, 0x46339008);
- read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x46339008
- write32 (DEFAULT_DMIBAR | 0x0700, 0x45339008);
- read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x46339008
- write32 (DEFAULT_DMIBAR | 0x0720, 0x45339008);
- read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x45339008
- write32 (DEFAULT_DMIBAR | 0x0700, 0x453b9008);
- read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x45339008
- write32 (DEFAULT_DMIBAR | 0x0720, 0x453b9008);
- read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x453b9008
- write32 (DEFAULT_DMIBAR | 0x0700, 0x45bb9008);
- read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x453b9008
- write32 (DEFAULT_DMIBAR | 0x0720, 0x45bb9008);
- read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x45bb9008
- write32 (DEFAULT_DMIBAR | 0x0700, 0x45fb9008);
- read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x45bb9008
- write32 (DEFAULT_DMIBAR | 0x0720, 0x45fb9008);
- read32 (DEFAULT_DMIBAR | 0x0914); // !!! = 0x9021a080
- write32 (DEFAULT_DMIBAR | 0x0914, 0x9021a280);
- read32 (DEFAULT_DMIBAR | 0x0934); // !!! = 0x9021a080
- write32 (DEFAULT_DMIBAR | 0x0934, 0x9021a280);
- read32 (DEFAULT_DMIBAR | 0x0914); // !!! = 0x9021a280
- write32 (DEFAULT_DMIBAR | 0x0914, 0x9821a280);
- read32 (DEFAULT_DMIBAR | 0x0934); // !!! = 0x9021a280
- write32 (DEFAULT_DMIBAR | 0x0934, 0x9821a280);
- read32 (DEFAULT_DMIBAR | 0x0a00); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a00, 0x03242018);
- read32 (DEFAULT_DMIBAR | 0x0a10); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a10, 0x03242018);
- read32 (DEFAULT_DMIBAR | 0x0a20); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a20, 0x03242018);
- read32 (DEFAULT_DMIBAR | 0x0a30); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a30, 0x03242018);
- read32 (DEFAULT_DMIBAR | 0x0258); // !!! = 0x40000600
- write32 (DEFAULT_DMIBAR | 0x0258, 0x60000600);
- read32 (DEFAULT_DMIBAR | 0x0904); // !!! = 0x3a1846ec
- write32 (DEFAULT_DMIBAR | 0x0904, 0x2a1846ec);
- read32 (DEFAULT_DMIBAR | 0x0914); // !!! = 0x9821a280
- write32 (DEFAULT_DMIBAR | 0x0914, 0x98200280);
- read32 (DEFAULT_DMIBAR | 0x0924); // !!! = 0x3a1846ec
- write32 (DEFAULT_DMIBAR | 0x0924, 0x2a1846ec);
- read32 (DEFAULT_DMIBAR | 0x0934); // !!! = 0x9821a280
- write32 (DEFAULT_DMIBAR | 0x0934, 0x98200280);
- read32 (DEFAULT_DMIBAR | 0x022c); // !!! = 0x00c26460
- write32 (DEFAULT_DMIBAR | 0x022c, 0x00c2403c);
- read8 (DEFAULT_RCBA | 0x21a4); // !!! = 0x42
+ write32 (DEFAULT_DMIBAR + 0x090c,
+ read32 (DEFAULT_DMIBAR + 0x090c) & 0xfe1fffff);
+ write32 (DEFAULT_DMIBAR + 0x092c,
+ read32 (DEFAULT_DMIBAR + 0x092c) & 0xfe1fffff);
+ read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x7a1842ec
+ write32 (DEFAULT_DMIBAR + 0x0904, 0x7a1842ec);
+ read32 (DEFAULT_DMIBAR + 0x090c); // !!! = 0x00000208
+ write32 (DEFAULT_DMIBAR + 0x090c, 0x00000128);
+ read32 (DEFAULT_DMIBAR + 0x0924); // !!! = 0x7a1842ec
+ write32 (DEFAULT_DMIBAR + 0x0924, 0x7a1842ec);
+ read32 (DEFAULT_DMIBAR + 0x092c); // !!! = 0x00000208
+ write32 (DEFAULT_DMIBAR + 0x092c, 0x00000128);
+ read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x46139008
+ write32 (DEFAULT_DMIBAR + 0x0700, 0x46139008);
+ read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x46139008
+ write32 (DEFAULT_DMIBAR + 0x0720, 0x46139008);
+ read32 (DEFAULT_DMIBAR + 0x0c04); // !!! = 0x2e680008
+ write32 (DEFAULT_DMIBAR + 0x0c04, 0x2e680008);
+ read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x7a1842ec
+ write32 (DEFAULT_DMIBAR + 0x0904, 0x3a1842ec);
+ read32 (DEFAULT_DMIBAR + 0x0924); // !!! = 0x7a1842ec
+ write32 (DEFAULT_DMIBAR + 0x0924, 0x3a1842ec);
+ read32 (DEFAULT_DMIBAR + 0x0910); // !!! = 0x00006300
+ write32 (DEFAULT_DMIBAR + 0x0910, 0x00004300);
+ read32 (DEFAULT_DMIBAR + 0x0930); // !!! = 0x00006300
+ write32 (DEFAULT_DMIBAR + 0x0930, 0x00004300);
+ read32 (DEFAULT_DMIBAR + 0x0a00); // !!! = 0x03042010
+ write32 (DEFAULT_DMIBAR + 0x0a00, 0x03042018);
+ read32 (DEFAULT_DMIBAR + 0x0a10); // !!! = 0x03042010
+ write32 (DEFAULT_DMIBAR + 0x0a10, 0x03042018);
+ read32 (DEFAULT_DMIBAR + 0x0a20); // !!! = 0x03042010
+ write32 (DEFAULT_DMIBAR + 0x0a20, 0x03042018);
+ read32 (DEFAULT_DMIBAR + 0x0a30); // !!! = 0x03042010
+ write32 (DEFAULT_DMIBAR + 0x0a30, 0x03042018);
+ read32 (DEFAULT_DMIBAR + 0x0c00); // !!! = 0x29700c08
+ write32 (DEFAULT_DMIBAR + 0x0c00, 0x29700c08);
+ read32 (DEFAULT_DMIBAR + 0x0a04); // !!! = 0x0c0708f0
+ write32 (DEFAULT_DMIBAR + 0x0a04, 0x0c0718f0);
+ read32 (DEFAULT_DMIBAR + 0x0a14); // !!! = 0x0c0708f0
+ write32 (DEFAULT_DMIBAR + 0x0a14, 0x0c0718f0);
+ read32 (DEFAULT_DMIBAR + 0x0a24); // !!! = 0x0c0708f0
+ write32 (DEFAULT_DMIBAR + 0x0a24, 0x0c0718f0);
+ read32 (DEFAULT_DMIBAR + 0x0a34); // !!! = 0x0c0708f0
+ write32 (DEFAULT_DMIBAR + 0x0a34, 0x0c0718f0);
+ read32 (DEFAULT_DMIBAR + 0x0900); // !!! = 0x50000000
+ write32 (DEFAULT_DMIBAR + 0x0900, 0x50000000);
+ read32 (DEFAULT_DMIBAR + 0x0920); // !!! = 0x50000000
+ write32 (DEFAULT_DMIBAR + 0x0920, 0x50000000);
+ read32 (DEFAULT_DMIBAR + 0x0908); // !!! = 0x51ffffff
+ write32 (DEFAULT_DMIBAR + 0x0908, 0x51ffffff);
+ read32 (DEFAULT_DMIBAR + 0x0928); // !!! = 0x51ffffff
+ write32 (DEFAULT_DMIBAR + 0x0928, 0x51ffffff);
+ read32 (DEFAULT_DMIBAR + 0x0a00); // !!! = 0x03042018
+ write32 (DEFAULT_DMIBAR + 0x0a00, 0x03042018);
+ read32 (DEFAULT_DMIBAR + 0x0a10); // !!! = 0x03042018
+ write32 (DEFAULT_DMIBAR + 0x0a10, 0x03042018);
+ read32 (DEFAULT_DMIBAR + 0x0a20); // !!! = 0x03042018
+ write32 (DEFAULT_DMIBAR + 0x0a20, 0x03042018);
+ read32 (DEFAULT_DMIBAR + 0x0a30); // !!! = 0x03042018
+ write32 (DEFAULT_DMIBAR + 0x0a30, 0x03042018);
+ read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x46139008
+ write32 (DEFAULT_DMIBAR + 0x0700, 0x46139008);
+ read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x46139008
+ write32 (DEFAULT_DMIBAR + 0x0720, 0x46139008);
+ read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x3a1842ec
+ write32 (DEFAULT_DMIBAR + 0x0904, 0x3a1846ec);
+ read32 (DEFAULT_DMIBAR + 0x0924); // !!! = 0x3a1842ec
+ write32 (DEFAULT_DMIBAR + 0x0924, 0x3a1846ec);
+ read32 (DEFAULT_DMIBAR + 0x0a00); // !!! = 0x03042018
+ write32 (DEFAULT_DMIBAR + 0x0a00, 0x03042018);
+ read32 (DEFAULT_DMIBAR + 0x0a10); // !!! = 0x03042018
+ write32 (DEFAULT_DMIBAR + 0x0a10, 0x03042018);
+ read32 (DEFAULT_DMIBAR + 0x0a20); // !!! = 0x03042018
+ write32 (DEFAULT_DMIBAR + 0x0a20, 0x03042018);
+ read32 (DEFAULT_DMIBAR + 0x0a30); // !!! = 0x03042018
+ write32 (DEFAULT_DMIBAR + 0x0a30, 0x03042018);
+ read32 (DEFAULT_DMIBAR + 0x0908); // !!! = 0x51ffffff
+ write32 (DEFAULT_DMIBAR + 0x0908, 0x51ffffff);
+ read32 (DEFAULT_DMIBAR + 0x0928); // !!! = 0x51ffffff
+ write32 (DEFAULT_DMIBAR + 0x0928, 0x51ffffff);
+ read32 (DEFAULT_DMIBAR + 0x0c00); // !!! = 0x29700c08
+ write32 (DEFAULT_DMIBAR + 0x0c00, 0x29700c08);
+ read32 (DEFAULT_DMIBAR + 0x0c0c); // !!! = 0x16063400
+ write32 (DEFAULT_DMIBAR + 0x0c0c, 0x00063400);
+ read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x46139008
+ write32 (DEFAULT_DMIBAR + 0x0700, 0x46339008);
+ read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x46139008
+ write32 (DEFAULT_DMIBAR + 0x0720, 0x46339008);
+ read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x46339008
+ write32 (DEFAULT_DMIBAR + 0x0700, 0x45339008);
+ read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x46339008
+ write32 (DEFAULT_DMIBAR + 0x0720, 0x45339008);
+ read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x45339008
+ write32 (DEFAULT_DMIBAR + 0x0700, 0x453b9008);
+ read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x45339008
+ write32 (DEFAULT_DMIBAR + 0x0720, 0x453b9008);
+ read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x453b9008
+ write32 (DEFAULT_DMIBAR + 0x0700, 0x45bb9008);
+ read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x453b9008
+ write32 (DEFAULT_DMIBAR + 0x0720, 0x45bb9008);
+ read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x45bb9008
+ write32 (DEFAULT_DMIBAR + 0x0700, 0x45fb9008);
+ read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x45bb9008
+ write32 (DEFAULT_DMIBAR + 0x0720, 0x45fb9008);
+ read32 (DEFAULT_DMIBAR + 0x0914); // !!! = 0x9021a080
+ write32 (DEFAULT_DMIBAR + 0x0914, 0x9021a280);
+ read32 (DEFAULT_DMIBAR + 0x0934); // !!! = 0x9021a080
+ write32 (DEFAULT_DMIBAR + 0x0934, 0x9021a280);
+ read32 (DEFAULT_DMIBAR + 0x0914); // !!! = 0x9021a280
+ write32 (DEFAULT_DMIBAR + 0x0914, 0x9821a280);
+ read32 (DEFAULT_DMIBAR + 0x0934); // !!! = 0x9021a280
+ write32 (DEFAULT_DMIBAR + 0x0934, 0x9821a280);
+ read32 (DEFAULT_DMIBAR + 0x0a00); // !!! = 0x03042018
+ write32 (DEFAULT_DMIBAR + 0x0a00, 0x03242018);
+ read32 (DEFAULT_DMIBAR + 0x0a10); // !!! = 0x03042018
+ write32 (DEFAULT_DMIBAR + 0x0a10, 0x03242018);
+ read32 (DEFAULT_DMIBAR + 0x0a20); // !!! = 0x03042018
+ write32 (DEFAULT_DMIBAR + 0x0a20, 0x03242018);
+ read32 (DEFAULT_DMIBAR + 0x0a30); // !!! = 0x03042018
+ write32 (DEFAULT_DMIBAR + 0x0a30, 0x03242018);
+ read32 (DEFAULT_DMIBAR + 0x0258); // !!! = 0x40000600
+ write32 (DEFAULT_DMIBAR + 0x0258, 0x60000600);
+ read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x3a1846ec
+ write32 (DEFAULT_DMIBAR + 0x0904, 0x2a1846ec);
+ read32 (DEFAULT_DMIBAR + 0x0914); // !!! = 0x9821a280
+ write32 (DEFAULT_DMIBAR + 0x0914, 0x98200280);
+ read32 (DEFAULT_DMIBAR + 0x0924); // !!! = 0x3a1846ec
+ write32 (DEFAULT_DMIBAR + 0x0924, 0x2a1846ec);
+ read32 (DEFAULT_DMIBAR + 0x0934); // !!! = 0x9821a280
+ write32 (DEFAULT_DMIBAR + 0x0934, 0x98200280);
+ read32 (DEFAULT_DMIBAR + 0x022c); // !!! = 0x00c26460
+ write32 (DEFAULT_DMIBAR + 0x022c, 0x00c2403c);
+ read8 (DEFAULT_RCBA + 0x21a4); // !!! = 0x42
- read32 (DEFAULT_RCBA | 0x21a4); // !!! = 0x00012c42
- read32 (DEFAULT_RCBA | 0x2340); // !!! = 0x0013001b
- write32 (DEFAULT_RCBA | 0x2340, 0x003a001b);
- read8 (DEFAULT_RCBA | 0x21b0); // !!! = 0x01
- write8 (DEFAULT_RCBA | 0x21b0, 0x02);
- read32 (DEFAULT_DMIBAR | 0x0084); // !!! = 0x0041ac41
- write32 (DEFAULT_DMIBAR | 0x0084, 0x0041ac42);
- read8 (DEFAULT_DMIBAR | 0x0088); // !!! = 0x00
- write8 (DEFAULT_DMIBAR | 0x0088, 0x20);
- read16 (DEFAULT_DMIBAR | 0x008a); // !!! = 0x0041
- read8 (DEFAULT_DMIBAR | 0x0088); // !!! = 0x00
- write8 (DEFAULT_DMIBAR | 0x0088, 0x20);
- read16 (DEFAULT_DMIBAR | 0x008a); // !!! = 0x0042
- read16 (DEFAULT_DMIBAR | 0x008a); // !!! = 0x0042
+ read32 (DEFAULT_RCBA + 0x21a4); // !!! = 0x00012c42
+ read32 (DEFAULT_RCBA + 0x2340); // !!! = 0x0013001b
+ write32 (DEFAULT_RCBA + 0x2340, 0x003a001b);
+ read8 (DEFAULT_RCBA + 0x21b0); // !!! = 0x01
+ write8 (DEFAULT_RCBA + 0x21b0, 0x02);
+ read32 (DEFAULT_DMIBAR + 0x0084); // !!! = 0x0041ac41
+ write32 (DEFAULT_DMIBAR + 0x0084, 0x0041ac42);
+ read8 (DEFAULT_DMIBAR + 0x0088); // !!! = 0x00
+ write8 (DEFAULT_DMIBAR + 0x0088, 0x20);
+ read16 (DEFAULT_DMIBAR + 0x008a); // !!! = 0x0041
+ read8 (DEFAULT_DMIBAR + 0x0088); // !!! = 0x00
+ write8 (DEFAULT_DMIBAR + 0x0088, 0x20);
+ read16 (DEFAULT_DMIBAR + 0x008a); // !!! = 0x0042
+ read16 (DEFAULT_DMIBAR + 0x008a); // !!! = 0x0042
- read32 (DEFAULT_DMIBAR | 0x0014); // !!! = 0x8000007f
- write32 (DEFAULT_DMIBAR | 0x0014, 0x80000019);
- read32 (DEFAULT_DMIBAR | 0x0020); // !!! = 0x01000000
- write32 (DEFAULT_DMIBAR | 0x0020, 0x81000022);
- read32 (DEFAULT_DMIBAR | 0x002c); // !!! = 0x02000000
- write32 (DEFAULT_DMIBAR | 0x002c, 0x82000044);
- read32 (DEFAULT_DMIBAR | 0x0038); // !!! = 0x07000080
- write32 (DEFAULT_DMIBAR | 0x0038, 0x87000080);
- read8 (DEFAULT_DMIBAR | 0x0004); // !!! = 0x00
- write8 (DEFAULT_DMIBAR | 0x0004, 0x01);
+ read32 (DEFAULT_DMIBAR + 0x0014); // !!! = 0x8000007f
+ write32 (DEFAULT_DMIBAR + 0x0014, 0x80000019);
+ read32 (DEFAULT_DMIBAR + 0x0020); // !!! = 0x01000000
+ write32 (DEFAULT_DMIBAR + 0x0020, 0x81000022);
+ read32 (DEFAULT_DMIBAR + 0x002c); // !!! = 0x02000000
+ write32 (DEFAULT_DMIBAR + 0x002c, 0x82000044);
+ read32 (DEFAULT_DMIBAR + 0x0038); // !!! = 0x07000080
+ write32 (DEFAULT_DMIBAR + 0x0038, 0x87000080);
+ read8 (DEFAULT_DMIBAR + 0x0004); // !!! = 0x00
+ write8 (DEFAULT_DMIBAR + 0x0004, 0x01);
- read32 (DEFAULT_RCBA | 0x0050); // !!! = 0x01200654
- write32 (DEFAULT_RCBA | 0x0050, 0x01200654);
- read32 (DEFAULT_RCBA | 0x0050); // !!! = 0x01200654
- write32 (DEFAULT_RCBA | 0x0050, 0x012a0654);
- read32 (DEFAULT_RCBA | 0x0050); // !!! = 0x012a0654
- read8 (DEFAULT_RCBA | 0x1114); // !!! = 0x00
- write8 (DEFAULT_RCBA | 0x1114, 0x05);
- read32 (DEFAULT_RCBA | 0x2014); // !!! = 0x80000011
- write32 (DEFAULT_RCBA | 0x2014, 0x80000019);
- read32 (DEFAULT_RCBA | 0x2020); // !!! = 0x00000000
- write32 (DEFAULT_RCBA | 0x2020, 0x81000022);
- read32 (DEFAULT_RCBA | 0x2020); // !!! = 0x81000022
- read32 (DEFAULT_RCBA | 0x2030); // !!! = 0x00000000
- write32 (DEFAULT_RCBA | 0x2030, 0x82000044);
- read32 (DEFAULT_RCBA | 0x2030); // !!! = 0x82000044
- read32 (DEFAULT_RCBA | 0x2040); // !!! = 0x00000000
- write32 (DEFAULT_RCBA | 0x2040, 0x87000080);
- read32 (DEFAULT_RCBA | 0x0050); // !!! = 0x012a0654
- write32 (DEFAULT_RCBA | 0x0050, 0x812a0654);
- read32 (DEFAULT_RCBA | 0x0050); // !!! = 0x812a0654
- read16 (DEFAULT_RCBA | 0x201a); // !!! = 0x0000
- read16 (DEFAULT_RCBA | 0x2026); // !!! = 0x0000
- read16 (DEFAULT_RCBA | 0x2036); // !!! = 0x0000
- read16 (DEFAULT_RCBA | 0x2046); // !!! = 0x0000
- read16 (DEFAULT_DMIBAR | 0x001a); // !!! = 0x0000
- read16 (DEFAULT_DMIBAR | 0x0026); // !!! = 0x0000
- read16 (DEFAULT_DMIBAR | 0x0032); // !!! = 0x0000
- read16 (DEFAULT_DMIBAR | 0x003e); // !!! = 0x0000
+ read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x01200654
+ write32 (DEFAULT_RCBA + 0x0050, 0x01200654);
+ read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x01200654
+ write32 (DEFAULT_RCBA + 0x0050, 0x012a0654);
+ read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x012a0654
+ read8 (DEFAULT_RCBA + 0x1114); // !!! = 0x00
+ write8 (DEFAULT_RCBA + 0x1114, 0x05);
+ read32 (DEFAULT_RCBA + 0x2014); // !!! = 0x80000011
+ write32 (DEFAULT_RCBA + 0x2014, 0x80000019);
+ read32 (DEFAULT_RCBA + 0x2020); // !!! = 0x00000000
+ write32 (DEFAULT_RCBA + 0x2020, 0x81000022);
+ read32 (DEFAULT_RCBA + 0x2020); // !!! = 0x81000022
+ read32 (DEFAULT_RCBA + 0x2030); // !!! = 0x00000000
+ write32 (DEFAULT_RCBA + 0x2030, 0x82000044);
+ read32 (DEFAULT_RCBA + 0x2030); // !!! = 0x82000044
+ read32 (DEFAULT_RCBA + 0x2040); // !!! = 0x00000000
+ write32 (DEFAULT_RCBA + 0x2040, 0x87000080);
+ read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x012a0654
+ write32 (DEFAULT_RCBA + 0x0050, 0x812a0654);
+ read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x812a0654
+ read16 (DEFAULT_RCBA + 0x201a); // !!! = 0x0000
+ read16 (DEFAULT_RCBA + 0x2026); // !!! = 0x0000
+ read16 (DEFAULT_RCBA + 0x2036); // !!! = 0x0000
+ read16 (DEFAULT_RCBA + 0x2046); // !!! = 0x0000
+ read16 (DEFAULT_DMIBAR + 0x001a); // !!! = 0x0000
+ read16 (DEFAULT_DMIBAR + 0x0026); // !!! = 0x0000
+ read16 (DEFAULT_DMIBAR + 0x0032); // !!! = 0x0000
+ read16 (DEFAULT_DMIBAR + 0x003e); // !!! = 0x0000
}
void
@@ -292,21 +292,21 @@ early_pch_init_native (void)
pcie_write_config8 (SOUTHBRIDGE, 0xa6,
pcie_read_config8 (SOUTHBRIDGE, 0xa6) | 2);
- write32 (DEFAULT_RCBA | 0x2088, 0x00109000);
- read32 (DEFAULT_RCBA | 0x20ac); // !!! = 0x00000000
- write32 (DEFAULT_RCBA | 0x20ac, 0x40000000);
- write32 (DEFAULT_RCBA | 0x100c, 0x01110000);
- write8 (DEFAULT_RCBA | 0x2340, 0x1b);
- read32 (DEFAULT_RCBA | 0x2314); // !!! = 0x0a080000
- write32 (DEFAULT_RCBA | 0x2314, 0x0a280000);
- read32 (DEFAULT_RCBA | 0x2310); // !!! = 0xc809605b
- write32 (DEFAULT_RCBA | 0x2310, 0xa809605b);
- write32 (DEFAULT_RCBA | 0x2324, 0x00854c74);
- read8 (DEFAULT_RCBA | 0x0400); // !!! = 0x00
- read32 (DEFAULT_RCBA | 0x2310); // !!! = 0xa809605b
- write32 (DEFAULT_RCBA | 0x2310, 0xa809605b);
- read32 (DEFAULT_RCBA | 0x2310); // !!! = 0xa809605b
- write32 (DEFAULT_RCBA | 0x2310, 0xa809605b);
+ write32 (DEFAULT_RCBA + 0x2088, 0x00109000);
+ read32 (DEFAULT_RCBA + 0x20ac); // !!! = 0x00000000
+ write32 (DEFAULT_RCBA + 0x20ac, 0x40000000);
+ write32 (DEFAULT_RCBA + 0x100c, 0x01110000);
+ write8 (DEFAULT_RCBA + 0x2340, 0x1b);
+ read32 (DEFAULT_RCBA + 0x2314); // !!! = 0x0a080000
+ write32 (DEFAULT_RCBA + 0x2314, 0x0a280000);
+ read32 (DEFAULT_RCBA + 0x2310); // !!! = 0xc809605b
+ write32 (DEFAULT_RCBA + 0x2310, 0xa809605b);
+ write32 (DEFAULT_RCBA + 0x2324, 0x00854c74);
+ read8 (DEFAULT_RCBA + 0x0400); // !!! = 0x00
+ read32 (DEFAULT_RCBA + 0x2310); // !!! = 0xa809605b
+ write32 (DEFAULT_RCBA + 0x2310, 0xa809605b);
+ read32 (DEFAULT_RCBA + 0x2310); // !!! = 0xa809605b
+ write32 (DEFAULT_RCBA + 0x2310, 0xa809605b);
write_2338 (0xea007f62, 0x00590133);
write_2338 (0xec007f62, 0x00590133);
diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c
index 02ec9a7..f2d04dd 100644
--- a/src/southbridge/intel/bd82x6x/early_thermal.c
+++ b/src/southbridge/intel/bd82x6x/early_thermal.c
@@ -23,6 +23,21 @@
#include "cpu/intel/model_206ax/model_206ax.h"
#include <cpu/x86/msr.h>
+static void write8p(uintptr_t addr, uint32_t val)
+{
+ write8((u8 *)addr, val);
+}
+
+static void write16p(uintptr_t addr, uint32_t val)
+{
+ write16((u16 *)addr, val);
+}
+
+static uint16_t read16p (uintptr_t addr)
+{
+ return read16((u16 *)addr);
+}
+
/* Early thermal init, must be done prior to giving ME its memory
which is done at the end of raminit. */
void early_thermal_init(void)
@@ -41,30 +56,30 @@ void early_thermal_init(void)
pci_read_config32(dev, 0x40) | 5);
- write16 (0x40000004, 0x3a2b);
- write8 (0x4000000c, 0xff);
- write8 (0x4000000d, 0x00);
- write8 (0x4000000e, 0x40);
- write8 (0x40000082, 0x00);
- write8 (0x40000001, 0xba);
+ write16p (0x40000004, 0x3a2b);
+ write8p (0x4000000c, 0xff);
+ write8p (0x4000000d, 0x00);
+ write8p (0x4000000e, 0x40);
+ write8p (0x40000082, 0x00);
+ write8p (0x40000001, 0xba);
/* Perform init. */
/* Configure TJmax. */
msr = rdmsr(MSR_TEMPERATURE_TARGET);
- write16(0x40000012, ((msr.lo >> 16) & 0xff) << 6);
+ write16p(0x40000012, ((msr.lo >> 16) & 0xff) << 6);
/* Northbridge temperature slope and offset. */
- write16(0x40000016, 0x808c);
+ write16p(0x40000016, 0x808c);
- write16 (0x40000014, 0xde87);
+ write16p (0x40000014, 0xde87);
/* Enable thermal data reporting, processor, PCH and northbridge. */
- write16(0x4000001a, (read16(0x4000001a) & ~0xf) | 0x10f0);
+ write16p(0x4000001a, (read16p(0x4000001a) & ~0xf) | 0x10f0);
/* Disable temporary BAR. */
pci_write_config32(dev, 0x40,
pci_read_config32(dev, 0x40) & ~1);
pci_write_config32(dev, 0x40, 0);
- write32 (DEFAULT_RCBA | 0x38b0,
- (read32 (DEFAULT_RCBA | 0x38b0) & 0xffff8003) | 0x403c);
+ write32 (DEFAULT_RCBA + 0x38b0,
+ (read32 (DEFAULT_RCBA + 0x38b0) & 0xffff8003) | 0x403c);
}
diff --git a/src/southbridge/intel/bd82x6x/early_usb_native.c b/src/southbridge/intel/bd82x6x/early_usb_native.c
index b1f8447..2e5686d 100644
--- a/src/southbridge/intel/bd82x6x/early_usb_native.c
+++ b/src/southbridge/intel/bd82x6x/early_usb_native.c
@@ -43,32 +43,32 @@ early_usb_init (const struct southbridge_usb_port *portmap)
/* Unlock registers. */
outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c);
for (i = 0; i < 14; i++)
- write32 (DEFAULT_RCBABASE | (0x3500 + 4 * i),
+ write32 (DEFAULT_RCBABASE + (0x3500 + 4 * i),
currents[portmap[i].current]);
for (i = 0; i < 10; i++)
- write32 (DEFAULT_RCBABASE | (0x3538 + 4 * i), 0);
+ write32 (DEFAULT_RCBABASE + (0x3538 + 4 * i), 0);
for (i = 0; i < 8; i++)
- write32 (DEFAULT_RCBABASE | (0x3560 + 4 * i), rcba_dump[i]);
+ write32 (DEFAULT_RCBABASE + (0x3560 + 4 * i), rcba_dump[i]);
for (i = 0; i < 8; i++)
- write32 (DEFAULT_RCBABASE | (0x3580 + 4 * i), 0);
+ write32 (DEFAULT_RCBABASE + (0x3580 + 4 * i), 0);
reg32 = 0;
for (i = 0; i < 14; i++)
if (!portmap[i].enabled)
reg32 |= (1 << i);
- write32 (DEFAULT_RCBABASE | 0x359c, reg32);
+ write32 (DEFAULT_RCBABASE + 0x359c, reg32);
reg32 = 0;
for (i = 0; i < 8; i++)
if (portmap[i].enabled && portmap[i].oc_pin >= 0)
reg32 |= (1 << (i + 8 * portmap[i].oc_pin));
- write32 (DEFAULT_RCBABASE | 0x35a0, reg32);
+ write32 (DEFAULT_RCBABASE + 0x35a0, reg32);
reg32 = 0;
for (i = 8; i < 14; i++)
if (portmap[i].enabled && portmap[i].oc_pin >= 4)
reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4)));
- write32 (DEFAULT_RCBABASE | 0x35a4, reg32);
+ write32 (DEFAULT_RCBABASE + 0x35a4, reg32);
for (i = 0; i < 22; i++)
- write32 (DEFAULT_RCBABASE | (0x35a8 + 4 * i), 0);
+ write32 (DEFAULT_RCBABASE + (0x35a8 + 4 * i), 0);
pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 11b765a..c323f73 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -59,17 +59,17 @@ static void pch_enable_ioapic(struct device *dev)
/* Enable ACPI I/O range decode */
pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
- set_ioapic_id(IO_APIC_ADDR, 0x02);
+ set_ioapic_id(VIO_APIC_VADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */
- reg32 = io_apic_read(IO_APIC_ADDR, 0x01);
- io_apic_write(IO_APIC_ADDR, 0x01, reg32);
+ reg32 = io_apic_read(VIO_APIC_VADDR, 0x01);
+ io_apic_write(VIO_APIC_VADDR, 0x01, reg32);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
- io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
+ io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
}
static void pch_enable_serial_irqs(struct device *dev)
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 901e71d..df18830 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -64,7 +64,7 @@ static const char *me_bios_path_values[] = {
#endif
/* MMIO base address for MEI interface */
-static u32 mei_base_address;
+static u32 *mei_base_address;
#if CONFIG_DEBUG_INTEL_ME
static void mei_dump(void *ptr, int dword, int offset, const char *type)
@@ -106,7 +106,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type)
static inline void mei_read_dword_ptr(void *ptr, int offset)
{
- u32 dword = read32(mei_base_address + offset);
+ u32 dword = read32(mei_base_address + (offset/sizeof(u32)));
memcpy(ptr, &dword, sizeof(dword));
mei_dump(ptr, dword, offset, "READ");
}
@@ -115,7 +115,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
- write32(mei_base_address + offset, dword);
+ write32(mei_base_address + (offset/sizeof(u32)), dword);
mei_dump(ptr, dword, offset, "WRITE");
}
@@ -145,13 +145,13 @@ static inline void read_me_csr(struct mei_csr *csr)
static inline void write_cb(u32 dword)
{
- write32(mei_base_address + MEI_H_CB_WW, dword);
+ write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword);
mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
}
static inline u32 read_cb(void)
{
- u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
+ u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32)));
mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
return dword;
}
@@ -501,11 +501,11 @@ static void intel_me7_finalize_smm(void)
struct me_hfs hfs;
u32 reg32;
- mei_base_address =
- pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
+ mei_base_address = (u32 *)
+ (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */
- if (!mei_base_address || mei_base_address == 0xfffffff0)
+ if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)
return;
/* Make sure ME is in a mode that expects EOP */
@@ -627,7 +627,7 @@ static int intel_mei_setup(device_t dev)
printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
return -1;
}
- mei_base_address = res->base;
+ mei_base_address = (u32*)(uintptr_t)res->base;
/* Ensure Memory and Bus Master bits are set */
reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index e25b3b8..3fa3269 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -66,7 +66,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data);
#endif
/* MMIO base address for MEI interface */
-static u32 mei_base_address;
+static u32 *mei_base_address;
#if CONFIG_DEBUG_INTEL_ME
static void mei_dump(void *ptr, int dword, int offset, const char *type)
@@ -108,7 +108,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type)
static inline void mei_read_dword_ptr(void *ptr, int offset)
{
- u32 dword = read32(mei_base_address + offset);
+ u32 dword = read32(mei_base_address + (offset/sizeof(u32)));
memcpy(ptr, &dword, sizeof(dword));
mei_dump(ptr, dword, offset, "READ");
}
@@ -117,7 +117,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
- write32(mei_base_address + offset, dword);
+ write32(mei_base_address + (offset/sizeof(u32)), dword);
mei_dump(ptr, dword, offset, "WRITE");
}
@@ -147,13 +147,13 @@ static inline void read_me_csr(struct mei_csr *csr)
static inline void write_cb(u32 dword)
{
- write32(mei_base_address + MEI_H_CB_WW, dword);
+ write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword);
mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
}
static inline u32 read_cb(void)
{
- u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
+ u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32)));
mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
return dword;
}
@@ -495,11 +495,11 @@ void intel_me8_finalize_smm(void)
struct me_hfs hfs;
u32 reg32;
- mei_base_address =
- pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
+ mei_base_address = (void *)
+ (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */
- if (!mei_base_address || mei_base_address == 0xfffffff0)
+ if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)
return;
/* Make sure ME is in a mode that expects EOP */
@@ -614,7 +614,7 @@ static int intel_mei_setup(device_t dev)
printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
return -1;
}
- mei_base_address = res->base;
+ mei_base_address = (u32 *)(uintptr_t)res->base;
/* Ensure Memory and Bus Master bits are set */
reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 7cde7bc..ce4c0e7 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -47,7 +47,11 @@
#define DEFAULT_GPIOBASE 0x0480
#define DEFAULT_PMBASE 0x0500
+#ifndef __ACPI__
+#define DEFAULT_RCBA ((u8 *)0xfed1c000)
+#else
#define DEFAULT_RCBA 0xfed1c000
+#endif
#ifndef __ACPI__
#define DEBUG_PERIODIC_SMIS 0
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index cb5699e..cf3b14e 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -66,7 +66,7 @@ static void sata_init(struct device *dev)
/* AHCI */
if (sata_mode == 0) {
- u32 abar;
+ u8 *abar;
printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
@@ -100,8 +100,8 @@ static void sata_init(struct device *dev)
((config->sata_port_map ^ 0x3f) << 24) | 0x183);
/* Initialize AHCI memory-mapped space */
- abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
- printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
+ abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+ printk(BIOS_DEBUG, "ABAR: %p\n", abar);
/* CAP (HBA Capabilities) : enable power management */
reg32 = read32(abar + 0x00);
reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS
diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c
index 9850fee..b76963f 100644
--- a/src/southbridge/intel/bd82x6x/usb_ehci.c
+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c
@@ -66,8 +66,9 @@ static void usb_ehci_init(struct device *dev)
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
/* Number of ports and companion controllers. */
- reg32 = read32(res->base + 4);
- write32(res->base + 4, (reg32 & 0xfff00000) | 3);
+ reg32 = read32((void *)(uintptr_t)(res->base + 4));
+ write32((void *)(uintptr_t)(res->base + 4),
+ (reg32 & 0xfff00000) | 3);
}
/* Restore protection. */
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 3f22bc7..d6ab01a 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -199,7 +199,7 @@ enum {
static u8 readb_(const void *addr)
{
- u8 v = read8((unsigned long)addr);
+ u8 v = read8(addr);
printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -207,7 +207,7 @@ static u8 readb_(const void *addr)
static u16 readw_(const void *addr)
{
- u16 v = read16((unsigned long)addr);
+ u16 v = read16(addr);
printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -215,41 +215,41 @@ static u16 readw_(const void *addr)
static u32 readl_(const void *addr)
{
- u32 v = read32((unsigned long)addr);
+ u32 v = read32(addr);
printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
}
-static void writeb_(u8 b, const void *addr)
+static void writeb_(u8 b, void *addr)
{
- write8((unsigned long)addr, b);
+ write8(addr, b);
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
-static void writew_(u16 b, const void *addr)
+static void writew_(u16 b, void *addr)
{
- write16((unsigned long)addr, b);
+ write16(addr, b);
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
-static void writel_(u32 b, const void *addr)
+static void writel_(u32 b, void *addr)
{
- write32((unsigned long)addr, b);
+ write32(addr, b);
printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
-#define readb_(a) read8((uint32_t)a)
-#define readw_(a) read16((uint32_t)a)
-#define readl_(a) read32((uint32_t)a)
-#define writeb_(val, addr) write8((uint32_t)addr, val)
-#define writew_(val, addr) write16((uint32_t)addr, val)
-#define writel_(val, addr) write32((uint32_t)addr, val)
+#define readb_(a) read8(a)
+#define readw_(a) read16(a)
+#define readl_(a) read32(a)
+#define writeb_(val, addr) write8(addr, val)
+#define writew_(val, addr) write16(addr, val)
+#define writel_(val, addr) write32(addr, val)
#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
diff --git a/src/southbridge/intel/esb6300/lpc.c b/src/southbridge/intel/esb6300/lpc.c
index b5b77ef..22bb150 100644
--- a/src/southbridge/intel/esb6300/lpc.c
+++ b/src/southbridge/intel/esb6300/lpc.c
@@ -242,7 +242,7 @@ static void lpc_init(struct device *dev)
value |= (1 << 8)|(1<<7);
value |= (6 << 0)|(1<<13)|(1<<11);
pci_write_config32(dev, 0xd0, value);
- setup_ioapic(IO_APIC_ADDR, 0); // don't rename IO APIC ID
+ setup_ioapic(VIO_APIC_VADDR, 0); // don't rename IO APIC ID
/* disable reset timer */
pci_write_config8(dev, 0xd4, 0x02);
diff --git a/src/southbridge/intel/esb6300/pic.c b/src/southbridge/intel/esb6300/pic.c
index e3fc2b2..c453ca3 100644
--- a/src/southbridge/intel/esb6300/pic.c
+++ b/src/southbridge/intel/esb6300/pic.c
@@ -23,7 +23,7 @@ static void pic_init(struct device *dev)
pci_write_config8(dev, 0x3c, 0xff);
/* Setup the ioapic */
- clear_ioapic(IO_APIC_ADDR + 0x10000);
+ clear_ioapic((void *)(IO_APIC_ADDR + 0x10000));
}
static void pic_read_resources(device_t dev)
diff --git a/src/southbridge/intel/fsp_bd82x6x/azalia.c b/src/southbridge/intel/fsp_bd82x6x/azalia.c
index 7a280c5..f4988d6 100644
--- a/src/southbridge/intel/fsp_bd82x6x/azalia.c
+++ b/src/southbridge/intel/fsp_bd82x6x/azalia.c
@@ -34,7 +34,7 @@
typedef struct southbridge_intel_bd82x6x_config config_t;
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
@@ -63,7 +63,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
return 0;
}
-static int codec_detect(u32 base)
+static int codec_detect(u8 *base)
{
u8 reg8;
@@ -72,7 +72,8 @@ static int codec_detect(u32 base)
goto no_codec;
/* Write back the value once reset bit is set. */
- write16(base + 0x0, read16(base + 0x0));
+ write16(base + 0x0,
+ read16(base + 0x0));
/* Read in Codec location (BAR + 0xe)[2..0]*/
reg8 = read8(base + 0xe);
@@ -118,7 +119,7 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
* no response would imply that the codec is non-operative
*/
-static int wait_for_ready(u32 base)
+static int wait_for_ready(u8 *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -126,7 +127,7 @@ static int wait_for_ready(u32 base)
int timeout = 50;
while(timeout--) {
- u32 reg32 = read32(base + HDA_ICII_REG);
+ u32 reg32 = read32(base + HDA_ICII_REG);
if (!(reg32 & HDA_ICII_BUSY))
return 0;
udelay(1);
@@ -141,7 +142,7 @@ static int wait_for_ready(u32 base)
* is non-operative
*/
-static int wait_for_valid(u32 base)
+static int wait_for_valid(u8 *base)
{
u32 reg32;
@@ -165,7 +166,7 @@ static int wait_for_valid(u32 base)
return -1;
}
-static void codec_init(struct device *dev, u32 base, int addr)
+static void codec_init(struct device *dev, u8 *base, int addr)
{
u32 reg32;
const u32 *verb;
@@ -213,7 +214,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
}
-static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
+static void codecs_init(struct device *dev, u8 *base, u32 codec_mask)
{
int i;
for (i = 3; i >= 0; i--) {
@@ -234,7 +235,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
static void azalia_init(struct device *dev)
{
- u32 base;
+ u8 *base;
struct resource *res;
u32 codec_mask;
u8 reg8;
@@ -248,7 +249,7 @@ static void azalia_init(struct device *dev)
// NOTE this will break as soon as the Azalia get's a bar above
// 4G. Is there anything we can do about it?
- base = (u32)res->base;
+ base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
if (RCBA32(0x2030) & (1 << 31)) {
diff --git a/src/southbridge/intel/fsp_bd82x6x/bootblock.c b/src/southbridge/intel/fsp_bd82x6x/bootblock.c
index 9b3e97a..c42a797 100644
--- a/src/southbridge/intel/fsp_bd82x6x/bootblock.c
+++ b/src/southbridge/intel/fsp_bd82x6x/bootblock.c
@@ -58,7 +58,7 @@ static void enable_port80_on_lpc(void)
pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
/* Enable port 80 POST on LPC */
- pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1);
+ pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
volatile u32 *gcs = (volatile u32 *)(DEFAULT_RCBA + GCS);
u32 reg32 = *gcs;
reg32 = reg32 & ~0x04;
diff --git a/src/southbridge/intel/fsp_bd82x6x/early_init.c b/src/southbridge/intel/fsp_bd82x6x/early_init.c
index c89395d..7b630f4 100644
--- a/src/southbridge/intel/fsp_bd82x6x/early_init.c
+++ b/src/southbridge/intel/fsp_bd82x6x/early_init.c
@@ -143,7 +143,7 @@ static void sandybridge_setup_bars(void)
{
/* Setting up Southbridge. */
printk(BIOS_DEBUG, "Setting up static southbridge registers...");
- pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c
index 5326eb5..bcaeeeb 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me.c
@@ -63,7 +63,7 @@ static const char *me_bios_path_values[] = {
#endif
/* MMIO base address for MEI interface */
-static u32 mei_base_address;
+static u32 *mei_base_address;
#if CONFIG_DEBUG_INTEL_ME
static void mei_dump(void *ptr, int dword, int offset, const char *type)
@@ -105,7 +105,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type)
static inline void mei_read_dword_ptr(void *ptr, int offset)
{
- u32 dword = read32(mei_base_address + offset);
+ u32 dword = read32(mei_base_address + (offset/sizeof(u32)));
memcpy(ptr, &dword, sizeof(dword));
mei_dump(ptr, dword, offset, "READ");
}
@@ -114,7 +114,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
- write32(mei_base_address + offset, dword);
+ write32(mei_base_address + (offset/sizeof(u32)), dword);
mei_dump(ptr, dword, offset, "WRITE");
}
@@ -144,13 +144,13 @@ static inline void read_me_csr(struct mei_csr *csr)
static inline void write_cb(u32 dword)
{
- write32(mei_base_address + MEI_H_CB_WW, dword);
+ write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword);
mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
}
static inline u32 read_cb(void)
{
- u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
+ u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32)));
mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
return dword;
}
@@ -500,11 +500,11 @@ static void intel_me7_finalize_smm(void)
struct me_hfs hfs;
u32 reg32;
- mei_base_address =
- pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
+ mei_base_address = (u32 *)
+ (pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */
- if (!mei_base_address || mei_base_address == 0xfffffff0)
+ if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)
return;
/* Make sure ME is in a mode that expects EOP */
@@ -626,7 +626,7 @@ static int intel_mei_setup(device_t dev)
printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
return -1;
}
- mei_base_address = res->base;
+ mei_base_address = res2mmio(res, 0, 0);
/* Ensure Memory and Bus Master bits are set */
reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
index d673ac7..9af5f93 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
@@ -64,7 +64,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data);
#endif
/* MMIO base address for MEI interface */
-static u32 mei_base_address;
+static u32 *mei_base_address;
#if CONFIG_DEBUG_INTEL_ME
static void mei_dump(void *ptr, int dword, int offset, const char *type)
@@ -106,7 +106,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type)
static inline void mei_read_dword_ptr(void *ptr, int offset)
{
- u32 dword = read32(mei_base_address + offset);
+ u32 dword = read32(mei_base_address + (offset/sizeof(u32)));
memcpy(ptr, &dword, sizeof(dword));
mei_dump(ptr, dword, offset, "READ");
}
@@ -115,7 +115,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
- write32(mei_base_address + offset, dword);
+ write32(mei_base_address + (offset/sizeof(u32)), dword);
mei_dump(ptr, dword, offset, "WRITE");
}
@@ -145,13 +145,13 @@ static inline void read_me_csr(struct mei_csr *csr)
static inline void write_cb(u32 dword)
{
- write32(mei_base_address + MEI_H_CB_WW, dword);
+ write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword);
mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
}
static inline u32 read_cb(void)
{
- u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
+ u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32)));
mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
return dword;
}
@@ -494,11 +494,11 @@ void intel_me8_finalize_smm(void)
struct me_hfs hfs;
u32 reg32;
- mei_base_address =
- pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
+ mei_base_address = (u32 *)
+ (pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */
- if (!mei_base_address || mei_base_address == 0xfffffff0)
+ if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)
return;
/* Make sure ME is in a mode that expects EOP */
@@ -613,7 +613,7 @@ static int intel_mei_setup(device_t dev)
printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
return -1;
}
- mei_base_address = res->base;
+ mei_base_address = (u32 *)(uintptr_t)res->base;
/* Ensure Memory and Bus Master bits are set */
reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.h b/src/southbridge/intel/fsp_bd82x6x/pch.h
index a06ca74..c1e9b71 100644
--- a/src/southbridge/intel/fsp_bd82x6x/pch.h
+++ b/src/southbridge/intel/fsp_bd82x6x/pch.h
@@ -48,7 +48,11 @@
#define DEFAULT_GPIOBASE 0x0480
#define DEFAULT_PMBASE 0x0400
+#ifndef __ACPI__
+#define DEFAULT_RCBA ((u8 *)0xfed1c000)
+#else
#define DEFAULT_RCBA 0xfed1c000
+#endif
#ifndef __ACPI__
#define DEBUG_PERIODIC_SMIS 0
diff --git a/src/southbridge/intel/fsp_bd82x6x/sata.c b/src/southbridge/intel/fsp_bd82x6x/sata.c
index 591bdbc..ff0e20b 100644
--- a/src/southbridge/intel/fsp_bd82x6x/sata.c
+++ b/src/southbridge/intel/fsp_bd82x6x/sata.c
@@ -57,7 +57,7 @@ static void sata_init(struct device *dev)
reg16 &= ~PCI_COMMAND_MEMORY;
pci_write_config16(dev, PCI_COMMAND, reg16);
} else if(config->sata_ahci) {
- u32 abar;
+ u32 *abar;
printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
@@ -66,12 +66,12 @@ static void sata_init(struct device *dev)
pci_write_config8(dev, INTR_LN, 0x0a);
/* Initialize AHCI memory-mapped space */
- abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
- printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
+ abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+ printk(BIOS_DEBUG, "ABAR: %p\n", abar);
/* Enable AHCI Mode */
- reg32 = read32(abar + 0x04);
+ reg32 = read32(abar + 0x01);
reg32 |= (1 << 31);
- write32(abar + 0x04, reg32);
+ write32(abar + 0x01, reg32);
} else {
printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c
index 844f4b8..e4e7071 100644
--- a/src/southbridge/intel/fsp_rangeley/early_init.c
+++ b/src/southbridge/intel/fsp_rangeley/early_init.c
@@ -34,15 +34,15 @@ static void rangeley_setup_bars(void)
{
/* Setting up Southbridge. */
printk(BIOS_DEBUG, "Setting up static southbridge registers...");
- pci_write_config32(LPC_BDF, RCBA, DEFAULT_RCBA | RCBA_ENABLE);
+ pci_write_config32(LPC_BDF, RCBA, (uintptr_t)DEFAULT_RCBA | RCBA_ENABLE);
pci_write_config32(LPC_BDF, ABASE, DEFAULT_ABASE | SET_BAR_ENABLE);
pci_write_config32(LPC_BDF, PBASE, DEFAULT_PBASE | SET_BAR_ENABLE);
printk(BIOS_DEBUG, " done.\n");
printk(BIOS_DEBUG, "Disabling Watchdog timer...");
/* Disable the watchdog reboot and turn off the watchdog timer */
- write8(DEFAULT_PBASE + PMC_CFG, read8(DEFAULT_PBASE + PMC_CFG) |
- NO_REBOOT); // disable reboot on timer trigger
+ write8((void *)(DEFAULT_PBASE + PMC_CFG),
+ read8((void *)(DEFAULT_PBASE + PMC_CFG)) | NO_REBOOT); // disable reboot on timer trigger
outw(DEFAULT_ABASE + TCO1_CNT, inw(DEFAULT_ABASE + TCO1_CNT) |
TCO_TMR_HALT); // disable watchdog timer
@@ -54,7 +54,7 @@ static void reset_rtc(void)
{
uint32_t pbase = pci_read_config32(LPC_BDF, PBASE) &
0xfffffff0;
- uint32_t gen_pmcon1 = read32(pbase + GEN_PMCON1);
+ uint32_t gen_pmcon1 = read32((void *)(pbase + GEN_PMCON1));
int rtc_failed = !!(gen_pmcon1 & RPS);
if (rtc_failed) {
@@ -63,7 +63,8 @@ static void reset_rtc(void)
coreboot_dmi_date);
/* Clear the power failure flag */
- write32(DEFAULT_PBASE + GEN_PMCON1, gen_pmcon1 & ~RPS);
+ write32((void *)(DEFAULT_PBASE + GEN_PMCON1),
+ gen_pmcon1 & ~RPS);
}
cmos_init(rtc_failed);
diff --git a/src/southbridge/intel/fsp_rangeley/gpio.c b/src/southbridge/intel/fsp_rangeley/gpio.c
index 8569b96..6ea9c2e 100644
--- a/src/southbridge/intel/fsp_rangeley/gpio.c
+++ b/src/southbridge/intel/fsp_rangeley/gpio.c
@@ -30,7 +30,7 @@
void setup_soc_gpios(const struct soc_gpio_map *gpio)
{
u16 gpiobase = pci_read_config16(SOC_LPC_DEV, GBASE) & ~0xf;
- u32 cfiobase = pci_read_config32(SOC_LPC_DEV, IOBASE) & ~0xf;
+ u32 *cfiobase = (u32 *)(pci_read_config32(SOC_LPC_DEV, IOBASE) & ~0xf);
u32 cfio_cnt = 0;
@@ -67,30 +67,30 @@ void setup_soc_gpios(const struct soc_gpio_map *gpio)
/* GPIO PAD settings */
/* CFIO Core Well Set 1 */
if ((gpio->core.cfio_init != NULL) || (gpio->core.cfio_entrynum != 0)) {
- write32(cfiobase + 0x0700, (u32)0x01001002);
+ write32(cfiobase + (0x0700 / sizeof(u32)), (u32)0x01001002);
for(cfio_cnt = 0; cfio_cnt < gpio->core.cfio_entrynum; cfio_cnt++) {
if (!((u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0))
continue;
- write32(cfiobase + CFIO_PAD_CONF0 + (16*cfio_cnt), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0);
- write32(cfiobase + CFIO_PAD_CONF1 + (16*cfio_cnt), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_1);
- write32(cfiobase + CFIO_PAD_VAL + (16*cfio_cnt), (u32)gpio->core.cfio_init[cfio_cnt].pad_val);
- write32(cfiobase + CFIO_PAD_DFT + (16*cfio_cnt), (u32)gpio->core.cfio_init[cfio_cnt].pad_dft);
+ write32(cfiobase + ((CFIO_PAD_CONF0 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0);
+ write32(cfiobase + ((CFIO_PAD_CONF1 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_1);
+ write32(cfiobase + ((CFIO_PAD_VAL + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_val);
+ write32(cfiobase + ((CFIO_PAD_DFT + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_dft);
}
- write32(cfiobase + 0x0700, (u32)0x01041002);
+ write32(cfiobase + (0x0700 / sizeof(u32)), (u32)0x01041002);
}
/* CFIO SUS Well Set 1 */
if ((gpio->sus.cfio_init != NULL) || (gpio->sus.cfio_entrynum != 0)) {
- write32(cfiobase + 0x1700, (u32)0x01001002);
+ write32(cfiobase + (0x1700 / sizeof(u32)), (u32)0x01001002);
for(cfio_cnt = 0; cfio_cnt < gpio->sus.cfio_entrynum; cfio_cnt++) {
if (!((u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0))
continue;
- write32(cfiobase + CFIO_PAD_CONF0 + 0x1000 + (16*cfio_cnt), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0);
- write32(cfiobase + CFIO_PAD_CONF1 + 0x1000 + (16*cfio_cnt), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_1);
- write32(cfiobase + CFIO_PAD_VAL + 0x1000 + (16*cfio_cnt), (u32)gpio->sus.cfio_init[cfio_cnt].pad_val);
- write32(cfiobase + CFIO_PAD_DFT + 0x1000 + (16*cfio_cnt), (u32)gpio->sus.cfio_init[cfio_cnt].pad_dft);
+ write32(cfiobase + ((CFIO_PAD_CONF0 + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0);
+ write32(cfiobase + ((CFIO_PAD_CONF1 + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_1);
+ write32(cfiobase + ((CFIO_PAD_VAL + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_val);
+ write32(cfiobase + ((CFIO_PAD_DFT + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_dft);
}
- write32(cfiobase + 0x1700, (u32)0x01041002);
+ write32(cfiobase + (0x1700 / sizeof(u32)), (u32)0x01041002);
}
}
diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c
index 9644067..8f29670 100644
--- a/src/southbridge/intel/fsp_rangeley/lpc.c
+++ b/src/southbridge/intel/fsp_rangeley/lpc.c
@@ -52,7 +52,7 @@ static void soc_enable_apic(struct device *dev)
u32 reg32;
volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
- u32 ilb_base = pci_read_config32(dev, IBASE) & ~0x0f;
+ u32 *ilb_base = (u32 *)(pci_read_config32(dev, IBASE) & ~0x0f);
/*
* Enable ACPI I/O and power management.
@@ -91,9 +91,9 @@ static void soc_enable_apic(struct device *dev)
static void soc_enable_serial_irqs(struct device *dev)
{
- u32 ibase;
+ u8 *ibase;
- ibase = pci_read_config32(dev, IBASE) & ~0xF;
+ ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF);
/* Set packet length and toggle silent mode bit for one frame. */
write8(ibase + ILB_SERIRQ_CNTL, (1 << 7));
@@ -206,10 +206,10 @@ static void soc_pirq_init(device_t dev)
{
int i, j;
int pirq;
- const u32 ibase = pci_read_config32(dev, IBASE) & ~0xF;
- const unsigned long pr_base = ibase + 0x08;
- const unsigned long ir_base = ibase + 0x20;
- const unsigned long actl = ibase;
+ u8 *ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF);
+ u8 *pr_base = ibase + 0x08;
+ u16 *ir_base = (u16 *)(ibase + 0x20);
+ u32 *actl = (u32 *)ibase;
const struct rangeley_irq_route *ir = &global_rangeley_irq_route;
/* Set up the PIRQ PIC routing based on static config. */
@@ -226,7 +226,7 @@ static void soc_pirq_init(device_t dev)
printk(BIOS_SPEW, "\t\t\tPIRQ[A-H] routed to each INT_PIN[A-D]\n"
"Dev\tINTA (IRQ)\tINTB (IRQ)\tINTC (IRQ)\tINTD (IRQ)\n");
for (i = 0; i < NUM_OF_PCI_DEVS; i++) {
- write16(ir_base + i*sizeof(ir->pcidev[i]), ir->pcidev[i]);
+ write16(ir_base + i, ir->pcidev[i]);
/* If the entry is more than just 0, print it out */
if(ir->pcidev[i]) {
@@ -293,10 +293,10 @@ static void soc_power_options(device_t dev)
/* Disable the HPET, Clear the counter, and re-enable it. */
static void enable_hpet(void)
{
- write8(HPET_GCFG, 0x00);
- write32(HPET_MCV, 0x00000000);
- write32(HPET_MCV + 0x04, 0x00000000);
- write8(HPET_GCFG, 0x01);
+ write8((u8 *)HPET_GCFG, 0x00);
+ write32((u32 *)HPET_MCV, 0x00000000);
+ write32((u32 *)(HPET_MCV + 0x04), 0x00000000);
+ write8((u8 *)HPET_GCFG, 0x01);
}
static void soc_disable_smm_only_flashing(struct device *dev)
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c
index fba9eb6..f8baa54 100644
--- a/src/southbridge/intel/fsp_rangeley/romstage.c
+++ b/src/southbridge/intel/fsp_rangeley/romstage.c
@@ -42,7 +42,7 @@
void main(FSP_INFO_HEADER *fsp_info_header)
{
uint32_t fd_mask = 0;
- uint32_t func_dis = DEFAULT_PBASE + PBASE_FUNC_DIS;
+ uint32_t *func_dis = (uint32_t *)(DEFAULT_PBASE + PBASE_FUNC_DIS);
/*
* Do not use the Serial Console before it is setup.
diff --git a/src/southbridge/intel/fsp_rangeley/sata.c b/src/southbridge/intel/fsp_rangeley/sata.c
index f672e4c..4648ac7 100644
--- a/src/southbridge/intel/fsp_rangeley/sata.c
+++ b/src/southbridge/intel/fsp_rangeley/sata.c
@@ -32,7 +32,7 @@ static void sata_init(struct device *dev)
{
u32 reg32;
u16 reg16;
- u32 abar;
+ u32 *abar;
/* Get the chip configuration */
config_t *config = dev->chip_info;
@@ -74,13 +74,13 @@ static void sata_init(struct device *dev)
pci_write_config16(dev, SATA_MAP, reg16);
/* Initialize AHCI memory-mapped space */
- abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
- printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
+ abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+ printk(BIOS_DEBUG, "ABAR: %p\n", abar);
/* Enable AHCI Mode */
- reg32 = read32(abar + 0x04);
+ reg32 = read32(abar + 0x01);
reg32 |= (1 << 31);
- write32(abar + 0x04, reg32);
+ write32(abar + 0x01, reg32);
} else {
printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
}
diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h
index 6db4b11..f1b1781 100644
--- a/src/southbridge/intel/fsp_rangeley/soc.h
+++ b/src/southbridge/intel/fsp_rangeley/soc.h
@@ -43,7 +43,11 @@
/* Southbridge internal device MEM BARs (Set to match FSP settings) */
#define DEFAULT_IBASE 0xfed08000
#define DEFAULT_PBASE 0xfed03000
+#ifndef __ACPI__
+#define DEFAULT_RCBA ((u8 *)0xfed1c000)
+#else
#define DEFAULT_RCBA 0xfed1c000
+#endif
#ifndef __ACPI__
#define DEBUG_PERIODIC_SMIS 0
diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c
index ee22019..b813d07 100644
--- a/src/southbridge/intel/fsp_rangeley/spi.c
+++ b/src/southbridge/intel/fsp_rangeley/spi.c
@@ -231,7 +231,7 @@ enum {
static u8 readb_(const void *addr)
{
- u8 v = read8((unsigned long)addr);
+ u8 v = read8(addr);
printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -239,7 +239,7 @@ static u8 readb_(const void *addr)
static u16 readw_(const void *addr)
{
- u16 v = read16((unsigned long)addr);
+ u16 v = read16(addr);
printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -247,7 +247,7 @@ static u16 readw_(const void *addr)
static u32 readl_(const void *addr)
{
- u32 v = read32((unsigned long)addr);
+ u32 v = read32(addr);
printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -255,14 +255,14 @@ static u32 readl_(const void *addr)
static void writeb_(u8 b, const void *addr)
{
- write8((unsigned long)addr, b);
+ write8(addr, b);
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writew_(u16 b, const void *addr)
{
- write16((unsigned long)addr, b);
+ write16(addr, b);
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
@@ -276,12 +276,12 @@ static void writel_(u32 b, const void *addr)
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
-#define readb_(a) read8((uint32_t)a)
-#define readw_(a) read16((uint32_t)a)
-#define readl_(a) read32((uint32_t)a)
-#define writeb_(val, addr) write8((uint32_t)addr, val)
-#define writew_(val, addr) write16((uint32_t)addr, val)
-#define writel_(val, addr) write32((uint32_t)addr, val)
+#define readb_(a) read8(a)
+#define readw_(a) read16(a)
+#define readl_(a) read32(a)
+#define writeb_(val, addr) write8(addr, val)
+#define writew_(val, addr) write16(addr, val)
+#define writel_(val, addr) write32(addr, val)
#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c
index ba74f30..737ec65 100644
--- a/src/southbridge/intel/i3100/lpc.c
+++ b/src/southbridge/intel/i3100/lpc.c
@@ -358,7 +358,7 @@ static void lpc_init(struct device *dev)
// TODO this code sets int 0 of the IOAPIC in Virtual Wire Mode
// (register 0x10/0x11) while the old code used int 1 (register 0x12)
// ... Why?
- setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IOAPIC ID
+ setup_ioapic(VIO_APIC_VADDR, 0); // Don't rename IOAPIC ID
/* Decode 0xffc00000 - 0xffffffff to fwh idsel 0 */
pci_write_config32(dev, 0xd0, 0x00000000);
diff --git a/src/southbridge/intel/i82801ax/lpc.c b/src/southbridge/intel/i82801ax/lpc.c
index 11519c1..aece452 100644
--- a/src/southbridge/intel/i82801ax/lpc.c
+++ b/src/southbridge/intel/i82801ax/lpc.c
@@ -103,13 +103,13 @@ static void i82801ax_enable_ioapic(struct device *dev)
pci_write_config32(dev, GEN_CNTL, reg32);
printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
- set_ioapic_id(IO_APIC_ADDR, 0x02);
+ set_ioapic_id(VIO_APIC_VADDR, 0x02);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
- io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
+ io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
}
static void i82801ax_enable_serial_irqs(struct device *dev)
diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c
index 278d65c..ee0b521 100644
--- a/src/southbridge/intel/i82801bx/lpc.c
+++ b/src/southbridge/intel/i82801bx/lpc.c
@@ -104,13 +104,13 @@ static void i82801bx_enable_ioapic(struct device *dev)
pci_write_config32(dev, GEN_CNTL, reg32);
printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
- set_ioapic_id(IO_APIC_ADDR, 0x02);
+ set_ioapic_id(VIO_APIC_VADDR, 0x02);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
- io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
+ io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
}
static void i82801bx_enable_serial_irqs(struct device *dev)
diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c
index f6c33b7..22671c3 100644
--- a/src/southbridge/intel/i82801cx/lpc.c
+++ b/src/southbridge/intel/i82801cx/lpc.c
@@ -41,13 +41,13 @@ static void i82801cx_enable_ioapic(struct device *dev)
pci_write_config32(dev, GEN_CNTL, reg32);
printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
- set_ioapic_id(IO_APIC_ADDR, 0x02);
+ set_ioapic_id(VIO_APIC_VADDR, 0x02);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
- io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
+ io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
}
// This is how interrupts are received from the Super I/O chip
diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c
index 1b23fad..83d6178 100644
--- a/src/southbridge/intel/i82801dx/lpc.c
+++ b/src/southbridge/intel/i82801dx/lpc.c
@@ -67,13 +67,13 @@ static void i82801dx_enable_ioapic(struct device *dev)
pci_write_config32(dev, GEN_CNTL, reg32);
printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
- set_ioapic_id(IO_APIC_ADDR, 0x02);
+ set_ioapic_id(VIO_APIC_VADDR, 0x02);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
- io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
+ io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
}
static void i82801dx_enable_serial_irqs(struct device *dev)
diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c
index 1823e65..0a2f6e3 100644
--- a/src/southbridge/intel/i82801ex/lpc.c
+++ b/src/southbridge/intel/i82801ex/lpc.c
@@ -281,7 +281,7 @@ static void lpc_init(struct device *dev)
i82801ex_general_cntl(dev);
/* IO APIC initialization. */
- setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IO APIC ID.
+ setup_ioapic(VIO_APIC_VADDR, 0); // Don't rename IO APIC ID.
i82801ex_enable_serial_irqs(dev);
diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c
index f6628e7..3d3d73e 100644
--- a/src/southbridge/intel/i82801gx/azalia.c
+++ b/src/southbridge/intel/i82801gx/azalia.c
@@ -34,7 +34,7 @@
typedef struct southbridge_intel_i82801gx_config config_t;
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
@@ -63,7 +63,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
return 0;
}
-static int codec_detect(u32 base)
+static int codec_detect(u8 *base)
{
u32 reg32;
@@ -114,7 +114,7 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
* no response would imply that the codec is non-operative
*/
-static int wait_for_ready(u32 base)
+static int wait_for_ready(u8 *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -122,7 +122,7 @@ static int wait_for_ready(u32 base)
int timeout = 50;
while(timeout--) {
- u32 reg32 = read32(base + HDA_ICII_REG);
+ u32 reg32 = read32(base + HDA_ICII_REG);
if (!(reg32 & HDA_ICII_BUSY))
return 0;
udelay(1);
@@ -137,7 +137,7 @@ static int wait_for_ready(u32 base)
* is non-operative
*/
-static int wait_for_valid(u32 base)
+static int wait_for_valid(u8 *base)
{
u32 reg32;
@@ -161,7 +161,7 @@ static int wait_for_valid(u32 base)
return -1;
}
-static void codec_init(struct device *dev, u32 base, int addr)
+static void codec_init(struct device *dev, u8 *base, int addr)
{
u32 reg32;
const u32 *verb;
@@ -205,7 +205,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
}
-static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
+static void codecs_init(struct device *dev, u8 *base, u32 codec_mask)
{
int i;
for (i = 2; i >= 0; i--) {
@@ -216,7 +216,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
static void azalia_init(struct device *dev)
{
- u32 base;
+ u8 *base;
struct resource *res;
u32 codec_mask;
u8 reg8;
@@ -297,7 +297,7 @@ static void azalia_init(struct device *dev)
// NOTE this will break as soon as the Azalia get's a bar above
// 4G. Is there anything we can do about it?
- base = (u32)res->base;
+ base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
codec_mask = codec_detect(base);
diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c
index d8e03b7..5954e6c 100644
--- a/src/southbridge/intel/i82801gx/bootblock.c
+++ b/src/southbridge/intel/i82801gx/bootblock.c
@@ -53,7 +53,7 @@ static void bootblock_southbridge_init(void)
enable_spi_prefetch();
/* Enable RCBA */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
/* Enable upper 128bytes of CMOS */
RCBA32(0x3400) = (1 << 2);
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index ee13b7d..4624841 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -32,7 +32,11 @@
#define DEFAULT_GPIOBASE 0x0480
#define DEFAULT_PMBASE 0x0500
+#ifndef __ACPI__
+#define DEFAULT_RCBA ((u8 *)0xfed1c000)
+#else
#define DEFAULT_RCBA 0xfed1c000
+#endif
#ifndef __ACPI__
#define DEBUG_PERIODIC_SMIS 0
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 6b9d11e..cbc0106 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -53,13 +53,13 @@ static void i82801gx_enable_ioapic(struct device *dev)
/* Enable ACPI I/O range decode */
pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
- set_ioapic_id(IO_APIC_ADDR, 0x02);
+ set_ioapic_id(VIO_APIC_VADDR, 0x02);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
- io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
+ io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
}
static void i82801gx_enable_serial_irqs(struct device *dev)
diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c
index bb176c7..161190b 100644
--- a/src/southbridge/intel/i82801gx/usb_ehci.c
+++ b/src/southbridge/intel/i82801gx/usb_ehci.c
@@ -29,7 +29,7 @@
static void usb_ehci_init(struct device *dev)
{
struct resource *res;
- u32 base;
+ u8 *base;
u32 reg32;
u8 reg8;
@@ -50,7 +50,7 @@ static void usb_ehci_init(struct device *dev)
/* Clear any pending port changes */
res = find_resource(dev, 0x10);
- base = res->base;
+ base = res2mmio(res, 0, 0);
reg32 = read32(base + 0x24) | (1 << 2);
write32(base + 0x24, reg32);
diff --git a/src/southbridge/intel/i82801ix/dmi_setup.c b/src/southbridge/intel/i82801ix/dmi_setup.c
index 3d9df6d..bca109a 100644
--- a/src/southbridge/intel/i82801ix/dmi_setup.c
+++ b/src/southbridge/intel/i82801ix/dmi_setup.c
@@ -87,7 +87,7 @@ void i82801ix_dmi_setup(void)
RCBA8(RCBA_ULD + 3) = 1;
RCBA8(RCBA_ULD + 2) = 1;
/* Set target rcrb base address, i.e. DMIBAR. */
- RCBA32(RCBA_ULBA) = DEFAULT_DMIBAR;
+ RCBA32(RCBA_ULBA) = (uintptr_t)DEFAULT_DMIBAR;
/* Enable ASPM. */
if (LPC_IS_MOBILE(PCI_DEV(0, 0x1f, 0))) {
diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c
index bd6548c..1e3b517 100644
--- a/src/southbridge/intel/i82801ix/early_init.c
+++ b/src/southbridge/intel/i82801ix/early_init.c
@@ -26,7 +26,7 @@ void i82801ix_early_init(void)
const device_t d31f0 = PCI_DEV(0, 0x1f, 0);
/* Set up RCBA. */
- pci_write_config32(d31f0, D31F0_RCBA, DEFAULT_RCBA | 1);
+ pci_write_config32(d31f0, D31F0_RCBA, (uintptr_t)DEFAULT_RCBA | 1);
/* Set up PMBASE. */
pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1);
diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c
index dd817b9..69c558d 100644
--- a/src/southbridge/intel/i82801ix/hdaudio.c
+++ b/src/southbridge/intel/i82801ix/hdaudio.c
@@ -35,7 +35,7 @@
typedef struct southbridge_intel_i82801ix_config config_t;
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
@@ -64,7 +64,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
return 0;
}
-static int codec_detect(u32 base)
+static int codec_detect(u8 *base)
{
u32 reg32;
@@ -115,7 +115,7 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
* no response would imply that the codec is non-operative
*/
-static int wait_for_ready(u32 base)
+static int wait_for_ready(u8 *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -123,7 +123,7 @@ static int wait_for_ready(u32 base)
int timeout = 50;
while(timeout--) {
- u32 reg32 = read32(base + HDA_ICII_REG);
+ u32 reg32 = read32(base + HDA_ICII_REG);
if (!(reg32 & HDA_ICII_BUSY))
return 0;
udelay(1);
@@ -138,7 +138,7 @@ static int wait_for_ready(u32 base)
* is non-operative
*/
-static int wait_for_valid(u32 base)
+static int wait_for_valid(u8 *base)
{
u32 reg32;
@@ -162,7 +162,7 @@ static int wait_for_valid(u32 base)
return -1;
}
-static void codec_init(struct device *dev, u32 base, int addr)
+static void codec_init(struct device *dev, u8 *base, int addr)
{
u32 reg32;
const u32 *verb;
@@ -206,7 +206,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
}
-static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
+static void codecs_init(struct device *dev, u8 *base, u32 codec_mask)
{
int i;
for (i = 2; i >= 0; i--) {
@@ -227,7 +227,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
static void azalia_init(struct device *dev)
{
- u32 base;
+ u8 *base;
struct resource *res;
u32 codec_mask;
u8 reg8;
@@ -281,7 +281,7 @@ static void azalia_init(struct device *dev)
// NOTE this will break as soon as the Azalia get's a bar above
// 4G. Is there anything we can do about it?
- base = (u32)res->base;
+ base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
codec_mask = codec_detect(base);
diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h
index d8dc077..10b2717 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.h
+++ b/src/southbridge/intel/i82801ix/i82801ix.h
@@ -27,8 +27,13 @@
#endif
#endif
-#define DEFAULT_TBAR 0xfed1b000
+#define DEFAULT_TBAR ((u8 *)0xfed1b000)
+#ifndef __ACPI__
+#define DEFAULT_RCBA ((u8 *)0xfed1c000)
+#else
#define DEFAULT_RCBA 0xfed1c000
+#endif
+
#ifdef CONFIG_BOARD_EMULATION_QEMU_X86_Q35
/*
* Qemu has the fw_cfg interface at 0x510. Move the pmbase to a
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index 6038eff..0ba33d6 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -62,7 +62,7 @@ static void i82801ix_enable_apic(struct device *dev)
*ioapic_index = 0x01;
*ioapic_data = reg32;
- setup_ioapic(IO_APIC_ADDR, 2); /* ICH7 code uses id 2. */
+ setup_ioapic(VIO_APIC_VADDR, 2); /* ICH7 code uses id 2. */
}
static void i82801ix_enable_serial_irqs(struct device *dev)
diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c
index 10c8a2b..f65eba2 100644
--- a/src/southbridge/intel/i82801ix/sata.c
+++ b/src/southbridge/intel/i82801ix/sata.c
@@ -36,8 +36,8 @@ static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map,
u32 reg32;
/* Initialize AHCI memory-mapped space */
- const u32 abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
- printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
+ u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+ printk(BIOS_DEBUG, "ABAR: %p\n", abar);
/* Set AHCI access mode.
No other ABAR registers should be accessed before this. */
@@ -67,7 +67,7 @@ static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map,
for (i = 0; i < 6; ++i) {
if (((i == 2) || (i == 3)) && is_mobile)
continue;
- const u32 addr = abar + 0x118 + (i * 0x80);
+ u8 *addr = abar + 0x118 + (i * 0x80);
write32(addr, read32(addr));
}
}
diff --git a/src/southbridge/intel/i82801ix/thermal.c b/src/southbridge/intel/i82801ix/thermal.c
index 3245a27..84afe93 100644
--- a/src/southbridge/intel/i82801ix/thermal.c
+++ b/src/southbridge/intel/i82801ix/thermal.c
@@ -34,7 +34,7 @@ static void thermal_init(struct device *dev)
u8 reg8;
u32 reg32;
- pci_write_config32(dev, 0x10, DEFAULT_TBAR);
+ pci_write_config32(dev, 0x10, (uintptr_t)DEFAULT_TBAR);
reg32 = pci_read_config32(dev, 0x04);
pci_write_config32(dev, 0x04, reg32 | (1 << 1));
diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c
index 314a1b1..2275c7a 100644
--- a/src/southbridge/intel/ibexpeak/azalia.c
+++ b/src/southbridge/intel/ibexpeak/azalia.c
@@ -33,7 +33,7 @@
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
@@ -62,7 +62,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
return 0;
}
-static int codec_detect(u32 base)
+static int codec_detect(u8 *base)
{
u8 reg8;
@@ -71,7 +71,8 @@ static int codec_detect(u32 base)
goto no_codec;
/* Write back the value once reset bit is set. */
- write16(base + 0x0, read16(base + 0x0));
+ write16(base + 0x0,
+ read16(base + 0x0));
/* Read in Codec location (BAR + 0xe)[2..0]*/
reg8 = read8(base + 0xe);
@@ -112,14 +113,14 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
* no response would imply that the codec is non-operative
*/
-static int wait_for_ready(u32 base)
+static int wait_for_ready(u8 *base)
{
/* Use a 1msec timeout */
int timeout = 1000;
while(timeout--) {
- u32 reg32 = read32(base + HDA_ICII_REG);
+ u32 reg32 = read32(base + HDA_ICII_REG);
if (!(reg32 & HDA_ICII_BUSY))
return 0;
udelay(1);
@@ -134,7 +135,7 @@ static int wait_for_ready(u32 base)
* is non-operative
*/
-static int wait_for_valid(u32 base)
+static int wait_for_valid(u8 *base)
{
u32 reg32;
@@ -157,7 +158,7 @@ static int wait_for_valid(u32 base)
return -1;
}
-static void codec_init(struct device *dev, u32 base, int addr)
+static void codec_init(struct device *dev, u8 *base, int addr)
{
u32 reg32;
const u32 *verb;
@@ -205,7 +206,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
}
-static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
+static void codecs_init(struct device *dev, u8 *base, u32 codec_mask)
{
int i;
for (i = 3; i >= 0; i--) {
@@ -226,7 +227,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
static void azalia_init(struct device *dev)
{
- u32 base;
+ u8 *base;
struct resource *res;
u32 codec_mask;
u8 reg8;
@@ -240,7 +241,7 @@ static void azalia_init(struct device *dev)
// NOTE this will break as soon as the Azalia get's a bar above
// 4G. Is there anything we can do about it?
- base = (u32)res->base;
+ base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
if (RCBA32(0x2030) & (1 << 31)) {
diff --git a/src/southbridge/intel/ibexpeak/early_thermal.c b/src/southbridge/intel/ibexpeak/early_thermal.c
index d23749e..e765943 100644
--- a/src/southbridge/intel/ibexpeak/early_thermal.c
+++ b/src/southbridge/intel/ibexpeak/early_thermal.c
@@ -43,11 +43,12 @@ void early_thermal_init(void)
/* Perform init. */
/* Configure TJmax. */
msr = rdmsr(MSR_TEMPERATURE_TARGET);
- write16(0x40000012, ((msr.lo >> 16) & 0xff) << 6);
+ write16((u16 *)0x40000012, ((msr.lo >> 16) & 0xff) << 6);
/* Northbridge temperature slope and offset. */
- write16(0x40000016, 0x7746);
+ write16((u16 *)0x40000016, 0x7746);
/* Enable thermal data reporting, processor, PCH and northbridge. */
- write16(0x4000001a, (read16(0x4000001a) & ~0xf) | 0x10f0);
+ write16((u16 *)0x4000001a,
+ (read16((u16 *)0x4000001a) & ~0xf) | 0x10f0);
/* Disable temporary BAR. */
pci_write_config32(dev, 0x40,
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 2124711..db73b0a 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -59,16 +59,16 @@ static void pch_enable_ioapic(struct device *dev)
/* Enable ACPI I/O range decode */
pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
- set_ioapic_id(IO_APIC_ADDR, 0x01);
+ set_ioapic_id(VIO_APIC_VADDR, 0x01);
/* affirm full set of redirection table entries ("write once") */
- reg32 = io_apic_read(IO_APIC_ADDR, 0x01);
- io_apic_write(IO_APIC_ADDR, 0x01, reg32);
+ reg32 = io_apic_read(VIO_APIC_VADDR, 0x01);
+ io_apic_write(VIO_APIC_VADDR, 0x01, reg32);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
- io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
+ io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
}
static void pch_enable_serial_irqs(struct device *dev)
@@ -394,7 +394,7 @@ static void enable_hpet(void)
reg32 &= ~(3 << 0);
RCBA32(HPTC) = reg32;
- write32(0xfed00010, read32(0xfed00010) | 1);
+ write32((u32 *)0xfed00010, read32((u32 *)0xfed00010) | 1);
}
static void enable_clock_gating(device_t dev)
diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c
index f94b17f..9592b23 100644
--- a/src/southbridge/intel/ibexpeak/me.c
+++ b/src/southbridge/intel/ibexpeak/me.c
@@ -63,7 +63,7 @@ static const char *me_bios_path_values[] = {
#endif
/* MMIO base address for MEI interface */
-static u32 mei_base_address;
+static u32 *mei_base_address;
#if CONFIG_DEBUG_INTEL_ME
static void mei_dump(void *ptr, int dword, int offset, const char *type)
@@ -105,7 +105,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type)
static inline void mei_read_dword_ptr(void *ptr, int offset)
{
- u32 dword = read32(mei_base_address + offset);
+ u32 dword = read32(mei_base_address + (offset/sizeof(u32)));
memcpy(ptr, &dword, sizeof(dword));
mei_dump(ptr, dword, offset, "READ");
}
@@ -114,7 +114,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
- write32(mei_base_address + offset, dword);
+ write32(mei_base_address + (offset/sizeof(u32)), dword);
mei_dump(ptr, dword, offset, "WRITE");
}
@@ -145,13 +145,13 @@ static inline void read_me_csr(struct mei_csr *csr)
static inline void write_cb(u32 dword)
{
- write32(mei_base_address + MEI_H_CB_WW, dword);
+ write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword);
mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
}
static inline u32 read_cb(void)
{
- u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
+ u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32)));
mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
return dword;
}
@@ -382,11 +382,11 @@ static void intel_me7_finalize_smm(void)
struct me_hfs hfs;
u32 reg32;
- mei_base_address =
- pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
+ mei_base_address = (u32 *)
+ (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */
- if (!mei_base_address || mei_base_address == 0xfffffff0)
+ if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)
return;
/* Make sure ME is in a mode that expects EOP */
@@ -508,7 +508,7 @@ static int intel_mei_setup(device_t dev)
printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
return -1;
}
- mei_base_address = res->base;
+ mei_base_address = (u32 *)(uintptr_t)res->base;
/* Ensure Memory and Bus Master bits are set */
reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index bd94689..12e9345 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -48,7 +48,11 @@
#define DEFAULT_GPIOBASE 0x0480
#define DEFAULT_PMBASE 0x0500
+#ifndef __ACPI__
+#define DEFAULT_RCBA ((u8 *)0xfed1c000)
+#else
#define DEFAULT_RCBA 0xfed1c000
+#endif
#ifndef __ACPI__
#define DEBUG_PERIODIC_SMIS 0
diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c
index 5f3c4d3..c8450ad 100644
--- a/src/southbridge/intel/ibexpeak/sata.c
+++ b/src/southbridge/intel/ibexpeak/sata.c
@@ -67,7 +67,7 @@ static void sata_init(struct device *dev)
if (sata_mode == 0) {
/* AHCI */
- u32 abar;
+ u32 *abar;
printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
@@ -103,8 +103,8 @@ static void sata_init(struct device *dev)
pci_write_config32(dev, 0x98, 0x00590200);
/* Initialize AHCI memory-mapped space */
- abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
- printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
+ abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+ printk(BIOS_DEBUG, "ABAR: %p\n", abar);
/* CAP (HBA Capabilities) : enable power management */
reg32 = read32(abar + 0x00);
reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS
@@ -118,16 +118,16 @@ static void sata_init(struct device *dev)
write32(abar + 0x00, reg32);
/* PI (Ports implemented) */
write32(abar + 0x0c, config->sata_port_map);
- (void)read32(abar + 0x0c); /* Read back 1 */
- (void)read32(abar + 0x0c); /* Read back 2 */
+ (void)read32(abar + 0x03); /* Read back 1 */
+ (void)read32(abar + 0x03); /* Read back 2 */
/* CAP2 (HBA Capabilities Extended) */
- reg32 = read32(abar + 0x24);
+ reg32 = read32(abar + 0x09);
reg32 &= ~0x00000002;
- write32(abar + 0x24, reg32);
+ write32(abar + 0x09, reg32);
/* VSP (Vendor Specific Register */
- reg32 = read32(abar + 0xa0);
+ reg32 = read32(abar + 0x28);
reg32 &= ~0x00000005;
- write32(abar + 0xa0, reg32);
+ write32(abar + 0x28, reg32);
} else {
/* IDE */
printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c
index fa39626..c684955 100644
--- a/src/southbridge/intel/ibexpeak/thermal.c
+++ b/src/southbridge/intel/ibexpeak/thermal.c
@@ -28,21 +28,22 @@
static void thermal_init(struct device *dev)
{
struct resource *res;
-
+ u8 *base;
printk(BIOS_DEBUG, "Thermal init start.\n");
res = find_resource(dev, 0x10);
if (!res)
return;
- write32(res->base + 4, 0x3a2b);
- write8(res->base + 0xe, 0x40);
- write16(res->base + 0x56, 0xffff);
- write16(res->base + 0x64, 0xffff);
- write16(res->base + 0x66, 0xffff);
- write16(res->base + 0x68, 0xfa);
+ base = res2mmio(res, 0, 0);
+ write32(base + 4, 0x3a2b);
+ write8(base + 0xe, 0x40);
+ write16(base + 0x56, 0xffff);
+ write16(base + 0x64, 0xffff);
+ write16(base + 0x66, 0xffff);
+ write16(base + 0x68, 0xfa);
- write8(res->base + 1, 0xb8);
+ write8(base + 1, 0xb8);
printk(BIOS_DEBUG, "Thermal init done.\n");
}
diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c
index 868a068..6a48d13 100644
--- a/src/southbridge/intel/ibexpeak/usb_ehci.c
+++ b/src/southbridge/intel/ibexpeak/usb_ehci.c
@@ -60,8 +60,9 @@ static void usb_ehci_init(struct device *dev)
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
/* Number of ports and companion controllers. */
- reg32 = read32(res->base + 4);
- write32(res->base + 4, (reg32 & 0xfff00000) | 2);
+ reg32 = read32((u32 *)(uintptr_t)(res->base + 4));
+ write32((u32 *)(uintptr_t)(res->base + 4),
+ (reg32 & 0xfff00000) | 2);
}
/* Restore protection. */
diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c
index be056be..168b8d2 100644
--- a/src/southbridge/intel/lynxpoint/azalia.c
+++ b/src/southbridge/intel/lynxpoint/azalia.c
@@ -30,7 +30,7 @@
#include "pch.h"
#include "hda_verb.h"
-static void codecs_init(u32 base, u32 codec_mask)
+static void codecs_init(u8 *base, u32 codec_mask)
{
int i;
@@ -46,7 +46,7 @@ static void codecs_init(u32 base, u32 codec_mask)
hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs);
}
-static void azalia_pch_init(struct device *dev, u32 base)
+static void azalia_pch_init(struct device *dev, u8 *base)
{
u8 reg8;
u16 reg16;
@@ -131,7 +131,7 @@ static void azalia_pch_init(struct device *dev, u32 base)
static void azalia_init(struct device *dev)
{
- u32 base;
+ u8 *base;
struct resource *res;
u32 codec_mask;
u32 reg32;
@@ -141,8 +141,8 @@ static void azalia_init(struct device *dev)
if (!res)
return;
- base = (u32)res->base;
- printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
+ base = res2mmio(res, 0, 0);
+ printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
/* Set Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c
index 40c6bb8..9d9e7b3 100644
--- a/src/southbridge/intel/lynxpoint/bootblock.c
+++ b/src/southbridge/intel/lynxpoint/bootblock.c
@@ -53,7 +53,7 @@ static void map_rcba(void)
{
pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
- pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1);
+ pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
}
static void enable_port80_on_lpc(void)
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index 5378428..eabf548 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -52,7 +52,7 @@ int pch_is_lp(void)
static void pch_enable_bars(void)
{
/* Setting up Southbridge. In the northbridge code. */
- pci_write_config32(PCH_LPC_DEV, RCBA, DEFAULT_RCBA | 1);
+ pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1);
/* Enable ACPI BAR */
diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c
index 424deb5..8f38cce 100644
--- a/src/southbridge/intel/lynxpoint/hda_verb.c
+++ b/src/southbridge/intel/lynxpoint/hda_verb.c
@@ -28,7 +28,7 @@
/**
* Set bits in a register and wait for status
*/
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
@@ -60,7 +60,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
/**
* Probe for supported codecs
*/
-int hda_codec_detect(u32 base)
+int hda_codec_detect(u8 *base)
{
u8 reg8;
@@ -91,7 +91,7 @@ no_codec:
* Wait 50usec for the codec to indicate it is ready
* no response would imply that the codec is non-operative
*/
-static int hda_wait_for_ready(u32 base)
+static int hda_wait_for_ready(u8 *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -113,7 +113,7 @@ static int hda_wait_for_ready(u32 base)
* the previous command. No response would imply that the code
* is non-operative
*/
-static int hda_wait_for_valid(u32 base)
+static int hda_wait_for_valid(u8 *base)
{
u32 reg32;
@@ -185,7 +185,7 @@ static u32 hda_find_verb(u32 verb_table_bytes,
/**
* Write a supplied verb table
*/
-int hda_codec_write(u32 base, u32 size, const u32 *data)
+int hda_codec_write(u8 *base, u32 size, const u32 *data)
{
int i;
@@ -205,7 +205,7 @@ int hda_codec_write(u32 base, u32 size, const u32 *data)
/**
* Initialize codec, then find the verb table and write it
*/
-int hda_codec_init(u32 base, int addr, int verb_size, const u32 *verb_data)
+int hda_codec_init(u8 *base, int addr, int verb_size, const u32 *verb_data)
{
const u32 *verb;
u32 reg32, size;
diff --git a/src/southbridge/intel/lynxpoint/hda_verb.h b/src/southbridge/intel/lynxpoint/hda_verb.h
index 8b3d27e..52c1468 100644
--- a/src/southbridge/intel/lynxpoint/hda_verb.h
+++ b/src/southbridge/intel/lynxpoint/hda_verb.h
@@ -30,8 +30,8 @@
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
-int hda_codec_detect(u32 base);
-int hda_codec_write(u32 base, u32 size, const u32 *data);
-int hda_codec_init(u32 base, int addr, int verb_size, const u32 *verb_data);
+int hda_codec_detect(u8 *base);
+int hda_codec_write(u8 *base, u32 size, const u32 *data);
+int hda_codec_init(u8 *base, int addr, int verb_size, const u32 *verb_data);
#endif
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 563cb0a..d753bea 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -57,22 +57,22 @@ static void pch_enable_ioapic(struct device *dev)
/* Enable ACPI I/O range decode */
pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
- set_ioapic_id(IO_APIC_ADDR, 0x02);
+ set_ioapic_id(VIO_APIC_VADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */
- reg32 = io_apic_read(IO_APIC_ADDR, 0x01);
+ reg32 = io_apic_read(VIO_APIC_VADDR, 0x01);
if (pch_is_lp()) {
/* PCH-LP has 39 redirection entries */
reg32 &= ~0x00ff0000;
reg32 |= 0x00270000;
}
- io_apic_write(IO_APIC_ADDR, 0x01, reg32);
+ io_apic_write(VIO_APIC_VADDR, 0x01, reg32);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
- io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
+ io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
}
static void pch_enable_serial_irqs(struct device *dev)
@@ -608,9 +608,9 @@ static void pch_lpc_add_mmio_resources(device_t dev)
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* RCBA */
- if (DEFAULT_RCBA < default_decode_base) {
+ if ((uintptr_t)DEFAULT_RCBA < default_decode_base) {
res = new_resource(dev, RCBA);
- res->base = DEFAULT_RCBA;
+ res->base = (resource_t)(uintptr_t)DEFAULT_RCBA;
res->size = 16 * 1024;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED | IORESOURCE_RESERVE;
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index 9670bbb..e32a2d9 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -61,7 +61,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev);
#endif
/* MMIO base address for MEI interface */
-static u32 mei_base_address;
+static u32 *mei_base_address;
void intel_me_mbp_clear(device_t dev);
#if CONFIG_DEBUG_INTEL_ME
@@ -104,7 +104,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type)
static inline void mei_read_dword_ptr(void *ptr, int offset)
{
- u32 dword = read32(mei_base_address + offset);
+ u32 dword = read32(mei_base_address + (offset/sizeof(u32)));
memcpy(ptr, &dword, sizeof(dword));
mei_dump(ptr, dword, offset, "READ");
}
@@ -113,7 +113,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
- write32(mei_base_address + offset, dword);
+ write32(mei_base_address + (offset/sizeof(u32)), dword);
mei_dump(ptr, dword, offset, "WRITE");
}
@@ -141,13 +141,13 @@ static inline void read_me_csr(struct mei_csr *csr)
static inline void write_cb(u32 dword)
{
- write32(mei_base_address + MEI_H_CB_WW, dword);
+ write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword);
mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
}
static inline u32 read_cb(void)
{
- u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
+ u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32)));
mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
return dword;
}
@@ -577,11 +577,11 @@ void intel_me_finalize_smm(void)
struct me_hfs hfs;
u32 reg32;
- mei_base_address =
- pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
+ mei_base_address = (u32 *)
+ (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */
- if (!mei_base_address || mei_base_address == 0xfffffff0)
+ if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)
return;
#if CONFIG_ME_MBP_CLEAR_LATE
@@ -745,7 +745,7 @@ static int intel_mei_setup(device_t dev)
printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
return -1;
}
- mei_base_address = res->base;
+ mei_base_address = (u32 *)(uintptr_t)res->base;
/* Ensure Memory and Bus Master bits are set */
reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 9b5cb6f..5ee7cd9 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -83,7 +83,11 @@
#endif
#define HPET_ADDR 0xfed00000
+#ifndef __ACPI__
+#define DEFAULT_RCBA ((u8 *)0xfed1c000)
+#else
#define DEFAULT_RCBA 0xfed1c000
+#endif
#ifndef __ACPI__
diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index 43a99c8..89a72f4 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -96,7 +96,7 @@ static void sata_init(struct device *dev)
pci_write_config32(dev, 0x94,
((config->sata_port_map ^ 0x3f) << 24) | 0x183);
} else if(config->sata_ahci) {
- u32 abar;
+ u32 *abar;
printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
@@ -156,8 +156,8 @@ static void sata_init(struct device *dev)
pci_write_config32(dev, 0x94, reg32);
/* Initialize AHCI memory-mapped space */
- abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
- printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
+ abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+ printk(BIOS_DEBUG, "ABAR: %p\n", abar);
/* CAP (HBA Capabilities) : enable power management */
reg32 = read32(abar + 0x00);
reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS
@@ -166,11 +166,11 @@ static void sata_init(struct device *dev)
reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY
write32(abar + 0x00, reg32);
/* PI (Ports implemented) */
- write32(abar + 0x0c, config->sata_port_map);
- (void) read32(abar + 0x0c); /* Read back 1 */
- (void) read32(abar + 0x0c); /* Read back 2 */
+ write32(abar + 0x03, config->sata_port_map);
+ (void) read32(abar + 0x03); /* Read back 1 */
+ (void) read32(abar + 0x03); /* Read back 2 */
/* CAP2 (HBA Capabilities Extended)*/
- reg32 = read32(abar + 0x24);
+ reg32 = read32(abar + 0x09);
/* Enable DEVSLP */
if (pch_is_lp()) {
if (config->sata_devslp_disable)
@@ -180,7 +180,7 @@ static void sata_init(struct device *dev)
} else {
reg32 &= ~0x00000002;
}
- write32(abar + 0x24, reg32);
+ write32(abar + 0x09, reg32);
} else {
printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c
index 75edf5c..398895a 100644
--- a/src/southbridge/intel/lynxpoint/serialio.c
+++ b/src/southbridge/intel/lynxpoint/serialio.c
@@ -32,9 +32,9 @@
/* Enable clock in PCI mode */
static void serialio_enable_clock(struct resource *bar0)
{
- u32 reg32 = read32(bar0->base + SIO_REG_PPR_CLOCK);
+ u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0));
reg32 |= SIO_REG_PPR_CLOCK_EN;
- write32(bar0->base + SIO_REG_PPR_CLOCK, reg32);
+ write32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0), reg32);
}
/* Put Serial IO D21:F0-F6 device into desired mode. */
@@ -85,22 +85,22 @@ static void serialio_d21_ltr(struct resource *bar0)
u32 reg;
/* 1. Program BAR0 + 808h[2] = 0b */
- reg = read32(bar0->base + SIO_REG_PPR_GEN);
+ reg = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0));
reg &= ~SIO_REG_PPR_GEN_LTR_MODE_MASK;
- write32(bar0->base + SIO_REG_PPR_GEN, reg);
+ write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg);
/* 2. Program BAR0 + 804h[1:0] = 00b */
- reg = read32(bar0->base + SIO_REG_PPR_RST);
+ reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0));
reg &= ~SIO_REG_PPR_RST_ASSERT;
- write32(bar0->base + SIO_REG_PPR_RST, reg);
+ write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg);
/* 3. Program BAR0 + 804h[1:0] = 11b */
- reg = read32(bar0->base + SIO_REG_PPR_RST);
+ reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0));
reg |= SIO_REG_PPR_RST_ASSERT;
- write32(bar0->base + SIO_REG_PPR_RST, reg);
+ write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg);
/* 4. Program BAR0 + 814h[31:0] = 00000000h */
- write32(bar0->base + SIO_REG_AUTO_LTR, 0);
+ write32(res2mmio(bar0, SIO_REG_AUTO_LTR, 0), 0);
}
/* Enable LTR Auto Mode for D23:F0. */
@@ -109,26 +109,26 @@ static void serialio_d23_ltr(struct resource *bar0)
u32 reg;
/* Program BAR0 + 1008h[2] = 1b */
- reg = read32(bar0->base + SIO_REG_SDIO_PPR_GEN);
+ reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0));
reg |= SIO_REG_PPR_GEN_LTR_MODE_MASK;
- write32(bar0->base + SIO_REG_SDIO_PPR_GEN, reg);
+ write32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0), reg);
/* Program BAR0 + 1010h = 0x00000000 */
- write32(bar0->base + SIO_REG_SDIO_PPR_SW_LTR, 0);
+ write32(res2mmio(bar0, SIO_REG_SDIO_PPR_SW_LTR, 0), 0);
/* Program BAR0 + 3Ch[30] = 1b */
- reg = read32(bar0->base + SIO_REG_SDIO_PPR_CMD12);
+ reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0));
reg |= SIO_REG_SDIO_PPR_CMD12_B30;
- write32(bar0->base + SIO_REG_SDIO_PPR_CMD12, reg);
+ write32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0), reg);
}
/* Select I2C voltage of 1.8V or 3.3V. */
static void serialio_i2c_voltage_sel(struct resource *bar0, u8 voltage)
{
- u32 reg32 = read32(bar0->base + SIO_REG_PPR_GEN);
+ u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0));
reg32 &= ~SIO_REG_PPR_GEN_VOLTAGE_MASK;
reg32 |= SIO_REG_PPR_GEN_VOLTAGE(voltage);
- write32(bar0->base + SIO_REG_PPR_GEN, reg32);
+ write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg32);
}
/* Init sequence to be run once, done as part of D21:F0 (SDMA) init. */
diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c
index 845129f..7c35e67 100644
--- a/src/southbridge/intel/lynxpoint/usb_ehci.c
+++ b/src/southbridge/intel/lynxpoint/usb_ehci.c
@@ -64,13 +64,13 @@ void usb_ehci_disable(device_t dev)
void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ)
{
u32 reg32;
- u32 bar0_base;
+ u8 *bar0_base;
u16 pwr_state;
u16 pci_cmd;
/* Check if the controller is disabled or not present */
- bar0_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- if (bar0_base == 0 || bar0_base == 0xffffffff)
+ bar0_base = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+ if (bar0_base == 0 || bar0_base == (u8 *)0xffffffff)
return;
pci_cmd = pci_read_config32(dev, PCI_COMMAND);
@@ -86,7 +86,7 @@ void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ)
pci_write_config16(dev, EHCI_PWR_CTL_STS, new_state);
/* Make sure memory bar is set */
- pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar0_base);
+ pci_write_config32(dev, PCI_BASE_ADDRESS_0, (u32)bar0_base);
/* Make sure memory space is enabled */
pci_write_config16(dev, PCI_COMMAND, pci_cmd |
diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c
index 6c7bf04..3b8c23b 100644
--- a/src/southbridge/intel/lynxpoint/usb_xhci.c
+++ b/src/southbridge/intel/lynxpoint/usb_xhci.c
@@ -28,7 +28,7 @@
typedef struct southbridge_intel_lynxpoint_config config_t;
-static u32 usb_xhci_mem_base(device_t dev)
+static u8 *usb_xhci_mem_base(device_t dev)
{
u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
@@ -36,7 +36,7 @@ static u32 usb_xhci_mem_base(device_t dev)
if (mem_base == 0 || mem_base == 0xffffffff)
return 0;
- return mem_base & ~0xf;
+ return (u8 *)(mem_base & ~0xf);
}
static int usb_xhci_port_count_usb3(device_t dev)
@@ -46,7 +46,7 @@ static int usb_xhci_port_count_usb3(device_t dev)
return 4;
} else {
/* LynxPoint-H can have 0, 2, 4, or 6 SS ports */
- u32 mem_base = usb_xhci_mem_base(dev);
+ u8 *mem_base = usb_xhci_mem_base(dev);
u32 fus = read32(mem_base + XHCI_USB3FUS);
fus >>= XHCI_USB3FUS_SS_SHIFT;
fus &= XHCI_USB3FUS_SS_MASK;
@@ -60,9 +60,9 @@ static int usb_xhci_port_count_usb3(device_t dev)
return 0;
}
-static void usb_xhci_reset_status_usb3(u32 mem_base, int port)
+static void usb_xhci_reset_status_usb3(u8 *mem_base, int port)
{
- u32 portsc = mem_base + XHCI_USB3_PORTSC(port);
+ u8 *portsc = mem_base + XHCI_USB3_PORTSC(port);
u32 status = read32(portsc);
/* Do not set Port Enabled/Disabled field */
status &= ~XHCI_USB3_PORTSC_PED;
@@ -71,9 +71,9 @@ static void usb_xhci_reset_status_usb3(u32 mem_base, int port)
write32(portsc, status);
}
-static void usb_xhci_reset_port_usb3(u32 mem_base, int port)
+static void usb_xhci_reset_port_usb3(u8 *mem_base, int port)
{
- u32 portsc = mem_base + XHCI_USB3_PORTSC(port);
+ u8 *portsc = mem_base + XHCI_USB3_PORTSC(port);
write32(portsc, read32(portsc) | XHCI_USB3_PORTSC_WPR);
}
@@ -92,7 +92,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
u32 status, port_disabled;
int timeout, port;
int port_count = usb_xhci_port_count_usb3(dev);
- u32 mem_base = usb_xhci_mem_base(dev);
+ u8 *mem_base = usb_xhci_mem_base(dev);
if (!mem_base || !port_count)
return;
@@ -121,7 +121,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
/* Reset all requested ports */
for (port = 0; port < port_count; port++) {
- u32 portsc = mem_base + XHCI_USB3_PORTSC(port);
+ u8 *portsc = mem_base + XHCI_USB3_PORTSC(port);
/* Skip disabled ports */
if (port_disabled & (1 << port))
continue;
@@ -164,7 +164,7 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
{
u16 reg16;
u32 reg32;
- u32 mem_base = usb_xhci_mem_base(dev);
+ u8 *mem_base = usb_xhci_mem_base(dev);
if (!mem_base || slp_typ < 3)
return;
@@ -295,7 +295,7 @@ static void usb_xhci_init(device_t dev)
{
u32 reg32;
u16 reg16;
- u32 mem_base = usb_xhci_mem_base(dev);
+ u8 *mem_base = usb_xhci_mem_base(dev);
config_t *config = dev->chip_info;
/* D20:F0:74h[1:0] = 00b (set D0 state) */
diff --git a/src/southbridge/intel/sch/audio.c b/src/southbridge/intel/sch/audio.c
index 9c77937..83f5324 100644
--- a/src/southbridge/intel/sch/audio.c
+++ b/src/southbridge/intel/sch/audio.c
@@ -32,7 +32,7 @@
typedef struct southbridge_intel_sch_config config_t;
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
@@ -61,7 +61,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
return 0;
}
-static int codec_detect(u32 base)
+static int codec_detect(u8 *base)
{
u32 reg32;
int count;
@@ -142,7 +142,7 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
* no response would imply that the codec is non-operative
*/
-static int wait_for_ready(u32 base)
+static int wait_for_ready(u8 *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -165,7 +165,7 @@ static int wait_for_ready(u32 base)
* is non-operative
*/
-static int wait_for_valid(u32 base)
+static int wait_for_valid(u8 *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -190,7 +190,7 @@ static int wait_for_valid(u32 base)
return -1;
}
-static void codec_init(struct device *dev, u32 base, int addr)
+static void codec_init(struct device *dev, u8 *base, int addr)
{
u32 reg32;
const u32 *verb;
@@ -242,7 +242,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
printk(BIOS_DEBUG, "sch_audio: verb loaded.\n");
}
-static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
+static void codecs_init(struct device *dev, u8 *base, u32 codec_mask)
{
int i;
@@ -254,7 +254,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
static void sch_audio_init(struct device *dev)
{
- u32 base;
+ u8 *base;
struct resource *res;
u32 codec_mask;
u32 reg32;
@@ -268,8 +268,8 @@ static void sch_audio_init(struct device *dev)
// NOTE this will break as soon as the sch_audio get's a bar above
// 4G. Is there anything we can do about it?
- base = (u32) res->base;
- printk(BIOS_DEBUG, "sch_audio: base = %08x\n", (u32) base);
+ base = res2mmio(res, 0, 0);
+ printk(BIOS_DEBUG, "sch_audio: base = %px\n", base);
codec_mask = codec_detect(base);
if (codec_mask) {
diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c
index 9b6049c..d6c8c5b 100644
--- a/src/southbridge/nvidia/ck804/lpc.c
+++ b/src/southbridge/nvidia/ck804/lpc.c
@@ -60,7 +60,7 @@ static void lpc_common_init(device_t dev)
/* I/O APIC initialization. */
res = find_resource(dev, PCI_BASE_ADDRESS_1); /* IOAPIC */
ASSERT(res != NULL);
- setup_ioapic(res->base, 0); /* Don't rename IOAPIC ID. */
+ setup_ioapic(res2mmio(res, 0, 0), 0); /* Don't rename IOAPIC ID. */
#if 1
dword = pci_read_config32(dev, 0xe4);
diff --git a/src/southbridge/nvidia/ck804/nic.c b/src/southbridge/nvidia/ck804/nic.c
index e285644..974ce0d 100644
--- a/src/southbridge/nvidia/ck804/nic.c
+++ b/src/southbridge/nvidia/ck804/nic.c
@@ -33,11 +33,11 @@ static void nic_init(struct device *dev)
int eeprom_valid = 0;
struct southbridge_nvidia_ck804_config *conf;
static u32 nic_index = 0;
- unsigned long base;
+ u8 *base;
struct resource *res;
res = find_resource(dev, 0x10);
- base = (unsigned long)res->base;
+ base = res2mmio(res, 0, 0);
#define NvRegPhyInterface 0xC0
#define PHY_RGMII 0x10000000
@@ -89,10 +89,10 @@ static void nic_init(struct device *dev)
/* If that is invalid we will read that from romstrap. */
if (!eeprom_valid) {
- unsigned long mac_pos;
- mac_pos = 0xffffffd0; /* See romstrap.inc and romstrap.lds. */
+ u32 *mac_pos;
+ mac_pos = (u32 *)0xffffffd0; /* See romstrap.inc and romstrap.lds. */
mac_l = read32(mac_pos) + nic_index;
- mac_h = read32(mac_pos + 4);
+ mac_h = read32(mac_pos + 1);
}
#if 1
/* Set that into NIC MMIO. */
diff --git a/src/southbridge/nvidia/mcp55/azalia.c b/src/southbridge/nvidia/mcp55/azalia.c
index 67433d3..490cfa7 100644
--- a/src/southbridge/nvidia/mcp55/azalia.c
+++ b/src/southbridge/nvidia/mcp55/azalia.c
@@ -31,7 +31,7 @@
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
@@ -58,7 +58,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
return 0;
}
-static int codec_detect(u32 base)
+static int codec_detect(u8 *base)
{
u32 reg32;
@@ -111,7 +111,7 @@ static u32 find_verb(struct device *dev, u32 viddid, u32 **verb)
* Wait 50usec for the codec to indicate it is ready.
* No response would imply that the codec is non-operative.
*/
-static int wait_for_ready(u32 base)
+static int wait_for_ready(u8 *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the same duration. */
int timeout = 50;
@@ -130,7 +130,7 @@ static int wait_for_ready(u32 base)
* Wait 50usec for the codec to indicate that it accepted the previous command.
* No response would imply that the code is non-operative.
*/
-static int wait_for_valid(u32 base)
+static int wait_for_valid(u8 *base)
{
u32 reg32;
@@ -152,7 +152,7 @@ static int wait_for_valid(u32 base)
return -1;
}
-static void codec_init(struct device *dev, u32 base, int addr)
+static void codec_init(struct device *dev, u8 *base, int addr)
{
u32 reg32, verb_size;
u32 *verb;
@@ -195,7 +195,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
}
-static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
+static void codecs_init(struct device *dev, u8 *base, u32 codec_mask)
{
int i;
for (i = 2; i >= 0; i--) {
@@ -206,7 +206,8 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
static void azalia_init(struct device *dev)
{
- u32 base, codec_mask, reg32;
+ u8 *base;
+ u32 codec_mask, reg32;
struct resource *res;
u8 reg8;
@@ -244,8 +245,8 @@ static void azalia_init(struct device *dev)
* NOTE: This will break as soon as the Azalia gets a BAR above
* 4G. Is there anything we can do about it?
*/
- base = (u32)res->base;
- printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
+ base = res2mmio(res, 0, 0);
+ printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
codec_mask = codec_detect(base);
if (codec_mask) {
diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c
index 11c2c4f..5f190b8 100644
--- a/src/southbridge/nvidia/mcp55/lpc.c
+++ b/src/southbridge/nvidia/mcp55/lpc.c
@@ -60,13 +60,13 @@
static void lpc_common_init(device_t dev, int master)
{
u8 byte;
- u32 ioapic_base;
+ void *ioapic_base;
/* IOAPIC initialization. */
byte = pci_read_config8(dev, 0x74);
byte |= (1 << 0); /* Enable IOAPIC. */
pci_write_config8(dev, 0x74, byte);
- ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_1); /* 0x14 */
+ ioapic_base = (void *)pci_read_config32(dev, PCI_BASE_ADDRESS_1); /* 0x14 */
if (master)
setup_ioapic(ioapic_base, 0);
diff --git a/src/southbridge/nvidia/mcp55/nic.c b/src/southbridge/nvidia/mcp55/nic.c
index fd736e6..136d060 100644
--- a/src/southbridge/nvidia/mcp55/nic.c
+++ b/src/southbridge/nvidia/mcp55/nic.c
@@ -31,7 +31,7 @@
#include <delay.h>
#include "mcp55.h"
-static int phy_read(u32 base, unsigned phy_addr, unsigned phy_reg)
+static int phy_read(u8 *base, unsigned phy_addr, unsigned phy_reg)
{
u32 dword;
unsigned loop = 0x100;
@@ -59,7 +59,7 @@ static int phy_read(u32 base, unsigned phy_addr, unsigned phy_reg)
return dword;
}
-static void phy_detect(u32 base)
+static void phy_detect(u8 *base)
{
u32 dword;
int i, val;
@@ -103,7 +103,8 @@ static void phy_detect(u32 base)
static void nic_init(struct device *dev)
{
- u32 mac_h = 0, mac_l = 0, base;
+ u8 *base;
+ u32 mac_h = 0, mac_l = 0;
int eeprom_valid = 0;
struct southbridge_nvidia_mcp55_config *conf;
static u32 nic_index = 0;
@@ -114,7 +115,7 @@ static void nic_init(struct device *dev)
if (!res)
return;
- base = res->base;
+ base = res2mmio(res, 0, 0);
phy_detect(base);
@@ -160,10 +161,10 @@ static void nic_init(struct device *dev)
}
// if that is invalid we will read that from romstrap
if(!eeprom_valid) {
- unsigned long mac_pos;
- mac_pos = 0xffffffd0; // refer to romstrap.inc and romstrap.lds
+ u32 *mac_pos;
+ mac_pos = (u32 *)0xffffffd0; // refer to romstrap.inc and romstrap.lds
mac_l = read32(mac_pos) + nic_index; // overflow?
- mac_h = read32(mac_pos + 4);
+ mac_h = read32(mac_pos + 1);
}
#if 1
diff --git a/src/southbridge/sis/sis966/aza.c b/src/southbridge/sis/sis966/aza.c
index 1a9462b..ed81205 100644
--- a/src/southbridge/sis/sis966/aza.c
+++ b/src/southbridge/sis/sis966/aza.c
@@ -42,7 +42,7 @@ u8 SiS_SiS7502_init[7][3]={
{0x00, 0x00, 0x00} //End of table
};
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 dword;
int count;
@@ -67,7 +67,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
}
-static u32 send_verb(u32 base, u32 verb)
+static u32 send_verb(u8 *base, u32 verb)
{
u32 dword;
@@ -75,7 +75,7 @@ static u32 send_verb(u32 base, u32 verb)
dword=dword|(unsigned long)0x0002;
write32(base + 0x68, dword);
do {
- dword = read32(base + 0x68);
+ dword = read32(base + 0x68);
} while ((dword & 1)!=0);
write32(base + 0x60, verb);
udelay(500);
@@ -92,7 +92,7 @@ static u32 send_verb(u32 base, u32 verb)
}
-static int codec_detect(u32 base)
+static int codec_detect(u8 *base)
{
u32 dword;
int idx=0;
@@ -194,7 +194,7 @@ static unsigned find_verb(u32 viddid, u32 **verb)
}
-static void codec_init(u32 base, int addr)
+static void codec_init(u8 *base, int addr)
{
u32 dword;
u32 *verb;
@@ -232,7 +232,7 @@ static void codec_init(u32 base, int addr)
printk(BIOS_DEBUG, "verb loaded!\n");
}
-static void codecs_init(u32 base, u32 codec_mask)
+static void codecs_init(u8 *base, u32 codec_mask)
{
codec_init(base, 0);
return;
@@ -240,7 +240,7 @@ static void codecs_init(u32 base, u32 codec_mask)
static void aza_init(struct device *dev)
{
- u32 base;
+ u8 *base;
struct resource *res;
u32 codec_mask;
@@ -286,8 +286,8 @@ static void aza_init(struct device *dev)
if(!res)
return;
- base = res->base;
- printk(BIOS_DEBUG, "base = 0x%08x\n", base);
+ base = res2mmio(res, 0, 0);
+ printk(BIOS_DEBUG, "base = 0x%p\n", base);
codec_mask = codec_detect(base);
diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c
index a61883b..c9f1ff6 100644
--- a/src/southbridge/sis/sis966/lpc.c
+++ b/src/southbridge/sis/sis966/lpc.c
@@ -59,13 +59,13 @@
static void lpc_common_init(device_t dev)
{
uint8_t byte;
- uint32_t ioapic_base;
+ void *ioapic_base;
/* IO APIC initialization */
byte = pci_read_config8(dev, 0x74);
byte |= (1<<0); // enable APIC
pci_write_config8(dev, 0x74, byte);
- ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
+ ioapic_base = (void *)pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
setup_ioapic(ioapic_base, 0); // Don't rename IO APIC ID
}
diff --git a/src/southbridge/sis/sis966/nic.c b/src/southbridge/sis/sis966/nic.c
index b12c831..183260f 100644
--- a/src/southbridge/sis/sis966/nic.c
+++ b/src/southbridge/sis/sis966/nic.c
@@ -133,7 +133,7 @@ static void set_apc(struct device *dev)
* @return Contents of EEPROM word (Reg).
*/
#define LoopNum 200
-static unsigned long ReadEEprom( struct device *dev, u32 base, u32 Reg)
+static unsigned long ReadEEprom( struct device *dev, u8 *base, u32 Reg)
{
u32 data;
u32 i;
@@ -142,13 +142,13 @@ static unsigned long ReadEEprom( struct device *dev, u32 base, u32 Reg)
ulValue = (0x80 | (0x2 << 8) | (Reg << 10)); //BIT_7
- write32(base+0x3c, ulValue);
+ write32(base + 0x3c, ulValue);
mdelay(10);
for(i=0 ; i <= LoopNum; i++)
{
- ulValue=read32(base+0x3c);
+ ulValue=read32(base + 0x3c);
if(!(ulValue & 0x0080)) //BIT_7
break;
@@ -160,14 +160,14 @@ static unsigned long ReadEEprom( struct device *dev, u32 base, u32 Reg)
if(i==LoopNum) data=0x10000;
else{
- ulValue=read32(base+0x3c);
+ ulValue=read32(base + 0x3c);
data = ((ulValue & 0xffff0000) >> 16);
}
return data;
}
-static int phy_read(u32 base, unsigned phy_addr, unsigned phy_reg)
+static int phy_read(u8 *base, unsigned phy_addr, unsigned phy_reg)
{
u32 ulValue;
u32 Read_Cmd;
@@ -181,14 +181,14 @@ static int phy_read(u32 base, unsigned phy_addr, unsigned phy_reg)
SMI_REQUEST);
// SmiMgtInterface Reg is the SMI management interface register(offset 44h) of MAC
- write32(base+0x44, Read_Cmd);
+ write32(base + 0x44, Read_Cmd);
// Polling SMI_REQ bit to be deasserted indicated read command completed
do
{
// Wait 20 usec before checking status
mdelay(20);
- ulValue = read32(base+0x44);
+ ulValue = read32(base + 0x44);
} while((ulValue & SMI_REQUEST) != 0);
//printk(BIOS_DEBUG, "base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue);
usData=(ulValue>>16);
@@ -201,7 +201,7 @@ static int phy_read(u32 base, unsigned phy_addr, unsigned phy_reg)
// Detect a valid PHY
// If there exist a valid PHY then return TRUE, else return FALSE
-static int phy_detect(u32 base,u16 *PhyAddr) //BOOL PHY_Detect()
+static int phy_detect(u8 *base,u16 *PhyAddr) //BOOL PHY_Detect()
{
int bFoundPhy = FALSE;
u16 usData;
@@ -238,7 +238,7 @@ static void nic_init(struct device *dev)
{
int val;
u16 PhyAddr;
- u32 base;
+ u8 *base;
struct resource *res;
printk(BIOS_DEBUG, "NIC_INIT:---------->\n");
@@ -269,8 +269,8 @@ static void nic_init(struct device *dev)
printk(BIOS_DEBUG, "NIC Cannot find resource..\n");
return;
}
- base = res->base;
- printk(BIOS_DEBUG, "NIC base address %x\n",base);
+ base = res2mmio(res, 0, 0);
+ printk(BIOS_DEBUG, "NIC base address %p\n",base);
if(!(val=phy_detect(base,&PhyAddr)))
{
@@ -299,9 +299,9 @@ static void nic_init(struct device *dev)
}else{
// read MAC address from firmware
printk(BIOS_DEBUG, "EEPROM invalid!!\nReg 0x38h=%.8lx \n",ulValue);
- MacAddr[0]=read16(0xffffffc0); // mac address store at here
- MacAddr[1]=read16(0xffffffc2);
- MacAddr[2]=read16(0xffffffc4);
+ MacAddr[0]=read16((u16 *)0xffffffc0); // mac address store at here
+ MacAddr[1]=read16((u16 *)0xffffffc2);
+ MacAddr[2]=read16((u16 *)0xffffffc4);
}
set_apc(dev);
diff --git a/src/southbridge/sis/sis966/usb2.c b/src/southbridge/sis/sis966/usb2.c
index c6f4027..94eabd5 100644
--- a/src/southbridge/sis/sis966/usb2.c
+++ b/src/southbridge/sis/sis966/usb2.c
@@ -66,7 +66,7 @@ static const u8 SiS_SiS7002_init[22][3]={
static void usb2_init(struct device *dev)
{
- u32 base;
+ u8 *base;
struct resource *res;
int i;
u8 temp8;
@@ -89,9 +89,9 @@ static void usb2_init(struct device *dev)
if(!res)
return;
- base = res->base;
- printk(BIOS_DEBUG, "base = 0x%08x\n", base);
- write32(base+0x20, 0x2);
+ base = res2mmio(res, 0, 0);
+ printk(BIOS_DEBUG, "base = 0x%p\n", base);
+ write32(base + 0x20, 0x2);
//-------------------------------------------------------------
#if DEBUG_USB2
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index d3e3d32..d85006c 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -636,7 +636,7 @@ static void southbridge_init_common(struct device *dev)
{
vt8237_common_init(dev);
pci_routing_fixup(dev);
- setup_ioapic(IO_APIC_ADDR, VT8237R_APIC_ID);
+ setup_ioapic(VIO_APIC_VADDR, VT8237R_APIC_ID);
setup_i8259();
init_keyboard(dev);
}
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