[coreboot-gerrit] New patch to review for coreboot: c3d780c baytrail: there is a chance that USBPHY_COMPBG is set to 0

[Marc Jones (marc.jones@se-eng.com)]

Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8218

-gerrit

commit c3d780cd102cfed110af4478dfff67b7b8ba7d5c
Author: Kane Chen <kane.chen at intel.com>
Date:   Thu Jul 17 11:31:57 2014 -0700

    baytrail: there is a chance that USBPHY_COMPBG is set to 0
    
    Due to some projects don't have the correct settings in devicetree.cb
    so put this change in case those projects without are setting in devicetree.cb
    
    BUG=chrome-os-partner:30690
    BRANCH=none
    TEST=emerge-rambi coreboot without problem
         checked the USBPHY_COMPBG is configured properly
         even there is no setting in devicetree
    
    Original-Change-Id: Iaf8155497c41f10c81d1faa7bb0e3452a7cedcc6
    Original-Signed-off-by: Kane Chen <kane.chen at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/209051
    Original-Reviewed-by: Shawn Nematbakhsh <shawnn at chromium.org>
    (cherry picked from commit 713f809952a2d8da434d619d48cb7ddce1991925)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: I86f9b77e703d2b844fa636678499c47ffaffeede
---
 src/soc/intel/baytrail/ehci.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c
index bfdb61a..74577af 100644
--- a/src/soc/intel/baytrail/ehci.c
+++ b/src/soc/intel/baytrail/ehci.c
@@ -94,10 +94,12 @@ static const struct reg_script ehci_hc_reset[] = {
 static void usb2_phy_init(device_t dev)
 {
 	struct soc_intel_baytrail_config *config = dev->chip_info;
+	u32 usb2_comp_bg = (config->usb2_comp_bg == 0 ?
+			    0x4700 : config->usb2_comp_bg);
 	struct reg_script usb2_phy_script[] = {
 		/* USB3PHYInit() */
 		REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG,
-			       config->usb2_comp_bg),
+			       usb2_comp_bg),
 		/* Per port phy settings, set in devicetree.cb */
 		REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE0,
 			       config->usb2_per_port_lane0),