[coreboot-gerrit] Patch set updated for coreboot: 7ec8006 ACPI: Add acpi_is_wakeup_s3() for romstage
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Sat Jan 10 08:57:48 CET 2015
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8187
-gerrit
commit 7ec80065b663bcd8280f80b170b99b4ab40d34fb
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Fri Jan 9 23:48:47 2015 +0200
ACPI: Add acpi_is_wakeup_s3() for romstage
This replaces acpi_is_wakeup_early().
Change-Id: I23112c1fc7b6f99584bc065fbf6b10fb073b1eb6
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/arch/x86/include/arch/acpi.h | 11 ++++-
src/cpu/amd/agesa/heapmanager.c | 6 +--
src/cpu/amd/car/post_cache_as_ram.c | 8 +---
src/mainboard/amd/olivehill/romstage.c | 2 +-
src/mainboard/amd/olivehillplus/romstage.c | 2 +-
src/mainboard/amd/parmer/romstage.c | 2 +-
src/mainboard/amd/persimmon/romstage.c | 2 +-
src/mainboard/amd/thatcher/romstage.c | 2 +-
src/mainboard/asrock/imb-a180/romstage.c | 2 +-
src/mainboard/asus/f2a85-m/romstage.c | 2 +-
src/mainboard/gizmosphere/gizmo/romstage.c | 2 +-
src/mainboard/gizmosphere/gizmo2/romstage.c | 2 +-
src/mainboard/hp/abm/romstage.c | 2 +-
src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 2 +-
src/mainboard/jetway/nf81-t56n-lf/romstage.c | 2 +-
src/mainboard/lenovo/g505s/romstage.c | 2 +-
src/mainboard/lippert/frontrunner-af/romstage.c | 2 +-
src/mainboard/lippert/toucan-af/romstage.c | 2 +-
src/northbridge/amd/amdk8/raminit.c | 6 +--
src/northbridge/amd/amdk8/raminit_f.c | 7 +--
src/southbridge/amd/agesa/hudson/Makefile.inc | 4 +-
src/southbridge/amd/agesa/hudson/early_setup.c | 28 ------------
src/southbridge/amd/agesa/hudson/hudson.c | 40 -----------------
src/southbridge/amd/agesa/hudson/ramtop.c | 59 +++++++++++++++++++++++++
src/southbridge/amd/cimx/sb800/Makefile.inc | 3 ++
src/southbridge/amd/cimx/sb800/cfg.c | 47 +-------------------
src/southbridge/amd/cimx/sb800/early.c | 8 ----
src/southbridge/amd/cimx/sb800/ramtop.c | 59 +++++++++++++++++++++++++
src/southbridge/amd/sb700/early_setup.c | 9 ++--
src/southbridge/amd/sb700/lpc.c | 17 +++----
src/southbridge/amd/sb800/early_setup.c | 9 ++--
src/southbridge/intel/i82371eb/smbus.c | 11 -----
src/southbridge/intel/i82371eb/wakeup.c | 3 +-
src/southbridge/via/k8t890/early_car.c | 4 +-
src/southbridge/via/vt8237r/early_smbus.c | 4 +-
src/southbridge/via/vt8237r/lpc.c | 10 +++--
36 files changed, 177 insertions(+), 206 deletions(-)
diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
index c497082..771b51c 100644
--- a/src/arch/x86/include/arch/acpi.h
+++ b/src/arch/x86/include/arch/acpi.h
@@ -581,14 +581,21 @@ static inline int acpi_s3_resume_allowed(void)
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
extern int acpi_slp_type;
+
+#ifdef __PRE_RAM__
+static inline int acpi_is_wakeup_s3(void)
+{
+ return (acpi_get_sleep_type() == 3);
+}
+#else
int acpi_is_wakeup(void);
int acpi_is_wakeup_s3(void);
-int acpi_is_wakeup_early(void);
+#endif
+
#else
#define acpi_slp_type 0
static inline int acpi_is_wakeup(void) { return 0; }
static inline int acpi_is_wakeup_s3(void) { return 0; }
-static inline int acpi_is_wakeup_early(void) { return 0; }
#endif
#endif /* __ASM_ACPI_H */
diff --git a/src/cpu/amd/agesa/heapmanager.c b/src/cpu/amd/agesa/heapmanager.c
index 50ec3ff..cc53d35 100644
--- a/src/cpu/amd/agesa/heapmanager.c
+++ b/src/cpu/amd/agesa/heapmanager.c
@@ -12,13 +12,11 @@ UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader)
{
UINT32 heap = BIOS_HEAP_START_ADDRESS;
-#if CONFIG_HAVE_ACPI_RESUME
- /* Both romstage and ramstage has this S3 detect. */
- if (acpi_get_sleep_type() == 3)
+ if (acpi_is_wakeup_s3())
heap = (UINT32) cbmem_find(CBMEM_ID_RESUME_SCRATCH) +
(CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE);
/* himem_heap_base + high_stack_size */
-#endif
+
return heap;
}
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 8bc5cd3..6c32090 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -101,12 +101,10 @@ void post_cache_as_ram(void)
{
void *resume_backup_memory = NULL;
- int s3resume = acpi_s3_resume_allowed() && acpi_is_wakeup_early();
+ int s3resume = acpi_is_wakeup_s3();
if (s3resume) {
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
cbmem_recovery(s3resume);
resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
-#endif
}
prepare_romstage_ramstack(resume_backup_memory);
@@ -141,10 +139,8 @@ void cache_as_ram_new_stack (void)
set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
enable_cache();
- if (acpi_s3_resume_allowed() && acpi_is_wakeup_early()) {
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+ if (acpi_is_wakeup_s3()) {
resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
-#endif
}
prepare_ramstage_region(resume_backup_memory);
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index 2262782..8286f0b 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -87,7 +87,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
+ int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
post_code(0x40);
agesawrapper_amdinitpost();
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index 6fa3af6..63044ed 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -90,7 +90,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
AGESAWRAPPER(amdinitearly);
- int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
+ int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
post_code(0x40);
AGESAWRAPPER(amdinitpost);
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c
index 1fb709a..1d25736 100644
--- a/src/mainboard/amd/parmer/romstage.c
+++ b/src/mainboard/amd/parmer/romstage.c
@@ -71,7 +71,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
+ int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
post_code(0x40);
agesawrapper_amdinitpost();
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 2fdab41..bff9e14 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -86,7 +86,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
+ int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
post_code(0x40);
agesawrapper_amdinitpost();
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index 30808a4..27d9680 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -85,7 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
+ int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
post_code(0x40);
agesawrapper_amdinitpost();
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c
index efeed35..cb6d07a 100644
--- a/src/mainboard/asrock/imb-a180/romstage.c
+++ b/src/mainboard/asrock/imb-a180/romstage.c
@@ -111,7 +111,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
+ int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
post_code(0x40);
agesawrapper_amdinitpost();
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index 95298d1..2332b4a 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -131,7 +131,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
+ int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
post_code(0x40);
agesawrapper_amdinitpost();
diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c
index f420bf2..527ad26 100644
--- a/src/mainboard/gizmosphere/gizmo/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo/romstage.c
@@ -94,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
+ int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
post_code(0x40);
agesawrapper_amdinitpost();
diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c
index 2262782..8286f0b 100644
--- a/src/mainboard/gizmosphere/gizmo2/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo2/romstage.c
@@ -87,7 +87,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
+ int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
post_code(0x40);
agesawrapper_amdinitpost();
diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c
index 5e3044a..a55ec02 100644
--- a/src/mainboard/hp/abm/romstage.c
+++ b/src/mainboard/hp/abm/romstage.c
@@ -100,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
+ int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
post_code(0x40);
agesawrapper_amdinitpost();
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
index bc92e6d..87fcd4c 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
@@ -63,7 +63,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
+ int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
post_code(0x40);
agesawrapper_amdinitpost();
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index 197c81d..c3ca947 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -102,7 +102,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
+ int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
post_code(0x40);
agesawrapper_amdinitpost();
diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c
index bc92e6d..87fcd4c 100644
--- a/src/mainboard/lenovo/g505s/romstage.c
+++ b/src/mainboard/lenovo/g505s/romstage.c
@@ -63,7 +63,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
+ int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
post_code(0x40);
agesawrapper_amdinitpost();
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c
index 0f718f2..cc03053 100644
--- a/src/mainboard/lippert/frontrunner-af/romstage.c
+++ b/src/mainboard/lippert/frontrunner-af/romstage.c
@@ -85,7 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
+ int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
post_code(0x40);
/* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index 415cdbe..7a8e916 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -86,7 +86,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
+ int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
post_code(0x40);
/* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index 19f83b9..4213cfb 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -2349,11 +2349,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
{
int i;
u32 whatWait = 0;
-#if CONFIG_HAVE_ACPI_RESUME
- int suspend = acpi_is_wakeup_early();
-#else
- int suspend = 0;
-#endif
+ int suspend = acpi_is_wakeup_s3();
/* Error if I don't have memory */
if (memory_end_k(ctrl, controllers) == 0) {
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index b8417a6..92d7f13 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -26,6 +26,7 @@
#include <cpu/amd/mtrr.h>
#include <stdlib.h>
+#include <arch/acpi.h>
#include "raminit.h"
#include "f.h"
#include <spd_ddr2.h>
@@ -3017,11 +3018,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
struct sys_info *sysinfo)
{
int i;
-#if CONFIG_HAVE_ACPI_RESUME
- int suspend = acpi_is_wakeup_early();
-#else
- int suspend = 0;
-#endif
+ int suspend = acpi_is_wakeup_s3();
#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
unsigned cpu_f0_f1[8];
diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc
index 84f0d3e..bcadd8d 100644
--- a/src/southbridge/amd/agesa/hudson/Makefile.inc
+++ b/src/southbridge/amd/agesa/hudson/Makefile.inc
@@ -19,7 +19,9 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
romstage-y += early_setup.c
ramstage-$(CONFIG_SPI_FLASH) += spi.c
-ramstage-y += resume.c
+ramstage-y += resume.c ramtop.c
+
+romstage-y += ramtop.c
romstage-y += imc.c
ramstage-y += imc.c
diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c
index 1b9b689..3816141 100644
--- a/src/southbridge/amd/agesa/hudson/early_setup.c
+++ b/src/southbridge/amd/agesa/hudson/early_setup.c
@@ -123,32 +123,4 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
return nvram_pos;
}
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
-int acpi_get_sleep_type(void)
-{
- u16 tmp = inw(ACPI_PM1_CNT_BLK);
- tmp = ((tmp & (7 << 10)) >> 10);
- /* printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); */
- return (int)tmp;
-}
-
-int acpi_is_wakeup_early(void)
-{
- return (acpi_get_sleep_type() == 3);
-}
-#endif /* CONFIG_HAVE_ACPI_RESUME */
-
-unsigned long get_top_of_ram(void)
-{
- uint32_t xdata = 0;
- int xnvram_pos = 0xf8, xi;
- for (xi = 0; xi<4; xi++) {
- outb(xnvram_pos, BIOSRAM_INDEX);
- xdata &= ~(0xff << (xi * 8));
- xdata |= inb(BIOSRAM_DATA) << (xi *8);
- xnvram_pos++;
- }
- return (unsigned long) xdata;
-}
-
#endif /* _HUDSON_EARLY_SETUP_C_ */
diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c
index be8aa69..fd2c268 100644
--- a/src/southbridge/amd/agesa/hudson/hudson.c
+++ b/src/southbridge/amd/agesa/hudson/hudson.c
@@ -38,30 +38,6 @@
*/
#define PM_MMIO_BASE 0xfed80300
-
-#if CONFIG_HAVE_ACPI_RESUME
-int acpi_get_sleep_type(void)
-{
- u16 tmp = inw(ACPI_PM1_CNT_BLK);
- tmp = ((tmp & (7 << 10)) >> 10);
- /* printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); */
- return (int)tmp;
-}
-#endif
-
-void backup_top_of_ram(uint64_t ramtop)
-{
- u32 dword = (u32) ramtop;
- int nvram_pos = 0xf8, i; /* temp */
- /* printk(BIOS_DEBUG, "dword=%x\n", dword); */
- for (i = 0; i<4; i++) {
- /* printk(BIOS_DEBUG, "nvram_pos=%x, dword>>(8*i)=%x\n", nvram_pos, (dword >>(8 * i)) & 0xff); */
- outb(nvram_pos, BIOSRAM_INDEX);
- outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
- nvram_pos++;
- }
-}
-
void pm_write8(u8 reg, u8 value)
{
write8(PM_MMIO_BASE + reg, value);
@@ -160,22 +136,6 @@ void hudson_enable(device_t dev)
}
}
-#if CONFIG_HAVE_ACPI_RESUME
-unsigned long get_top_of_ram(void)
-{
- uint32_t xdata = 0;
- int xnvram_pos = 0xf8, xi;
- if (acpi_get_sleep_type() != 3)
- return 0;
- for (xi = 0; xi<4; xi++) {
- outb(xnvram_pos, BIOSRAM_INDEX);
- xdata &= ~(0xff << (xi * 8));
- xdata |= inb(BIOSRAM_DATA) << (xi *8);
- xnvram_pos++;
- }
- return (unsigned long) xdata;
-}
-#endif
static void hudson_init_acpi_ports(void)
{
diff --git a/src/southbridge/amd/agesa/hudson/ramtop.c b/src/southbridge/amd/agesa/hudson/ramtop.c
new file mode 100644
index 0000000..182150f
--- /dev/null
+++ b/src/southbridge/amd/agesa/hudson/ramtop.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/acpi.h>
+#include <cbmem.h>
+#include "hudson.h"
+
+int acpi_get_sleep_type(void)
+{
+ u16 tmp = inw(ACPI_PM1_CNT_BLK);
+ tmp = ((tmp & (7 << 10)) >> 10);
+ return (int)tmp;
+}
+
+#ifndef __PRE_RAM__
+void backup_top_of_ram(uint64_t ramtop)
+{
+ u32 dword = (u32) ramtop;
+ int nvram_pos = 0xf8, i; /* temp */
+ for (i = 0; i<4; i++) {
+ outb(nvram_pos, BIOSRAM_INDEX);
+ outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
+ nvram_pos++;
+ }
+}
+#endif
+
+unsigned long get_top_of_ram(void)
+{
+ uint32_t xdata = 0;
+ int xnvram_pos = 0xf8, xi;
+ if (acpi_get_sleep_type() != 3)
+ return 0;
+ for (xi = 0; xi<4; xi++) {
+ outb(xnvram_pos, BIOSRAM_INDEX);
+ xdata &= ~(0xff << (xi * 8));
+ xdata |= inb(BIOSRAM_DATA) << (xi *8);
+ xnvram_pos++;
+ }
+ return (unsigned long) xdata;
+}
diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc
index f4a84b7..ca3d86a 100644
--- a/src/southbridge/amd/cimx/sb800/Makefile.inc
+++ b/src/southbridge/amd/cimx/sb800/Makefile.inc
@@ -34,6 +34,9 @@ ramstage-$(CONFIG_SB800_IMC_FAN_CONTROL) += fan.c
ramstage-$(CONFIG_SPI_FLASH) += spi.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
+romstage-$(CONFIG_HAVE_ACPI_RESUME) += ramtop.c
+ramstage-$(CONFIG_HAVE_ACPI_RESUME) += ramtop.c
+
romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += ../../sb800/enable_usbdebug.c
ramstage-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c
diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c
index 9ddcf8f..ac6e6ae 100644
--- a/src/southbridge/amd/cimx/sb800/cfg.c
+++ b/src/southbridge/amd/cimx/sb800/cfg.c
@@ -26,48 +26,6 @@
#include <arch/io.h>
#include <arch/acpi.h>
-#if CONFIG_HAVE_ACPI_RESUME
-int acpi_get_sleep_type(void)
-{
- u16 tmp = inw(PM1_CNT_BLK_ADDRESS);
- tmp = ((tmp & (7 << 10)) >> 10);
- /* printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); */
- return (int)tmp;
-}
-#endif
-
-#ifndef __PRE_RAM__
-void backup_top_of_ram(uint64_t ramtop)
-{
- u32 dword = (u32) ramtop;
- int nvram_pos = 0xf8, i; /* temp */
- printk(BIOS_DEBUG, "dword=%x\n", dword);
- for (i = 0; i<4; i++) {
- printk(BIOS_DEBUG, "nvram_pos=%x, dword>>(8*i)=%x\n", nvram_pos, (dword >>(8 * i)) & 0xff);
- outb(nvram_pos, BIOSRAM_INDEX);
- outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
- nvram_pos++;
- }
-}
-#endif
-
-#if CONFIG_HAVE_ACPI_RESUME
-unsigned long get_top_of_ram(void)
-{
- u32 xdata = 0;
- int xnvram_pos = 0xf8, xi;
- if (acpi_get_sleep_type() != 3)
- return 0;
- for (xi = 0; xi<4; xi++) {
- outb(xnvram_pos, BIOSRAM_INDEX);
- xdata &= ~(0xff << (xi * 8));
- xdata |= inb(BIOSRAM_DATA) << (xi *8);
- xnvram_pos++;
- }
- return (unsigned long) xdata;
-}
-#endif
-
/**
* @brief South Bridge CIMx configuration
*
@@ -80,10 +38,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
if (!sb_config)
return;
-#if CONFIG_HAVE_ACPI_RESUME
- if (acpi_get_sleep_type() == 3)
- sb_config->S3Resume = 1;
-#endif
+ sb_config->S3Resume = acpi_is_wakeup_s3();
/* header */
sb_config->StdHeader.PcieBasePtr = PCIEX_BASE_ADDRESS;
diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c
index 7492f99..34375c5 100644
--- a/src/southbridge/amd/cimx/sb800/early.c
+++ b/src/southbridge/amd/cimx/sb800/early.c
@@ -20,7 +20,6 @@
#include <stdint.h>
#include <device/pci_ids.h>
#include <arch/io.h> /* inl, outl */
-#include <arch/acpi.h>
#include "SBPLATFORM.h"
#include "sb_cimx.h"
#include "cfg.h" /*sb800_cimx_config*/
@@ -74,10 +73,3 @@ void sb800_clk_output_48Mhz(void)
*(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
*(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */
}
-
-#if CONFIG_HAVE_ACPI_RESUME
-int acpi_is_wakeup_early(void)
-{
- return (acpi_get_sleep_type() == 3);
-}
-#endif
diff --git a/src/southbridge/amd/cimx/sb800/ramtop.c b/src/southbridge/amd/cimx/sb800/ramtop.c
new file mode 100644
index 0000000..7e9abae
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb800/ramtop.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/acpi.h>
+#include <cbmem.h>
+#include "SBPLATFORM.h"
+
+int acpi_get_sleep_type(void)
+{
+ u16 tmp = inw(PM1_CNT_BLK_ADDRESS);
+ tmp = ((tmp & (7 << 10)) >> 10);
+ return (int)tmp;
+}
+
+#ifndef __PRE_RAM__
+void backup_top_of_ram(uint64_t ramtop)
+{
+ u32 dword = (u32) ramtop;
+ int nvram_pos = 0xf8, i; /* temp */
+ for (i = 0; i<4; i++) {
+ outb(nvram_pos, BIOSRAM_INDEX);
+ outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
+ nvram_pos++;
+ }
+}
+#endif
+
+unsigned long get_top_of_ram(void)
+{
+ u32 xdata = 0;
+ int xnvram_pos = 0xf8, xi;
+ if (acpi_get_sleep_type() != 3)
+ return 0;
+ for (xi = 0; xi<4; xi++) {
+ outb(xnvram_pos, BIOSRAM_INDEX);
+ xdata &= ~(0xff << (xi * 8));
+ xdata |= inb(BIOSRAM_DATA) << (xi *8);
+ xnvram_pos++;
+ }
+ return (unsigned long) xdata;
+}
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index 82d51e6..855cbc4 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -721,20 +721,18 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
return nvram_pos;
}
-#if CONFIG_HAVE_ACPI_RESUME
-int acpi_is_wakeup_early(void)
+int acpi_get_sleep_type(void)
{
u16 tmp;
tmp = inw(ACPI_PM1_CNT_BLK);
- printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp);
- return (((tmp & (7 << 10)) >> 10) == 3);
+ return ((tmp & (7 << 10)) >> 10);
}
unsigned long get_top_of_ram(void)
{
uint32_t xdata = 0;
int xnvram_pos = 0xfc, xi;
- if (!acpi_is_wakeup_early())
+ if (acpi_get_sleep_type() != 3)
return 0;
for (xi = 0; xi<4; xi++) {
outb(xnvram_pos, BIOSRAM_INDEX);
@@ -744,6 +742,5 @@ unsigned long get_top_of_ram(void)
}
return (unsigned long) xdata;
}
-#endif
#endif
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
index 8ebc765..658e954 100644
--- a/src/southbridge/amd/sb700/lpc.c
+++ b/src/southbridge/amd/sb700/lpc.c
@@ -29,7 +29,6 @@
#include <pc80/isa-dma.h>
#include <arch/io.h>
#include <arch/ioapic.h>
-#include <arch/acpi.h>
#include <cbmem.h>
#include <cpu/amd/powernow.h>
#include "sb700.h"
@@ -80,19 +79,15 @@ static void lpc_init(device_t dev)
#endif
pci_write_config8(dev, 0x78, byte);
- /* hack, but the whole sb700 startup lacks any device which
- is doing the acpi init */
-#if CONFIG_HAVE_ACPI_RESUME
- {
- u16 tmp = inw(ACPI_PM1_CNT_BLK);
- acpi_slp_type = ((tmp & (7 << 10)) >> 10);
- printk(BIOS_DEBUG, "SLP_TYP type was %x\n", acpi_slp_type);
- }
-#endif
-
cmos_check_update_date();
}
+int acpi_get_sleep_type(void)
+{
+ u16 tmp = inw(ACPI_PM1_CNT_BLK);
+ return ((tmp & (7 << 10)) >> 10);
+}
+
void backup_top_of_ram(uint64_t ramtop)
{
u32 dword = (u32) ramtop;
diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c
index 2b488d9..24aa200 100644
--- a/src/southbridge/amd/sb800/early_setup.c
+++ b/src/southbridge/amd/sb800/early_setup.c
@@ -666,20 +666,18 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
return nvram_pos;
}
-#if CONFIG_HAVE_ACPI_RESUME
-int acpi_is_wakeup_early(void)
+int acpi_get_sleep_type(void)
{
u16 tmp;
tmp = inw(ACPI_PM1_CNT_BLK);
- printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp);
- return (((tmp & (7 << 10)) >> 10) == 3);
+ return ((tmp & (7 << 10)) >> 10);
}
unsigned long get_top_of_ram(void)
{
uint32_t xdata = 0;
int xnvram_pos = 0xfc, xi;
- if (!acpi_is_wakeup_early())
+ if (acpi_get_sleep_type() != 3)
return 0;
for (xi = 0; xi<4; xi++) {
outb(xnvram_pos, BIOSRAM_INDEX);
@@ -689,6 +687,5 @@ unsigned long get_top_of_ram(void)
}
return (unsigned long) xdata;
}
-#endif
#endif
diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c
index d236cfa..6341751 100644
--- a/src/southbridge/intel/i82371eb/smbus.c
+++ b/src/southbridge/intel/i82371eb/smbus.c
@@ -31,11 +31,6 @@
#include "i82371eb.h"
#include "smbus.h"
-#if CONFIG_HAVE_ACPI_RESUME
-extern u8 acpi_slp_type;
-int acpi_get_sleep_type(void);
-#endif
-
static void pwrmgt_enable(struct device *dev)
{
struct southbridge_intel_i82371eb_config *sb = dev->chip_info;
@@ -92,12 +87,6 @@ static void pwrmgt_enable(struct device *dev)
outw(0xffff, DEFAULT_PMBASE + GLBSTS);
outl(0xffffffff, DEFAULT_PMBASE + DEVSTS);
-#if CONFIG_HAVE_ACPI_RESUME
- /* this reads PMCNTRL, so we have to call it before writing the
- * default value */
- acpi_slp_type = acpi_get_sleep_type();
-#endif
-
/* set PMCNTRL default */
outw(SUS_TYP_S0|SCI_EN, DEFAULT_PMBASE + PMCNTRL);
}
diff --git a/src/southbridge/intel/i82371eb/wakeup.c b/src/southbridge/intel/i82371eb/wakeup.c
index dd4a28f..f9ca385 100644
--- a/src/southbridge/intel/i82371eb/wakeup.c
+++ b/src/southbridge/intel/i82371eb/wakeup.c
@@ -19,12 +19,11 @@
*/
#include <stdint.h>
+#include <arch/acpi.h>
#include <arch/io.h>
#include <console/console.h>
#include "i82371eb.h"
-int acpi_get_sleep_type(void);
-
/*
* Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142
*
diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c
index 7eba967..d41e0df 100644
--- a/src/southbridge/via/k8t890/early_car.c
+++ b/src/southbridge/via/k8t890/early_car.c
@@ -180,11 +180,9 @@ static inline int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
return nvram_pos;
}
-#if CONFIG_HAVE_ACPI_RESUME
unsigned long get_top_of_ram(void)
{
- if (!acpi_is_wakeup_early())
+ if (acpi_get_sleep_type() != 3)
return 0;
return (unsigned long) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM);
}
-#endif
diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c
index bb06322..b766bd7 100644
--- a/src/southbridge/via/vt8237r/early_smbus.c
+++ b/src/southbridge/via/vt8237r/early_smbus.c
@@ -330,8 +330,7 @@ void enable_rom_decode(void)
pci_write_config8(dev, 0x41, 0x7f);
}
-#if CONFIG_HAVE_ACPI_RESUME
-int acpi_is_wakeup_early(void)
+int acpi_get_sleep_type(void)
{
device_t dev;
u16 tmp;
@@ -354,7 +353,6 @@ int acpi_is_wakeup_early(void)
printk(BIOS_DEBUG, "%02x", tmp);
return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
}
-#endif
#if defined(__GNUC__)
void vt8237_early_spi_init(void)
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index 92eaa39..d3e3d32 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -244,10 +244,6 @@ static void setup_pm(device_t dev)
/* SCI is generated for RTC/pwrBtn/slpBtn. */
tmp = inw(VT8237R_ACPI_IO_BASE + 0x04);
-#if CONFIG_HAVE_ACPI_RESUME
- acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
- printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type);
-#endif
/* All SMI on, both IDE buses ON, PSON rising edge. */
outw(0x1, VT8237R_ACPI_IO_BASE + 0x2c);
@@ -258,6 +254,12 @@ static void setup_pm(device_t dev)
outw(tmp, VT8237R_ACPI_IO_BASE + 0x04);
}
+int acpi_get_sleep_type(void)
+{
+ u16 tmp = inw(VT8237R_ACPI_IO_BASE + 0x04);
+ return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
+}
+
static void vt8237r_init(struct device *dev)
{
u8 enables;
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